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comparison packages/hal/arm/aeb/current/include/hal_platform_setup.h @ 44:41bd4f3a90de ecos-sw-1999-10-08

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Merge from eCos master repository on 1999-10-08-07:47:04-BST
author jlarmour
date Fri, 08 Oct 1999 13:16:25 +0000
parents 443894e2e912
children 797268ecc331
comparison
equal deleted inserted replaced
43:3e1bfbe59ff6 44:41bd4f3a90de
41 // 41 //
42 //####DESCRIPTIONEND#### 42 //####DESCRIPTIONEND####
43 // 43 //
44 //===========================================================================*/ 44 //===========================================================================*/
45 45
46 // From <cyg/hal/hal_cache.h> Need to make that file assembly safe.
47 #define CYG_DEVICE_CCR 0xFFFFA400
48 #define CCR_I 0x08 // Invalidate mode
49
46 #if CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE==4096 50 #if CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE==4096
47 // Override default to a more sensible value 51 // Override default to a more sensible value
48 #undef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 52 #undef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
49 #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 2048 53 #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 2048
50 #endif 54 #endif
51 55
56 #ifdef CYGHWR_HAL_ARM_AEB_REVISION_C
57 // AEB rev C has 256kB of memory. Cache is working (set cachable)
58 #define AEB_SRAM .long 0xFFFFA008,0x00008000,0x00048000,0x00007c04
59 #define AEB_BAD .long 0xFFFFA00C,0x00048000,0x01000000,0x00000000
60 #else
61 // AEB rev B has 128kB of memory. Cache is broken (clear cachable)
62 #define AEB_SRAM .long 0xFFFFA008,0x00008000,0x00028000,0x00007804
63 #define AEB_BAD .long 0xFFFFA00C,0x00028000,0x01000000,0x00000000
64 #endif
65
52 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS 66 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
53 #define PLATFORM_SETUP1 \ 67 #define PLATFORM_SETUP1 \
68 ldr r1,=CYG_DEVICE_CCR ;\
69 mov r2,#CCR_I ;\
70 strb r2,[r1,#0] /* invalidate... */ ;\
71 mov r2,#0 ;\
72 strb r2,[r1,#0] /* and disable the cache. */ ;\
54 ldr r1,=segment_register_setups ;\ 73 ldr r1,=segment_register_setups ;\
55 10: ldr r2,[r1,#0] /* segment address */ ;\ 74 10: ldr r2,[r1,#0] /* segment address */ ;\
56 cmp r2,#0 ;\ 75 cmp r2,#0 ;\
57 beq 20f ;\ 76 beq 20f ;\
58 ldr r3,[r1,#4] /* segment start */ ;\ 77 ldr r3,[r1,#4] /* segment start */ ;\
62 ldr r3,[r1,#12] /* segment flags */ ;\ 81 ldr r3,[r1,#12] /* segment flags */ ;\
63 str r3,[r2,#0x40] ;\ 82 str r3,[r2,#0x40] ;\
64 add r1,r1,#16 /* next segment */ ;\ 83 add r1,r1,#16 /* next segment */ ;\
65 b 10b ;\ 84 b 10b ;\
66 segment_register_setups: ;\ 85 segment_register_setups: ;\
67 .long 0xFFFFA008,0x00008000,0x00028000,0x00007804 /* segment 2 */ ;\ 86 AEB_SRAM /* segment 2 */ ;\
68 .long 0xFFFFA00C,0x00028000,0x01000000,0x00000000 /* segment 3 */ ;\ 87 AEB_BAD /* segment 3 */ ;\
69 .long 0 ;\ 88 .long 0 ;\
70 20: 89 20:
71 #else 90 #else
72 #define PLATFORM_SETUP1 91 #define PLATFORM_SETUP1
73 #endif 92 #endif