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comparison packages/hal/arm/ebsa285/current/include/hal_platform_ints.h @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
parents
children 84e4bde58b26
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75:41bf073c0c32 76:435cced73e2f
1 #ifndef CYGONCE_HAL_PLATFORM_INTS_H
2 #define CYGONCE_HAL_PLATFORM_INTS_H
3 //==========================================================================
4 //
5 // hal_platform_ints.h
6 //
7 // HAL Interrupt and clock support
8 //
9 //==========================================================================
10 //####COPYRIGHTBEGIN####
11 //
12 // -------------------------------------------
13 // The contents of this file are subject to the Red Hat eCos Public License
14 // Version 1.1 (the "License"); you may not use this file except in
15 // compliance with the License. You may obtain a copy of the License at
16 // http://www.redhat.com/
17 //
18 // Software distributed under the License is distributed on an "AS IS"
19 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
20 // License for the specific language governing rights and limitations under
21 // the License.
22 //
23 // The Original Code is eCos - Embedded Configurable Operating System,
24 // released September 30, 1998.
25 //
26 // The Initial Developer of the Original Code is Red Hat.
27 // Portions created by Red Hat are
28 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
29 // All Rights Reserved.
30 // -------------------------------------------
31 //
32 //####COPYRIGHTEND####
33 //==========================================================================
34 //#####DESCRIPTIONBEGIN####
35 //
36 // Author(s): hmt
37 // Contributors: hmt
38 // Date: 1999-04-21
39 // Purpose: Define Interrupt support
40 // Description: The interrupt details for the EBSA285 are defined here.
41 // Usage:
42 // #include <cyg/hal/hal_platform_ints.h>
43 // ...
44 //
45 //
46 //####DESCRIPTIONEND####
47 //
48 //==========================================================================
49
50 #define CYGNUM_HAL_INTERRUPT_reserved0 0
51 #define CYGNUM_HAL_INTERRUPT_SOFT_IRQ 1
52 #define CYGNUM_HAL_INTERRUPT_SERIAL_RX 2
53 #define CYGNUM_HAL_INTERRUPT_SERIAL_TX 3
54 #define CYGNUM_HAL_INTERRUPT_TIMER_1 4
55 #define CYGNUM_HAL_INTERRUPT_TIMER_2 5
56 #define CYGNUM_HAL_INTERRUPT_TIMER_3 6
57 #define CYGNUM_HAL_INTERRUPT_TIMER_4 7
58 #define CYGNUM_HAL_INTERRUPT_IRQ_IN_0 8
59 #define CYGNUM_HAL_INTERRUPT_IRQ_IN_1 9
60 #define CYGNUM_HAL_INTERRUPT_IRQ_IN_2 10
61 #define CYGNUM_HAL_INTERRUPT_IRQ_IN_3 11
62 #define CYGNUM_HAL_INTERRUPT_XBUS_CS_0 12
63 #define CYGNUM_HAL_INTERRUPT_XBUS_CS_1 13
64 #define CYGNUM_HAL_INTERRUPT_XBUS_CS_2 14
65 #define CYGNUM_HAL_INTERRUPT_DOORBELL 15
66 #define CYGNUM_HAL_INTERRUPT_DMA_1 16
67 #define CYGNUM_HAL_INTERRUPT_DMA_2 17
68 #define CYGNUM_HAL_INTERRUPT_PCI_IRQ 18
69 #define CYGNUM_HAL_INTERRUPT_PMCSR 19
70 #define CYGNUM_HAL_INTERRUPT_reserved20 20
71 #define CYGNUM_HAL_INTERRUPT_reserved21 21
72 #define CYGNUM_HAL_INTERRUPT_BIST 22
73 #define CYGNUM_HAL_INTERRUPT_SERR 23
74 #define CYGNUM_HAL_INTERRUPT_SDRAM_PARITY 24
75 #define CYGNUM_HAL_INTERRUPT_I2O_POST 25
76 #define CYGNUM_HAL_INTERRUPT_reserved26 26
77 #define CYGNUM_HAL_INTERRUPT_DISCARD_TIMER 27
78 #define CYGNUM_HAL_INTERRUPT_PCI_DATA_PARITY 28
79 #define CYGNUM_HAL_INTERRUPT_PCI_MASTER_ABORT 29
80 #define CYGNUM_HAL_INTERRUPT_PCI_TARGET_ABORT 30
81 #define CYGNUM_HAL_INTERRUPT_PCI_PARITY_ERROR 31
82
83 #define CYGNUM_HAL_ISR_MIN 0
84 #define CYGNUM_HAL_ISR_MAX 31
85
86 #define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1)
87
88 // The vector used by the Real time clock
89 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER_3
90
91 // The vector used by hal_diag (for reception)
92 #define CYG_DIAG_DEV_INT CYGNUM_HAL_INTERRUPT_SERIAL_RX
93 // The vector used by gdb stubs (for reception)
94 #define CYG_GDB_DEV_INT CYGNUM_HAL_INTERRUPT_SERIAL_RX
95
96 // Do we want to poll in the default ISR for ^C interrupt chars?
97 #ifdef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
98 extern int hal_ctrlc_isr( CYG_ADDRWORD vector, CYG_ADDRWORD data);
99 #define CYGDBG_HAL_CTRLC_ISR( _V_, _D_ ) hal_ctrlc_isr( _V_, _D_ )
100 #endif
101
102 #endif // CYGONCE_HAL_PLATFORM_INTS_H