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comparison packages/hal/mn10300/am33/current/include/variant.inc @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
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children 6ed91473a1cd
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75:41bf073c0c32 76:435cced73e2f
1 #ifndef CYGONCE_HAL_VARIANT_INC
2 #define CYGONCE_HAL_VARIANT_INC
3 ##=============================================================================
4 ##
5 ## variant.inc
6 ##
7 ## AM33 assembler header file
8 ##
9 ##=============================================================================
10 #####COPYRIGHTBEGIN####
11 #
12 # -------------------------------------------
13 # The contents of this file are subject to the Red Hat eCos Public License
14 # Version 1.1 (the "License"); you may not use this file except in
15 # compliance with the License. You may obtain a copy of the License at
16 # http://www.redhat.com/
17 #
18 # Software distributed under the License is distributed on an "AS IS"
19 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
20 # License for the specific language governing rights and limitations under
21 # the License.
22 #
23 # The Original Code is eCos - Embedded Configurable Operating System,
24 # released September 30, 1998.
25 #
26 # The Initial Developer of the Original Code is Red Hat.
27 # Portions created by Red Hat are
28 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
29 # All Rights Reserved.
30 # -------------------------------------------
31 #
32 #####COPYRIGHTEND####
33 ##=============================================================================
34 #######DESCRIPTIONBEGIN####
35 ##
36 ## Author(s): nickg
37 ## Contributors: nickg
38 ## Date: 1999-04-06
39 ## Purpose: AM33 definitions.
40 ## Description: This file contains various definitions and macros that are
41 ## useful for writing assembly code for the AM33 CPU variant.
42 ## Usage:
43 ## #include <cyg/hal/variant.inc>
44 ## ...
45 ##
46 ##
47 ######DESCRIPTIONEND####
48 ##
49 ##=============================================================================
50
51 #include <pkgconf/hal.h>
52
53 .am33 # Enable AM33 instruction set
54
55 #include <cyg/hal/platform.inc>
56
57 #------------------------------------------------------------------------------
58 # Register definitions
59
60 #define NMICR 0xD4000000 // NMI control register
61 #define DCR 0xC0000030 // Debug control register
62 #define ISR 0xC0000034 // Interrupt control register
63 #define TBR 0xC0000024 // Trap Base Register
64
65 #define DCR_DE 0x0001 // DE bit in DCR
66
67 ##-----------------------------------------------------------------------------
68 ## Register addresses and initialization values
69
70 #define SDRAMCONFIG 0xDA000000
71
72 #define INIT_SDRAMCONFIG 0x0000002f
73
74 #------------------------------------------------------------------------------
75 # AM33 specific CPU initialization:
76
77 # Initialize CPU
78 .macro hal_cpu_init
79 # Set up the PSW
80 mov 0x00000700,d0
81 mov d0,epsw
82 # mov reset_vector,a0 # set TBR to reset address
83 # mov a0,(TBR)
84 .endm
85
86 #define CYGPKG_HAL_MN10300_CPU_INIT_DEFINED
87
88 #------------------------------------------------------------------------------
89 # CPU state save and restore macros
90
91 .macro hal_cpu_save_all
92 movm [all],(sp) # push all registers
93 .endm
94
95 .macro hal_cpu_load_all
96 movm (sp),[all] # pop regs
97 .endm
98
99 .macro hal_cpu_get_psw reg
100 mov epsw,\reg
101 .endm
102
103 .macro hal_cpu_set_psw reg
104 mov \reg,epsw
105 .endm
106
107 # Location of PC in saved context (HAL_SavedRegisters)
108 #define SAVED_CONTEXT_PC_OFFSET 104
109
110 #-----------------------------------------------------------------------------
111 # Clear the NMID bit in the epsw to allow NMIs to be delivered again.
112
113 .macro hal_cpu_clear_nmid
114 and 0xFFFDFFFF,epsw # clear NMID bit
115 .endm
116
117
118 #------------------------------------------------------------------------------
119 # MEMC macros.
120
121 #ifndef CYGPKG_HAL_MN10300_MEMC_DEFINED
122
123 .macro hal_memc_init
124 mov INIT_SDRAMCONFIG,d0
125 mov d0,(SDRAMCONFIG)
126 .endm
127
128 #define CYGPKG_HAL_MN10300_MEMC_DEFINED
129
130 #endif
131
132 ##-----------------------------------------------------------------------------
133 # Default interrupt decoding macros.
134
135 #ifndef CYGPKG_HAL_MN10300_INTC_DEFINED
136
137
138
139 # initialize all interrupts to disabled
140 .macro hal_intc_init
141 .endm
142
143 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
144
145 #define CYG_ISR_TABLE_SIZE 10
146
147 .macro hal_intc_decode dreg,areg,dreg1
148 mov _mn10300_interrupt_control,\areg
149 movhu (0x100,\areg),\dreg1 # dreg1 = IAGR
150 mov (0,a2),\dreg # dreg = vector priority
151 mov \dreg1,(0,a2) # store real vector in saved state
152 asl 2,\dreg # dreg = byte index of isr
153 add 12,\dreg # skip NMI vectors
154 .endm
155
156 #else
157
158 #define CYG_ISR_TABLE_SIZE 57
159
160 # decode the interrupt
161 .macro hal_intc_decode dreg,areg,dreg1
162 mov _mn10300_interrupt_control,\areg
163 movhu (0x100,\areg),\dreg # dreg = IAGR
164 mov \dreg,(0,a2) # store real vector in saved state
165 add 12,\dreg # skip NMI vectors
166 .endm
167
168 #endif
169
170 #define CYGPKG_HAL_MN10300_INTC_DEFINED
171
172 #endif
173
174
175 #------------------------------------------------------------------------------
176 # Diagnostics macros.
177
178 #ifndef CYGPKG_HAL_MN10300_DIAG_DEFINED
179
180 .macro hal_diag_init
181 .endm
182
183 .macro hal_diag_excpt_start
184 .endm
185
186 .macro hal_diag_intr_start
187 .endm
188
189 .macro hal_diag_restore
190 .endm
191
192 .macro hal_diag_led val
193 movm [d2,a2],(sp)
194 mov \val,d2
195 movm (sp),[d2,a2]
196 .endm
197
198
199 #define CYGPKG_HAL_MN10300_DIAG_DEFINED
200
201 #endif
202
203 #------------------------------------------------------------------------------
204 # Monitor initialization.
205
206 #ifndef CYGPKG_HAL_MN10300_MON_DEFINED
207
208 .macro hal_mon_init
209 hal_mon_init_vectors
210 hal_mon_init_vsr
211 .endm
212
213 #if defined(CYG_HAL_STARTUP_ROM)
214 .macro hal_mon_init_vectors
215 mov _mn10300_interrupt_vectors,a0
216 mov __hardware_vector_0,d0
217 movhu d0,(0,a0)
218 mov __hardware_vector_1,d0
219 movhu d0,(4,a0)
220 mov __hardware_vector_2,d0
221 movhu d0,(8,a0)
222 mov __hardware_vector_3,d0
223 movhu d0,(12,a0)
224 mov __hardware_vector_4,d0
225 movhu d0,(16,a0)
226 mov __hardware_vector_5,d0
227 movhu d0,(20,a0)
228 mov __hardware_vector_6,d0
229 movhu d0,(24,a0)
230 .endm
231 #else
232 .macro hal_mon_init_vectors
233 .endm
234 #endif
235
236 .extern nmi_vsr_trampoline
237 .extern nmi_sysef_trampoline
238
239 # init vsr table in SRAM where the ROM
240 # vectors the interrupts.
241
242 #if defined(CYG_HAL_STARTUP_ROM)
243 .macro hal_mon_init_vsr
244 mov _hal_vsr_table,a0
245 mov __default_interrupt_vsr,d0
246 mov d0,(0,a0)
247 mov d0,(4,a0)
248 mov d0,(8,a0)
249 mov d0,(12,a0)
250 mov d0,(16,a0)
251 mov d0,(20,a0)
252 mov d0,(24,a0)
253 mov nmi_vsr_trampoline,d0
254 mov d0,(28,a0)
255 mov __default_trap_vsr,d0
256 mov d0,(32,a0)
257 mov nmi_sysef_trampoline,d0
258 mov d0,(44,a0)
259 mov __default_nmi_vsr,d0
260 mov d0,(36,a0)
261 mov d0,(40,a0)
262 mov d0,(48,a0)
263 mov d0,(52,a0)
264 mov d0,(56,a0)
265 mov d0,(60,a0)
266 mov d0,(64,a0)
267 mov d0,(68,a0)
268 mov d0,(72,a0)
269 mov d0,(76,a0)
270 mov d0,(80,a0)
271 mov d0,(84,a0)
272 mov d0,(88,a0)
273 mov d0,(92,a0)
274 mov d0,(96,a0)
275 mov d0,(100,a0)
276 mov d0,(104,a0)
277 mov d0,(108,a0)
278 .endm
279 #elif defined(CYG_HAL_STARTUP_RAM)
280 .macro hal_mon_init_vsr
281 mov _hal_vsr_table,a0
282 mov __default_interrupt_vsr,d0
283 mov d0,(0,a0)
284 mov d0,(4,a0)
285 mov d0,(8,a0)
286 mov d0,(12,a0)
287 mov d0,(16,a0)
288 mov d0,(20,a0)
289 mov d0,(24,a0)
290 #if !(defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs))
291 mov nmi_vsr_trampoline,d0
292 mov d0,(28,a0)
293 mov nmi_sysef_trampoline,d0
294 mov d0,(44,a0)
295 #endif
296 mov __default_trap_vsr,d0
297 mov d0,(32,a0)
298 mov __default_nmi_vsr,d0
299 mov d0,(36,a0)
300 mov d0,(40,a0)
301 mov d0,(48,a0)
302 mov d0,(52,a0)
303 mov d0,(56,a0)
304 mov d0,(60,a0)
305 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
306 mov d0,(64,a0) # breakpoint VSR only if stubs included
307 #endif
308 mov d0,(68,a0)
309 mov d0,(72,a0)
310 mov d0,(76,a0)
311 mov d0,(80,a0)
312 mov d0,(84,a0)
313 mov d0,(88,a0)
314 mov d0,(92,a0)
315 mov d0,(96,a0)
316 mov d0,(100,a0)
317 mov d0,(104,a0)
318 mov d0,(108,a0)
319 .endm
320 #else
321 .macro hal_mon_init_vsr
322 .endif
323 #endif
324
325 #define CYGPKG_HAL_MN10300_MON_DEFINED
326
327 #define CYG_HAL_MN10300_VSR_TABLE_DEFINED
328
329 #endif
330
331
332
333 #------------------------------------------------------------------------------
334 #endif // ifndef CYGONCE_HAL_VARIANT_INC
335 # end of variant.inc