Mercurial > ecos
comparison packages/hal/arm/pid/current/include/hal_cache.h @ 2:443894e2e912 ecos-v1_2_1-release
Block commit of eCos version 1.2.1
| author | jlarmour |
|---|---|
| date | Tue, 11 May 1999 12:24:34 +0000 |
| parents | |
| children | c38311975d4f |
comparison
equal
deleted
inserted
replaced
| 1:72f549f0d891 | 2:443894e2e912 |
|---|---|
| 1 #ifndef CYGONCE_HAL_CACHE_H | |
| 2 #define CYGONCE_HAL_CACHE_H | |
| 3 | |
| 4 //============================================================================= | |
| 5 // | |
| 6 // hal_cache.h | |
| 7 // | |
| 8 // HAL cache control API | |
| 9 // | |
| 10 //============================================================================= | |
| 11 //####COPYRIGHTBEGIN#### | |
| 12 // | |
| 13 // ------------------------------------------- | |
| 14 // The contents of this file are subject to the Cygnus eCos Public License | |
| 15 // Version 1.0 (the "License"); you may not use this file except in | |
| 16 // compliance with the License. You may obtain a copy of the License at | |
| 17 // http://sourceware.cygnus.com/ecos | |
| 18 // | |
| 19 // Software distributed under the License is distributed on an "AS IS" | |
| 20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 21 // License for the specific language governing rights and limitations under | |
| 22 // the License. | |
| 23 // | |
| 24 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 25 // September 30, 1998. | |
| 26 // | |
| 27 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. | |
| 29 // ------------------------------------------- | |
| 30 // | |
| 31 //####COPYRIGHTEND#### | |
| 32 //============================================================================= | |
| 33 //#####DESCRIPTIONBEGIN#### | |
| 34 // | |
| 35 // Author(s): nickg, gthomas | |
| 36 // Contributors: nickg, gthomas | |
| 37 // Date: 1998-09-28 | |
| 38 // Purpose: Cache control API | |
| 39 // Description: The macros defined here provide the HAL APIs for handling | |
| 40 // cache control operations. | |
| 41 // Usage: | |
| 42 // #include <cyg/hal/hal_cache.h> | |
| 43 // ... | |
| 44 // | |
| 45 // | |
| 46 //####DESCRIPTIONEND#### | |
| 47 // | |
| 48 //============================================================================= | |
| 49 | |
| 50 #include <cyg/infra/cyg_type.h> | |
| 51 | |
| 52 //----------------------------------------------------------------------------- | |
| 53 // Cache dimensions | |
| 54 | |
| 55 // Data cache | |
| 56 #define HAL_DCACHE_SIZE 0 // Size of data cache in bytes | |
| 57 #define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line | |
| 58 #define HAL_DCACHE_WAYS 0 // Associativity of the cache | |
| 59 | |
| 60 // Instruction cache | |
| 61 #define HAL_ICACHE_SIZE 0 // Size of cache in bytes | |
| 62 #define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line | |
| 63 #define HAL_ICACHE_WAYS 0 // Associativity of the cache | |
| 64 | |
| 65 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) | |
| 66 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) | |
| 67 | |
| 68 //----------------------------------------------------------------------------- | |
| 69 // Global control of data cache | |
| 70 | |
| 71 // Enable the data cache | |
| 72 #define HAL_DCACHE_ENABLE() | |
| 73 | |
| 74 // Disable the data cache | |
| 75 #define HAL_DCACHE_DISABLE() | |
| 76 | |
| 77 // Invalidate the entire cache | |
| 78 #define HAL_DCACHE_INVALIDATE_ALL() | |
| 79 | |
| 80 // Synchronize the contents of the cache with memory. | |
| 81 #define HAL_DCACHE_SYNC() | |
| 82 | |
| 83 // Purge contents of data cache | |
| 84 #define HAL_DCACHE_PURGE_ALL() | |
| 85 | |
| 86 // Set the data cache refill burst size | |
| 87 //#define HAL_DCACHE_BURST_SIZE(_size_) | |
| 88 | |
| 89 // Set the data cache write mode | |
| 90 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) | |
| 91 | |
| 92 //#define HAL_DCACHE_WRITETHRU_MODE 0 | |
| 93 //#define HAL_DCACHE_WRITEBACK_MODE 1 | |
| 94 | |
| 95 // Load the contents of the given address range into the data cache | |
| 96 // and then lock the cache so that it stays there. | |
| 97 //#define HAL_DCACHE_LOCK(_base_, _size_) | |
| 98 | |
| 99 // Undo a previous lock operation | |
| 100 //#define HAL_DCACHE_UNLOCK(_base_, _size_) | |
| 101 | |
| 102 // Unlock entire cache | |
| 103 //#define HAL_DCACHE_UNLOCK_ALL() | |
| 104 | |
| 105 //----------------------------------------------------------------------------- | |
| 106 // Data cache line control | |
| 107 | |
| 108 // Allocate cache lines for the given address range without reading its | |
| 109 // contents from memory. | |
| 110 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) | |
| 111 | |
| 112 // Write dirty cache lines to memory and invalidate the cache entries | |
| 113 // for the given address range. | |
| 114 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) | |
| 115 | |
| 116 // Invalidate cache lines in the given range without writing to memory. | |
| 117 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) | |
| 118 | |
| 119 // Write dirty cache lines to memory for the given address range. | |
| 120 //#define HAL_DCACHE_STORE( _base_ , _size_ ) | |
| 121 | |
| 122 // Preread the given range into the cache with the intention of reading | |
| 123 // from it later. | |
| 124 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) | |
| 125 | |
| 126 // Preread the given range into the cache with the intention of writing | |
| 127 // to it later. | |
| 128 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) | |
| 129 | |
| 130 // Allocate and zero the cache lines associated with the given range. | |
| 131 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) | |
| 132 | |
| 133 //----------------------------------------------------------------------------- | |
| 134 // Global control of Instruction cache | |
| 135 | |
| 136 // Enable the instruction cache | |
| 137 #define HAL_ICACHE_ENABLE() | |
| 138 | |
| 139 // Disable the instruction cache | |
| 140 #define HAL_ICACHE_DISABLE() | |
| 141 | |
| 142 // Invalidate the entire cache | |
| 143 #define HAL_ICACHE_INVALIDATE_ALL() | |
| 144 | |
| 145 // Synchronize the contents of the cache with memory. | |
| 146 #define HAL_ICACHE_SYNC() | |
| 147 | |
| 148 // Set the instruction cache refill burst size | |
| 149 //#define HAL_ICACHE_BURST_SIZE(_size_) | |
| 150 | |
| 151 // Load the contents of the given address range into the instruction cache | |
| 152 // and then lock the cache so that it stays there. | |
| 153 //#define HAL_ICACHE_LOCK(_base_, _size_) | |
| 154 | |
| 155 // Undo a previous lock operation | |
| 156 //#define HAL_ICACHE_UNLOCK(_base_, _size_) | |
| 157 | |
| 158 // Unlock entire cache | |
| 159 //#define HAL_ICACHE_UNLOCK_ALL() | |
| 160 | |
| 161 //----------------------------------------------------------------------------- | |
| 162 // Instruction cache line control | |
| 163 | |
| 164 // Invalidate cache lines in the given range without writing to memory. | |
| 165 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) | |
| 166 | |
| 167 //----------------------------------------------------------------------------- | |
| 168 #endif // ifndef CYGONCE_HAL_CACHE_H | |
| 169 // End of hal_cache.h |
