Mercurial > ecos

comparison packages/hal/mips/arch/current/include/mips-regs.h @ 2:443894e2e912 ecos-v1_2_1-release

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Block commit of eCos version 1.2.1
author jlarmour
date Tue, 11 May 1999 12:24:34 +0000
parents 3111d98ba7b3
children 4741a3c3496a
comparison
equal deleted inserted replaced
1:72f549f0d891 2:443894e2e912
1 /* mips-regs.h - register defines for MIPS processors 1 /* mips-regs.h - register defines for MIPS processors
2 * 2 *
3 * Copyright (c) 1998 Cygnus Support 3 * Copyright (c) 1998 Cygnus Solutions
4 * 4 *
5 * The authors hereby grant permission to use, copy, modify, distribute, 5 * The authors hereby grant permission to use, copy, modify, distribute,
6 * and license this software and its documentation for any purpose, provided 6 * and license this software and its documentation for any purpose, provided
7 * that existing copyright notices are retained in all copies and that this 7 * that existing copyright notices are retained in all copies and that this
8 * notice is included verbatim in any distributions. No written agreement, 8 * notice is included verbatim in any distributions. No written agreement,
11 * and need not follow the licensing terms described here, provided that 11 * and need not follow the licensing terms described here, provided that
12 * the new terms are clearly indicated on the first page of each file where 12 * the new terms are clearly indicated on the first page of each file where
13 * they apply. 13 * they apply.
14 */ 14 */
15 15
16 #include <pkgconf/hal.h>
17
18 #ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
16 19
17 /* This value must agree with NUMREGS in mips-stub.h. */ 20 /* This value must agree with NUMREGS in mips-stub.h. */
18 21
19 #define NUM_REGS 90 22 #define NUM_REGS 90
20 23
24 #define REG_SIZE 4 27 #define REG_SIZE 4
25 #endif 28 #endif
26 29
27 /* General register names for assembly code. */ 30 /* General register names for assembly code. */
28 31
29 #define zero $0 32 #define zero $0
30 #define at $1 /* assembler temporary */ 33 #define at $1 /* assembler temporary */
31 #define v0 $2 /* value holders */ 34 #define v0 $2 /* value holders */
32 #define v1 $3 35 #define v1 $3
33 #define a0 $4 /* arguments */ 36 #define a0 $4 /* arguments */
34 #define a1 $5 37 #define a1 $5
35 #define a2 $6 38 #define a2 $6
36 #define a3 $7 39 #define a3 $7
37 #define t0 $8 /* temporaries */ 40 #define t0 $8 /* temporaries */
38 #define t1 $9 41 #define t1 $9
39 #define t2 $10 42 #define t2 $10
40 #define t3 $11 43 #define t3 $11
41 #define t4 $12 44 #define t4 $12
42 #define t5 $13 45 #define t5 $13
43 #define t6 $14 46 #define t6 $14
44 #define t7 $15 47 #define t7 $15
45 #define s0 $16 /* saved registers */ 48 #define s0 $16 /* saved registers */
46 #define s1 $17 49 #define s1 $17
47 #define s2 $18 50 #define s2 $18
48 #define s3 $19 51 #define s3 $19
49 #define s4 $20 52 #define s4 $20
50 #define s5 $21 53 #define s5 $21
51 #define s6 $22 54 #define s6 $22
52 #define s7 $23 55 #define s7 $23
53 #define t8 $24 /* temporaries */ 56 #define t8 $24 /* temporaries */
54 #define t9 $25 57 #define t9 $25
55 #define k0 $26 /* kernel registers */ 58 #define k0 $26 /* kernel registers */
56 #define k1 $27 59 #define k1 $27
57 #define gp $28 /* global pointer */ 60 #define gp $28 /* global pointer */
58 #define sp $29 /* stack pointer */ 61 #define sp $29 /* stack pointer */
59 #define s8 $30 /* saved register */ 62 #define s8 $30 /* saved register */
60 #define fp $30 /* frame pointer (obsolete usage) */ 63 #define fp $30 /* frame pointer (obsolete usage) */
61 #define ra $31 /* return address */ 64 #define ra $31 /* return address */
62 65
63 /* MIPS registers, numbered in the order in which gdb expects to see them. */ 66 /* MIPS registers, numbered in the order in which gdb expects to see them. */
64 #define ZERO 0 67 #define ZERO 0
65 #define AT 1 68 #define AT 1
66 #define V0 2 69 #define V0 2
67 #define V1 3 70 #define V1 3
68 #define A0 4 71 #define A0 4
69 #define A1 5 72 #define A1 5
70 #define A2 6 73 #define A2 6
71 #define A3 7 74 #define A3 7
72 75
73 #define T0 8 76 #define T0 8
74 #define T1 9 77 #define T1 9
75 #define T2 10 78 #define T2 10
76 #define T3 11 79 #define T3 11
77 #define T4 12 80 #define T4 12
78 #define T5 13 81 #define T5 13
79 #define T6 14 82 #define T6 14
80 #define T7 15 83 #define T7 15
81 84
82 #define S0 16 85 #define S0 16
83 #define S1 17 86 #define S1 17
84 #define S2 18 87 #define S2 18
85 #define S3 19 88 #define S3 19
86 #define S4 20 89 #define S4 20
87 #define S5 21 90 #define S5 21
88 #define S6 22 91 #define S6 22
89 #define S7 23 92 #define S7 23
90 93
91 #define T8 24 94 #define T8 24
92 #define T9 25 95 #define T9 25
93 #define K0 26 96 #define K0 26
94 #define K1 27 97 #define K1 27
95 #define GP 28 98 #define GP 28
96 #define SP 29 99 #define SP 29
97 #define S8 30 100 #define S8 30
98 #define RA 31 101 #define RA 31
99 102
100 #define SR 32 103 #define SR 32
101 #define LO 33 104 #define LO 33
102 #define HI 34 105 #define HI 34
103 #define BAD_VA 35 106 #define BAD_VA 35
104 #define CAUSE 36 107 #define CAUSE 36
105 #define PC 37 108 #define PC 37
106 109
107 /* System Control Coprocessor (CP0) exception processing registers */ 110 /* System Control Coprocessor (CP0) exception processing registers */
108 #define C0_CONTEXT $4 /* Context */ 111 #define C0_CONTEXT $4 /* Context */
109 #define C0_BADVADDR $8 /* Bad Virtual Address */ 112 #define C0_BADVADDR $8 /* Bad Virtual Address */
110 #define C0_COUNT $9 /* Count */ 113 #define C0_COUNT $9 /* Count */
111 #define C0_COMPARE $11 /* Compare */ 114 #define C0_COMPARE $11 /* Compare */
112 #define C0_STATUS $12 /* Processor Status */ 115 #define C0_STATUS $12 /* Processor Status */
113 #define C0_CAUSE $13 /* Exception Cause */ 116 #define C0_CAUSE $13 /* Exception Cause */
114 #define C0_EPC $14 /* Exception PC */ 117 #define C0_EPC $14 /* Exception PC */
115 #define C0_XCONTEXT $20 /* XContext */ 118 #define C0_XCONTEXT $20 /* XContext */
116 #define C0_ECC $26 /* ECC */ 119 #define C0_ECC $26 /* ECC */
117 #define C0_CACHEERR $27 /* CacheErr */ 120 #define C0_CACHEERR $27 /* CacheErr */
118 #define C0_ERROREPC $30 /* ErrorEPC */ 121 #define C0_ERROREPC $30 /* ErrorEPC */
119 122
120 /* Status register fields */ 123 /* Status register fields */
121 #define SR_CUMASK 0xf0000000 /* Coprocessor usable bits */ 124 #define SR_CUMASK 0xf0000000 /* Coprocessor usable bits */
122 #define SR_CU3 0x80000000 /* Coprocessor 3 usable */ 125 #define SR_CU3 0x80000000 /* Coprocessor 3 usable */
123 #define SR_CU2 0x40000000 /* coprocessor 2 usable */ 126 #define SR_CU2 0x40000000 /* coprocessor 2 usable */
124 #define SR_CU1 0x20000000 /* Coprocessor 1 usable */ 127 #define SR_CU1 0x20000000 /* Coprocessor 1 usable */
125 #define SR_CU0 0x10000000 /* Coprocessor 0 usable */ 128 #define SR_CU0 0x10000000 /* Coprocessor 0 usable */
126 129
127 #define SR_FR 0x04000000 /* Enable 32 floating-point registers */ 130 #define SR_FR 0x04000000 /* Enable 32 floating-point registers */
128 #define SR_RE 0x02000000 /* Reverse Endian in user mode */ 131 #define SR_RE 0x02000000 /* Reverse Endian in user mode */
129 132
130 #define SR_BEV 0x00400000 /* Bootstrap Exception Vector */ 133 #define SR_BEV 0x00400000 /* Bootstrap Exception Vector */
131 #define SR_TS 0x00200000 /* TLB shutdown (reserved on R4600) */ 134 #define SR_TS 0x00200000 /* TLB shutdown (reserved on R4600) */
132 #define SR_SR 0x00100000 /* Soft Reset */ 135 #define SR_SR 0x00100000 /* Soft Reset */
133 136
134 #define SR_CH 0x00040000 /* Cache Hit */ 137 #define SR_CH 0x00040000 /* Cache Hit */
135 #define SR_CE 0x00020000 /* ECC register modifies check bits */ 138 #define SR_CE 0x00020000 /* ECC register modifies check bits */
136 #define SR_DE 0x00010000 /* Disable cache errors */ 139 #define SR_DE 0x00010000 /* Disable cache errors */
137 140
138 #define SR_IMASK 0x0000ff00 /* Interrupt Mask */ 141 #define SR_IMASK 0x0000ff00 /* Interrupt Mask */
139 #define SR_IMASK8 0x00000000 /* Interrupt Mask level=8 */ 142 #define SR_IMASK8 0x00000000 /* Interrupt Mask level=8 */
140 #define SR_IMASK7 0x00008000 /* Interrupt Mask level=7 */ 143 #define SR_IMASK7 0x00008000 /* Interrupt Mask level=7 */
141 #define SR_IMASK6 0x0000c000 /* Interrupt Mask level=6 */ 144 #define SR_IMASK6 0x0000c000 /* Interrupt Mask level=6 */
142 #define SR_IMASK5 0x0000e000 /* Interrupt Mask level=5 */ 145 #define SR_IMASK5 0x0000e000 /* Interrupt Mask level=5 */
143 #define SR_IMASK4 0x0000f000 /* Interrupt Mask level=4 */ 146 #define SR_IMASK4 0x0000f000 /* Interrupt Mask level=4 */
144 #define SR_IMASK3 0x0000f800 /* Interrupt Mask level=3 */ 147 #define SR_IMASK3 0x0000f800 /* Interrupt Mask level=3 */
145 #define SR_IMASK2 0x0000fc00 /* Interrupt Mask level=2 */ 148 #define SR_IMASK2 0x0000fc00 /* Interrupt Mask level=2 */
146 #define SR_IMASK1 0x0000fe00 /* Interrupt Mask level=1 */ 149 #define SR_IMASK1 0x0000fe00 /* Interrupt Mask level=1 */
147 #define SR_IMASK0 0x0000ff00 /* Interrupt Mask level=0 */ 150 #define SR_IMASK0 0x0000ff00 /* Interrupt Mask level=0 */
148 151
149 #define SR_IBIT8 0x00008000 /* (Intr5) */ 152 #define SR_IBIT8 0x00008000 /* (Intr5) */
150 #define SR_IBIT7 0x00004000 /* (Intr4) */ 153 #define SR_IBIT7 0x00004000 /* (Intr4) */
151 #define SR_IBIT6 0x00002000 /* (Intr3) */ 154 #define SR_IBIT6 0x00002000 /* (Intr3) */
152 #define SR_IBIT5 0x00001000 /* (Intr2) */ 155 #define SR_IBIT5 0x00001000 /* (Intr2) */
153 #define SR_IBIT4 0x00000800 /* (Intr1) */ 156 #define SR_IBIT4 0x00000800 /* (Intr1) */
154 #define SR_IBIT3 0x00000400 /* (Intr0) */ 157 #define SR_IBIT3 0x00000400 /* (Intr0) */
155 #define SR_IBIT2 0x00000200 /* (Software Interrupt 1) */ 158 #define SR_IBIT2 0x00000200 /* (Software Interrupt 1) */
156 #define SR_IBIT1 0x00000100 /* (Software Interrupt 0) */ 159 #define SR_IBIT1 0x00000100 /* (Software Interrupt 0) */
157 160
158 #define SR_KX 0x00000080 /* xtlb in kernel mode */ 161 #define SR_KX 0x00000080 /* xtlb in kernel mode */
159 #define SR_SX 0x00000040 /* mips3 & xtlb in supervisor mode */ 162 #define SR_SX 0x00000040 /* mips3 & xtlb in supervisor mode */
160 #define SR_UX 0x00000020 /* mips3 & xtlb in user mode */ 163 #define SR_UX 0x00000020 /* mips3 & xtlb in user mode */
161 164
162 #define SR_KSU_MASK 0x00000018 /* ksu mode mask */ 165 #define SR_KSU_MASK 0x00000018 /* ksu mode mask */
163 #define SR_KSU_USER 0x00000010 /* user mode */ 166 #define SR_KSU_USER 0x00000010 /* user mode */
164 #define SR_KSU_SUPV 0x00000008 /* supervisor mode */ 167 #define SR_KSU_SUPV 0x00000008 /* supervisor mode */
165 #define SR_KSU_KERN 0x00000000 /* kernel mode */ 168 #define SR_KSU_KERN 0x00000000 /* kernel mode */
166 169
167 #define SR_ERL 0x00000004 /* error level */ 170 #define SR_ERL 0x00000004 /* error level */
168 #define SR_EXL 0x00000002 /* exception level */ 171 #define SR_EXL 0x00000002 /* exception level */
169 #define SR_IE 0x00000001 /* interrupt enable */ 172 #define SR_IE 0x00000001 /* interrupt enable */
170 173
171 /* Cause register fields */ 174 /* Cause register fields */
172 #define CAUSE_BD 0x80000000 /* Branch Delay */ 175 #define CAUSE_BD 0x80000000 /* Branch Delay */
173 #define CAUSE_CEMASK 0x30000000 /* Coprocessor Error */ 176 #define CAUSE_CEMASK 0x30000000 /* Coprocessor Error */
174 #define CAUSE_CESHIFT 28 /* Right justify CE */ 177 #define CAUSE_CESHIFT 28 /* Right justify CE */
175 #define CAUSE_IPMASK 0x0000ff00 /* Interrupt Pending */ 178 #define CAUSE_IPMASK 0x0000ff00 /* Interrupt Pending */
176 #define CAUSE_IPSHIFT 8 /* Right justify IP */ 179 #define CAUSE_IPSHIFT 8 /* Right justify IP */
177 #define CAUSE_IP8 0x00008000 /* (Intr5) */ 180 #define CAUSE_IP8 0x00008000 /* (Intr5) */
178 #define CAUSE_IP7 0x00004000 /* (Intr4) */ 181 #define CAUSE_IP7 0x00004000 /* (Intr4) */
179 #define CAUSE_IP6 0x00002000 /* (Intr3) */ 182 #define CAUSE_IP6 0x00002000 /* (Intr3) */
180 #define CAUSE_IP5 0x00001000 /* (Intr2) */ 183 #define CAUSE_IP5 0x00001000 /* (Intr2) */
181 #define CAUSE_IP4 0x00000800 /* (Intr1) */ 184 #define CAUSE_IP4 0x00000800 /* (Intr1) */
182 #define CAUSE_IP3 0x00000400 /* (Intr0) */ 185 #define CAUSE_IP3 0x00000400 /* (Intr0) */
183 #define CAUSE_SW2 0x00000200 /* (Software Interrupt 1) */ 186 #define CAUSE_SW2 0x00000200 /* (Software Interrupt 1) */
184 #define CAUSE_SW1 0x00000100 /* (Software Interrupt 0) */ 187 #define CAUSE_SW1 0x00000100 /* (Software Interrupt 0) */
185 #define CAUSE_EXCMASK 0x0000007c /* Exception Code */ 188 #define CAUSE_EXCMASK 0x0000007c /* Exception Code */
186 #define CAUSE_EXCSHIFT 2 /* Right justify EXC */ 189 #define CAUSE_EXCSHIFT 2 /* Right justify EXC */
187 190
188 /* Exception Codes */ 191 /* Exception Codes */
189 #define EXC_INT 0 /* External interrupt */ 192 #define EXC_INT 0 /* External interrupt */
190 #define EXC_MOD 1 /* TLB modification exception */ 193 #define EXC_MOD 1 /* TLB modification exception */
191 #define EXC_TLBL 2 /* TLB miss (Load or Ifetch) */ 194 #define EXC_TLBL 2 /* TLB miss (Load or Ifetch) */
192 #define EXC_TLBS 3 /* TLB miss (Store) */ 195 #define EXC_TLBS 3 /* TLB miss (Store) */
193 #define EXC_ADEL 4 /* Address error (Load or Ifetch) */ 196 #define EXC_ADEL 4 /* Address error (Load or Ifetch) */
194 #define EXC_ADES 5 /* Address error (Store) */ 197 #define EXC_ADES 5 /* Address error (Store) */
195 #define EXC_IBE 6 /* Bus error (Ifetch) */ 198 #define EXC_IBE 6 /* Bus error (Ifetch) */
196 #define EXC_DBE 7 /* Bus error (data load or store) */ 199 #define EXC_DBE 7 /* Bus error (data load or store) */
197 #define EXC_SYS 8 /* System call */ 200 #define EXC_SYS 8 /* System call */
198 #define EXC_BP 9 /* Break point */ 201 #define EXC_BP 9 /* Break point */
199 #define EXC_RI 10 /* Reserved instruction */ 202 #define EXC_RI 10 /* Reserved instruction */
200 #define EXC_CPU 11 /* Coprocessor unusable */ 203 #define EXC_CPU 11 /* Coprocessor unusable */
201 #define EXC_OVF 12 /* Arithmetic overflow */ 204 #define EXC_OVF 12 /* Arithmetic overflow */
202 #define EXC_TRAP 13 /* Trap exception */ 205 #define EXC_TRAP 13 /* Trap exception */
203 #define EXC_FPE 15 /* Floating Point Exception */ 206 #define EXC_FPE 15 /* Floating Point Exception */
204 207
205 208 #endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS