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comparison packages/devs/serial/sh/cq7708/current/src/sh_sci_cq7708.inl @ 105:5a0cc6c243a9 ecos-sw-2000-06-30

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Merge from eCos master repository on 2000-06-30-08:18:49-BST
author jlarmour
date Fri, 30 Jun 2000 16:27:35 +0000
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104:ad66e26a9e7c 105:5a0cc6c243a9
1 //==========================================================================
2 //
3 // io/serial/sh/sh_sci_cq7708.c
4 //
5 // Serial I/O Interface Module definitions for SH3/CQ7708
6 //
7 //==========================================================================
8 //####COPYRIGHTBEGIN####
9 //
10 // -------------------------------------------
11 // The contents of this file are subject to the Red Hat eCos Public License
12 // Version 1.1 (the "License"); you may not use this file except in
13 // compliance with the License. You may obtain a copy of the License at
14 // http://www.redhat.com/
15 //
16 // Software distributed under the License is distributed on an "AS IS"
17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
18 // License for the specific language governing rights and limitations under
19 // the License.
20 //
21 // The Original Code is eCos - Embedded Configurable Operating System,
22 // released September 30, 1998.
23 //
24 // The Initial Developer of the Original Code is Red Hat.
25 // Portions created by Red Hat are
26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
27 // All Rights Reserved.
28 // -------------------------------------------
29 //
30 //####COPYRIGHTEND####
31 //==========================================================================
32 //#####DESCRIPTIONBEGIN####
33 //
34 // Author(s): jskov
35 // Contributors:jskov
36 // Date: 1999-06-16
37 // Purpose: Defines SCI serial resources for SH3/CQ7708.
38 // Description:
39 //
40 //####DESCRIPTIONEND####
41 //==========================================================================
42
43 // Controller bases in the SH3/CQ7708 (only one)
44 #define SH_SERIAL_SCI_BASE 0xfffffe80
45
46 // The SCI controller register layout on the SH3/CQ7708.
47 #define SCI_SCSMR 0 // serial mode register
48 #define SCI_SCBRR 2 // bit rate register
49 #define SCI_SCSCR 4 // serial control register
50 #define SCI_SCTDR 6 // transmit data register
51 #define SCI_SCSSR 8 // serial status register
52 #define SCI_SCRDR 10 // receive data register
53 #define SCI_SCSPTR -4 // serial port register
54
55 static sh_sci_info sh_serial_info = {CYGARC_REG_SCSPTR,
56 CYGNUM_HAL_INTERRUPT_SCI_ERI,
57 CYGNUM_HAL_INTERRUPT_SCI_RXI,
58 CYGNUM_HAL_INTERRUPT_SCI_TXI,
59 SH_SERIAL_SCI_BASE};
60
61 #if CYGNUM_IO_SERIAL_SH_CQ7708_SCI_BUFSIZE > 0
62 static unsigned char sh_serial_out_buf[CYGNUM_IO_SERIAL_SH_CQ7708_SCI_BUFSIZE];
63 static unsigned char sh_serial_in_buf[CYGNUM_IO_SERIAL_SH_CQ7708_SCI_BUFSIZE];
64
65 static SERIAL_CHANNEL_USING_INTERRUPTS(sh_serial_channel,
66 sh_serial_funs,
67 sh_serial_info,
68 CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_CQ7708_SCI_BAUD),
69 CYG_SERIAL_STOP_DEFAULT,
70 CYG_SERIAL_PARITY_DEFAULT,
71 CYG_SERIAL_WORD_LENGTH_DEFAULT,
72 CYG_SERIAL_FLAGS_DEFAULT,
73 &sh_serial_out_buf[0],
74 sizeof(sh_serial_out_buf),
75 &sh_serial_in_buf[0],
76 sizeof(sh_serial_in_buf)
77 );
78 #else
79 static SERIAL_CHANNEL(sh_serial_channel,
80 sh_serial_funs,
81 sh_serial_info,
82 CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SH_CQ7708_SCI_BAUD),
83 CYG_SERIAL_STOP_DEFAULT,
84 CYG_SERIAL_PARITY_DEFAULT,
85 CYG_SERIAL_WORD_LENGTH_DEFAULT,
86 CYG_SERIAL_FLAGS_DEFAULT
87 );
88 #endif
89
90 DEVTAB_ENTRY(sh_serial_io,
91 CYGDAT_IO_SERIAL_SH_CQ7708_SCI_NAME,
92 0, // Does not depend on a lower level interface
93 &cyg_io_serial_devio,
94 sh_serial_init,
95 sh_serial_lookup, // Serial driver may need initializing
96 &sh_serial_channel
97 );
98