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comparison packages/hal/arm/cl7211/current/include/hal_platform_setup.h @ 32:5af43b635655 ecos-sw-1999-08-18

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Merge from eCos master repository on 1999-08-18-15:20:01-BST
author jlarmour
date Wed, 18 Aug 1999 15:33:44 +0000
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children e97d78785e2d
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31:e8319549378c 32:5af43b635655
1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
3
4 /*=============================================================================
5 //
6 // hal_platform_setup.h
7 //
8 // Platform specific support for HAL (assembly code)
9 //
10 //=============================================================================
11 //####COPYRIGHTBEGIN####
12 //
13 // -------------------------------------------
14 // The contents of this file are subject to the Cygnus eCos Public License
15 // Version 1.0 (the "License"); you may not use this file except in
16 // compliance with the License. You may obtain a copy of the License at
17 // http://sourceware.cygnus.com/ecos
18 //
19 // Software distributed under the License is distributed on an "AS IS"
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
21 // License for the specific language governing rights and limitations under
22 // the License.
23 //
24 // The Original Code is eCos - Embedded Cygnus Operating System, released
25 // September 30, 1998.
26 //
27 // The Initial Developer of the Original Code is Cygnus. Portions created
28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
29 // -------------------------------------------
30 //
31 //####COPYRIGHTEND####
32 //=============================================================================
33 //#####DESCRIPTIONBEGIN####
34 //
35 // Author(s): gthomas
36 // Contributors: gthomas
37 // Date: 1999-04-21
38 // Purpose: Cirrus CL7211 platform specific support routines
39 // Description:
40 // Usage: #include <cyg/hal/hal_platform_setup.h>
41 //
42 //####DESCRIPTIONEND####
43 //
44 //===========================================================================*/
45
46 #include <pkgconf/system.h> // System-wide configuration info
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_cl7211.h> // Platform specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50
51 #define CYGHWR_HAL_ARM_HAS_MMU // This processor has an MMU
52
53 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS)
54
55 //
56 // Memory map - set up by ROM (GDB stubs)
57 //
58 // Region Logical Address Physical Address
59 // DRAM 0x00000000..0x00xFFFFF 0xC00x0000 (see below)
60 // Expansion 2 0x20000000 0x20000000
61 // Expansion 3 0x30000000 0x30000000
62 // PCMCIA 0 0x40000000 0x40000000
63 // PCMCIA 1 0x50000000 0x50000000
64 // SRAM 0x60000000..0x600007FF 0x60000000
65 // I/O 0x80000000 0x80000000
66 // MMU Tables 0xC00y0000
67 // LCD buffer 0xC0000000..0xC001FFFF 0xC0000000
68 // ROM 0xE0000000..0xEFFFFFFF 0x00000000
69 // ROM 0xF0000000..0xFFFFFFFF 0x10000000
70
71 #ifdef CYGHWR_HAL_ARM_CL7211_LCD_INSTALLED
72 #define MMU_BASE 0xC0020000
73 #define PTE_BASE 0xC0024000
74 #define LCD_BUFFER_SIZE 0x00020000
75 #else
76 #define MMU_BASE 0xC0000000
77 #define PTE_BASE 0xC0004000
78 #define LCD_BUFFER_SIZE 0x00000000
79 #endif
80 #if (CYGHWR_HAL_ARM_CL7211_DRAM_SIZE == 2)
81 #define MMU_TABLES_SIZE 0x4000+0x1000+0x1000 // RAM used for PTE entries
82 #define DRAM_LA_END 0x00200000-MMU_TABLES_SIZE
83 #elif (CYGHWR_HAL_ARM_CL7211_DRAM_SIZE == 16)
84 #define MMU_TABLES_SIZE 0x4000+0x4000+0x1000 // RAM used for PTE entries
85 #define DRAM_LA_END 0x01000000-MMU_TABLES_SIZE
86 #endif
87 #define DRAM_LA_START 0x00000000
88 #define DRAM_PA MMU_BASE+MMU_TABLES_SIZE
89 #define LCD_LA_START 0xC0000000
90 #define LCD_LA_END 0xC0020000
91 #define LCD_PA 0xC0000000
92 #define ROM0_LA_START 0xE0000000
93 #define ROM0_PA 0x00000000
94 #define ROM1_LA_START 0xF0000000
95 #define ROM1_LA_END 0x00000000
96 #define ROM1_PA 0x10000000
97 #define EXPANSION2_LA_START 0x20000000
98 #define EXPANSION2_PA 0x20000000
99 #define EXPANSION3_LA_START 0x30000000
100 #define EXPANSION3_PA 0x30000000
101 #define PCMCIA0_LA_START 0x40000000
102 #define PCMCIA0_PA 0x40000000
103 #define PCMCIA1_LA_START 0x50000000
104 #define PCMCIA1_PA 0x50000000
105 #define SRAM_LA_START 0x60000000
106 #define SRAM_LA_END 0x60001000
107 #define SRAM_PA 0x60000000
108 #define IO_LA_START 0x80000000
109 #define IO_LA_END 0x80003000
110 #define IO_PA 0x80000000
111
112 #if (CYGHWR_HAL_ARM_CL7211_DRAM_SIZE == 2)
113 // Note: The DRAM on this board is very irregular in that every
114 // other 256K piece is missing. E.g. only these [physical]
115 // addresses are valid:
116 // 0xC0000000..0xC003FFFF
117 // 0xC0080000..0xC00BFFFF
118 // 0xC0200000..0xC023FFFF Note the additional GAP!
119 // etc.
120 // 0xC0800000..0xC083FFFF Note the additional GAP!
121 // 0xC0880000..0xC08CFFFF
122 // 0xC0A00000..0xC0A3FFFF
123 // etc.
124 // The MMU mapping code takes this into consideration and creates
125 // a continuous logical map for the DRAM.
126 #define MAP_DRAM \
127 /* Map DRAM */ ;\
128 ldr r3,=DRAM_LA_START ;\
129 ldr r4,=DRAM_LA_END ;\
130 ldr r5,=DRAM_PA ;\
131 /* 0x00000000..0x000FFFFF */ ;\
132 mov r6,r2 /* Set up page table descriptor */ ;\
133 ldr r7,=MMU_L1_TYPE_Page ;\
134 orr r6,r6,r7 ;\
135 str r6,[r1],#4 /* Store PTE, update pointer */ ;\
136 10: mov r6,r5 /* Build page table entry */ ;\
137 ldr r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\
138 orr r6,r6,r7 ;\
139 ldr r7,=MMU_PAGE_SIZE ;\
140 str r6,[r2],#4 /* Next page */ ;\
141 add r3,r3,r7 ;\
142 add r5,r5,r7 ;\
143 ldr r8,=DRAM_LA_START+MMU_SECTION_SIZE ;\
144 cmp r3,r8 /* Done with first 1M? */ ;\
145 beq 20f ;\
146 ldr r7,=0x40000 /* Special check for 256K boundary */ ;\
147 and r7,r7,r5 ;\
148 cmp r7,#0 ;\
149 beq 10b ;\
150 add r5,r5,r7 /* Skip 256K hole */ ;\
151 ldr r7,=0x100000 ;\
152 and r7,r5,r7 ;\
153 beq 10b ;\
154 add r5,r5,r7 /* Nothing at 0xC0100000 */ ;\
155 ldr r7,=0x400000 /* Also nothing at 0xC0400000 */ ;\
156 and r7,r5,r7 ;\
157 beq 10b ;\
158 add r5,r5,r7 ;\
159 b 10b ;\
160 20: ;\
161 /* 0x00100000..0x001FFFFF */ ;\
162 mov r6,r2 /* Set up page table descriptor */ ;\
163 ldr r7,=MMU_L1_TYPE_Page ;\
164 orr r6,r6,r7 ;\
165 str r6,[r1],#4 /* Store PTE, update pointer */ ;\
166 10: mov r6,r5 /* Build page table entry */ ;\
167 ldr r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\
168 orr r6,r6,r7 ;\
169 ldr r7,=MMU_PAGE_SIZE ;\
170 str r6,[r2],#4 /* Next page */ ;\
171 add r3,r3,r7 ;\
172 cmp r3,r4 /* Done with first DRAM? */ ;\
173 beq 20f ;\
174 add r5,r5,r7 ;\
175 ldr r7,=0x40000 /* Special check for 256K boundary */ ;\
176 and r7,r7,r5 ;\
177 cmp r7,#0 ;\
178 beq 10b ;\
179 add r5,r5,r7 /* Skip 256K hole */ ;\
180 ldr r7,=0x100000 ;\
181 and r7,r5,r7 ;\
182 beq 10b ;\
183 add r5,r5,r7 /* Nothing at 0xC0300000 */ ;\
184 ldr r7,=0x400000 /* Also nothing at 0xC0400000 */ ;\
185 and r7,r5,r7 ;\
186 beq 10b ;\
187 add r5,r5,r7 ;\
188 b 10b ;\
189 20: ;
190 #elif (CYGHWR_HAL_ARM_CL7211_DRAM_SIZE == 16)
191 // The 16M board is arranged as:
192 // 0xC0000000..0xC07FFFFF
193 // 0xC1000000..0xC17FFFFF
194 #define MAP_DRAM \
195 /* Map DRAM */ ;\
196 ldr r3,=DRAM_LA_START ;\
197 ldr r4,=DRAM_LA_END ;\
198 ldr r5,=DRAM_PA ;\
199 /* 0xXXX00000..0xXXXFFFFF */ ;\
200 10: mov r6,r2 /* Set up page table descriptor */ ;\
201 ldr r7,=MMU_L1_TYPE_Page ;\
202 orr r6,r6,r7 ;\
203 str r6,[r1],#4 /* Store PTE, update pointer */ ;\
204 ldr r8,=MMU_SECTION_SIZE/MMU_PAGE_SIZE ;\
205 ldr r6,=DRAM_PA+0x00800000 /* Need to skip at 8M boundary */ ;\
206 cmp r5,r6 ;\
207 bne 15f ;\
208 ldr r5,=DRAM_PA+0x01000000 /* Next chunk of DRAM */ ;\
209 15: mov r6,r5 /* Build page table entry */ ;\
210 ldr r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\
211 orr r6,r6,r7 ;\
212 ldr r7,=MMU_PAGE_SIZE ;\
213 str r6,[r2],#4 /* Next page */ ;\
214 add r3,r3,r7 ;\
215 add r5,r5,r7 ;\
216 cmp r3,r4 /* End of DRAM? */ ;\
217 beq 20f ;\
218 sub r8,r8,#1 /* End of 1M section? */ ;\
219 cmp r8,#0 ;\
220 bne 15b /* Next page */ ;\
221 b 10b /* Next section */ ;\
222 20:
223 #else
224 #err Invalid DRAM size selected
225 #endif
226
227 #ifdef CYG_HAL_ARM_CL7111 // CL7111, 710 processor
228 #define MMU_INITIALIZE \
229 ldr r1,=MMU_Control_Init ;\
230 mcr MMU_CP,0,r1,MMU_Control,c0 /* MMU off */ ;\
231 ldr r1,=MMU_BASE ;\
232 mcr MMU_CP,0,r1,MMU_Base,c0 ;\
233 mcr MMU_CP,0,r1,MMU_FlushTLB,c0,0 /* Invalidate TLB */ ;\
234 mcr MMU_CP,0,r1,MMU_FlushIDC,c0,0 /* Invalidate Caches */ ;\
235 ldr r1,=0xFFFFFFFF ;\
236 mcr MMU_CP,0,r1,MMU_DomainAccess,c0 ;\
237 ldr r2,=10f ;\
238 ldr r1,=MMU_Control_Init|MMU_Control_M ;\
239 mcr MMU_CP,0,r1,MMU_Control,c0 ;\
240 mov pc,r2 /* Change address spaces */ ;\
241 nop ;\
242 nop ;\
243 nop ;\
244 10:
245 #else // EP7211, 720T processor
246 #define MMU_INITIALIZE \
247 ldr r1,=MMU_Control_Init ;\
248 mcr MMU_CP,0,r1,MMU_Control,c0 /* MMU off */ ;\
249 ldr r1,=MMU_BASE ;\
250 mcr MMU_CP,0,r1,MMU_Base,c0 ;\
251 mcr MMU_CP,0,r1,MMU_TLB,c7,0 /* Invalidate TLB - 720 style */ ;\
252 mcr MMU_CP,0,r1,MMU_FlushIDC,c0,0 /* Invalidate Caches */ ;\
253 ldr r1,=0xFFFFFFFF ;\
254 mcr MMU_CP,0,r1,MMU_DomainAccess,c0 ;\
255 ldr r2,=10f ;\
256 ldr r1,=MMU_Control_Init|MMU_Control_M ;\
257 mcr MMU_CP,0,r1,MMU_Control,c0 ;\
258 mov pc,r2 /* Change address spaces */ ;\
259 nop ;\
260 nop ;\
261 nop ;\
262 10:
263 #endif
264
265 #define PLATFORM_SETUP1 \
266 /* Initialize memory configuration */ ;\
267 ldr r1,=MEMCFG1 ;\
268 ldr r2,=0x8200A080 /* FIXME - what is this? */ ;\
269 str r2,[r1] ;\
270 ldr r1,=MEMCFG2 ;\
271 ldr r2,=0xFEFC0000 ;\
272 str r2,[r1] ;\
273 ldr r1,=DRFPR ;\
274 ldr r2,=0x81 /* DRAM refresh = 64KHz */ ;\
275 strb r2,[r1] ;\
276 /* Initialize MMU to create new memory map */ ;\
277 ldr r1,=MMU_BASE ;\
278 ldr r2,=PTE_BASE ;\
279 MAP_DRAM ;\
280 /* Nothing until PCMCIA0 */ ;\
281 ldr r3,=0x3FF /* Page tables need 2K boundary */ ;\
282 add r2,r2,r3 ;\
283 ldr r3,=~0x3FF ;\
284 and r2,r2,r3 ;\
285 ldr r3,=(DRAM_LA_END+0x000FFFFF)&0xFFF00000 ;\
286 ldr r4,=EXPANSION2_LA_START ;\
287 ldr r5,=MMU_L1_TYPE_Fault ;\
288 ldr r7,=MMU_SECTION_SIZE ;\
289 10: str r5,[r1],#4 ;\
290 add r3,r3,r7 ;\
291 cmp r3,r4 ;\
292 bne 10b ;\
293 /* EXPANSION2, EXNAPSION3, PCMCIA0, PCMCIA1 */ ;\
294 ldr r3,=EXPANSION2_LA_START ;\
295 ldr r4,=SRAM_LA_START ;\
296 ldr r5,=EXPANSION2_PA ;\
297 ldr r6,=MMU_L1_TYPE_Section|MMU_AP_Any ;\
298 ldr r7,=MMU_SECTION_SIZE ;\
299 10: orr r0,r5,r6 ;\
300 str r0,[r1],#4 ;\
301 add r5,r5,r7 ;\
302 add r3,r3,r7 ;\
303 cmp r3,r4 ;\
304 bne 10b ;\
305 /* SRAM */ ;\
306 ldr r3,=SRAM_LA_START ;\
307 ldr r4,=MMU_L1_TYPE_Page|MMU_DOMAIN(0) ;\
308 orr r4,r4,r2 ;\
309 str r4,[r1],#4 ;\
310 ldr r4,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\
311 orr r4,r3,r4 ;\
312 str r4,[r2],#4 ;\
313 ldr r3,=SRAM_LA_START+MMU_PAGE_SIZE ;\
314 ldr r4,=SRAM_LA_START+MMU_SECTION_SIZE ;\
315 ldr r5,=MMU_L2_TYPE_Fault ;\
316 ldr r7,=MMU_PAGE_SIZE ;\
317 10: str r5,[r2],#4 ;\
318 add r3,r3,r7 ;\
319 cmp r3,r4 ;\
320 bne 10b ;\
321 ldr r4,=IO_LA_START ;\
322 ldr r5,=MMU_L1_TYPE_Fault ;\
323 ldr r7,=MMU_SECTION_SIZE ;\
324 20: str r5,[r1],#4 ;\
325 add r3,r3,r7 ;\
326 cmp r3,r4 ;\
327 bne 20b ;\
328 /* I/O */ ;\
329 ldr r3,=0x3FF /* Page tables need 2K boundary */ ;\
330 add r2,r2,r3 ;\
331 ldr r3,=~0x3FF ;\
332 and r2,r2,r3 ;\
333 ldr r4,=MMU_L1_TYPE_Page|MMU_DOMAIN(0) ;\
334 orr r4,r4,r2 ;\
335 str r4,[r1],#4 ;\
336 ldr r3,=IO_LA_START ;\
337 ldr r4,=IO_LA_END ;\
338 ldr r7,=MMU_PAGE_SIZE ;\
339 ldr r5,=IO_PA|MMU_L2_TYPE_Small|MMU_AP_All ;\
340 10: str r5,[r2],#4 ;\
341 add r5,r5,r7 ;\
342 add r3,r3,r7 ;\
343 cmp r3,r4 ;\
344 bne 10b ;\
345 ldr r4,=IO_LA_START+MMU_SECTION_SIZE ;\
346 ldr r5,=MMU_L2_TYPE_Fault ;\
347 ldr r7,=MMU_PAGE_SIZE ;\
348 10: str r5,[r2],#4 ;\
349 add r3,r3,r7 ;\
350 cmp r3,r4 ;\
351 bne 10b ;\
352 ldr r4,=LCD_LA_START ;\
353 ldr r5,=MMU_L1_TYPE_Fault ;\
354 ldr r7,=MMU_SECTION_SIZE ;\
355 20: str r5,[r1],#4 ;\
356 add r3,r3,r7 ;\
357 cmp r3,r4 ;\
358 bne 20b ;\
359 /* LCD Buffer & Unmapped DRAM (holes and all) */ ;\
360 ldr r3,=LCD_LA_START ;\
361 ldr r4,=ROM0_LA_START ;\
362 ldr r5,=LCD_PA ;\
363 ldr r6,=MMU_L1_TYPE_Section|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\
364 ldr r7,=MMU_SECTION_SIZE ;\
365 10: orr r0,r5,r6 ;\
366 str r0,[r1],#4 ;\
367 add r5,r5,r7 ;\
368 add r3,r3,r7 ;\
369 cmp r3,r4 ;\
370 bne 10b ;\
371 /* ROM0, ROM1 */ ;\
372 ldr r3,=ROM0_LA_START ;\
373 ldr r4,=ROM1_LA_END ;\
374 ldr r5,=ROM0_PA ;\
375 ldr r6,=MMU_L1_TYPE_Section|MMU_AP_Any|MMU_Cacheable ;\
376 ldr r7,=MMU_SECTION_SIZE ;\
377 10: orr r0,r5,r6 ;\
378 str r0,[r1],#4 ;\
379 add r5,r5,r7 ;\
380 add r3,r3,r7 ;\
381 cmp r3,r4 ;\
382 bne 10b ;\
383 /* Now initialize the MMU to use this new page table */ ;\
384 MMU_INITIALIZE
385
386 #else
387
388 #define PLATFORM_SETUP1
389 #endif
390
391
392 /*---------------------------------------------------------------------------*/
393 /* end of hal_platform_setup.h */
394 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */