Mercurial > ecos
comparison packages/hal/arm/integrator/current/include/hal_cache.h @ 195:67850532eebb
Merge from eCos master repository on 2001-11-02-06:43:03-GMT
| author | jlarmour |
|---|---|
| date | Fri, 02 Nov 2001 16:12:33 +0000 |
| parents | |
| children | e0c0827131d1 |
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| 194:feb0fcf83327 | 195:67850532eebb |
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| 1 #ifndef CYGONCE_HAL_CACHE_H | |
| 2 #define CYGONCE_HAL_CACHE_H | |
| 3 | |
| 4 //============================================================================= | |
| 5 // | |
| 6 // hal_cache.h | |
| 7 // | |
| 8 // HAL cache control API | |
| 9 // | |
| 10 //============================================================================= | |
| 11 //####COPYRIGHTBEGIN#### | |
| 12 // | |
| 13 // ------------------------------------------- | |
| 14 // The contents of this file are subject to the Red Hat eCos Public License | |
| 15 // Version 1.1 (the "License"); you may not use this file except in | |
| 16 // compliance with the License. You may obtain a copy of the License at | |
| 17 // http://www.redhat.com/ | |
| 18 // | |
| 19 // Software distributed under the License is distributed on an "AS IS" | |
| 20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 21 // License for the specific language governing rights and limitations under | |
| 22 // the License. | |
| 23 // | |
| 24 // The Original Code is eCos - Embedded Configurable Operating System, | |
| 25 // released September 30, 1998. | |
| 26 // | |
| 27 // The Initial Developer of the Original Code is Red Hat. | |
| 28 // Portions created by Red Hat are | |
| 29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. | |
| 30 // All Rights Reserved. | |
| 31 // ------------------------------------------- | |
| 32 // | |
| 33 //####COPYRIGHTEND#### | |
| 34 //============================================================================= | |
| 35 //#####DESCRIPTIONBEGIN#### | |
| 36 // | |
| 37 // Author(s): David A Rusling | |
| 38 // Contributors: Philippe Robin | |
| 39 // Date: November 7, 2000 | |
| 40 // Purpose: Cache control API | |
| 41 // Description: The macros defined here provide the HAL APIs for handling | |
| 42 // cache control operations. | |
| 43 // Usage: | |
| 44 // #include <cyg/hal/hal_cache.h> | |
| 45 // ... | |
| 46 // | |
| 47 // | |
| 48 //####DESCRIPTIONEND#### | |
| 49 // | |
| 50 //============================================================================= | |
| 51 | |
| 52 #include <cyg/infra/cyg_type.h> | |
| 53 | |
| 54 //----------------------------------------------------------------------------- | |
| 55 // Cache dimensions | |
| 56 | |
| 57 // Data cache | |
| 58 #define HAL_DCACHE_SIZE 0 // Size of data cache in bytes | |
| 59 #define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line | |
| 60 #define HAL_DCACHE_WAYS 0 // Associativity of the cache | |
| 61 | |
| 62 // Instruction cache | |
| 63 #define HAL_ICACHE_SIZE 0 // Size of cache in bytes | |
| 64 #define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line | |
| 65 #define HAL_ICACHE_WAYS 0 // Associativity of the cache | |
| 66 | |
| 67 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) | |
| 68 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) | |
| 69 | |
| 70 //----------------------------------------------------------------------------- | |
| 71 // Global control of data cache | |
| 72 | |
| 73 // Enable the data cache | |
| 74 #define HAL_DCACHE_ENABLE() | |
| 75 | |
| 76 // Disable the data cache | |
| 77 #define HAL_DCACHE_DISABLE() | |
| 78 | |
| 79 // Invalidate the entire cache | |
| 80 #define HAL_DCACHE_INVALIDATE_ALL() | |
| 81 | |
| 82 // Synchronize the contents of the cache with memory. | |
| 83 #define HAL_DCACHE_SYNC() | |
| 84 | |
| 85 // Query the state of the data cache | |
| 86 #define HAL_DCACHE_IS_ENABLED(_state_) 0 | |
| 87 | |
| 88 // Purge contents of data cache | |
| 89 #define HAL_DCACHE_PURGE_ALL() | |
| 90 | |
| 91 // Set the data cache refill burst size | |
| 92 //#define HAL_DCACHE_BURST_SIZE(_size_) | |
| 93 | |
| 94 // Set the data cache write mode | |
| 95 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) | |
| 96 | |
| 97 //#define HAL_DCACHE_WRITETHRU_MODE 0 | |
| 98 //#define HAL_DCACHE_WRITEBACK_MODE 1 | |
| 99 | |
| 100 // Load the contents of the given address range into the data cache | |
| 101 // and then lock the cache so that it stays there. | |
| 102 //#define HAL_DCACHE_LOCK(_base_, _size_) | |
| 103 | |
| 104 // Undo a previous lock operation | |
| 105 //#define HAL_DCACHE_UNLOCK(_base_, _size_) | |
| 106 | |
| 107 // Unlock entire cache | |
| 108 //#define HAL_DCACHE_UNLOCK_ALL() | |
| 109 | |
| 110 //----------------------------------------------------------------------------- | |
| 111 // Data cache line control | |
| 112 | |
| 113 // Allocate cache lines for the given address range without reading its | |
| 114 // contents from memory. | |
| 115 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) | |
| 116 | |
| 117 // Write dirty cache lines to memory and invalidate the cache entries | |
| 118 // for the given address range. | |
| 119 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) | |
| 120 | |
| 121 // Invalidate cache lines in the given range without writing to memory. | |
| 122 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) | |
| 123 | |
| 124 // Write dirty cache lines to memory for the given address range. | |
| 125 //#define HAL_DCACHE_STORE( _base_ , _size_ ) | |
| 126 | |
| 127 // Preread the given range into the cache with the intention of reading | |
| 128 // from it later. | |
| 129 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) | |
| 130 | |
| 131 // Preread the given range into the cache with the intention of writing | |
| 132 // to it later. | |
| 133 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) | |
| 134 | |
| 135 // Allocate and zero the cache lines associated with the given range. | |
| 136 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) | |
| 137 | |
| 138 //----------------------------------------------------------------------------- | |
| 139 // Global control of Instruction cache | |
| 140 | |
| 141 // Enable the instruction cache | |
| 142 #define HAL_ICACHE_ENABLE() | |
| 143 | |
| 144 // Disable the instruction cache | |
| 145 #define HAL_ICACHE_DISABLE() | |
| 146 | |
| 147 // Invalidate the entire cache | |
| 148 #define HAL_ICACHE_INVALIDATE_ALL() | |
| 149 | |
| 150 // Synchronize the contents of the cache with memory. | |
| 151 #define HAL_ICACHE_SYNC() | |
| 152 | |
| 153 // Set the instruction cache refill burst size | |
| 154 //#define HAL_ICACHE_BURST_SIZE(_size_) | |
| 155 | |
| 156 // Load the contents of the given address range into the instruction cache | |
| 157 // and then lock the cache so that it stays there. | |
| 158 //#define HAL_ICACHE_LOCK(_base_, _size_) | |
| 159 | |
| 160 // Undo a previous lock operation | |
| 161 //#define HAL_ICACHE_UNLOCK(_base_, _size_) | |
| 162 | |
| 163 // Unlock entire cache | |
| 164 //#define HAL_ICACHE_UNLOCK_ALL() | |
| 165 | |
| 166 //----------------------------------------------------------------------------- | |
| 167 // Instruction cache line control | |
| 168 | |
| 169 // Invalidate cache lines in the given range without writing to memory. | |
| 170 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) | |
| 171 | |
| 172 //----------------------------------------------------------------------------- | |
| 173 #endif // ifndef CYGONCE_HAL_CACHE_H | |
| 174 // End of hal_cache.h |
