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comparison packages/kernel/current/tests/kcache2.c @ 143:6b5f480c6929 ecos-sw-2000-12-08

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Merge from eCos master repository on 2000-12-08-02:09:36-GMT
author jlarmour
date Fri, 08 Dec 2000 03:30:06 +0000
parents bf00f99aec69
children 678094f34118
comparison
equal deleted inserted replaced
142:12eccf9656f3 143:6b5f480c6929
232 c = m[HAL_DCACHE_LINE_SIZE*2]; 232 c = m[HAL_DCACHE_LINE_SIZE*2];
233 } 233 }
234 #endif 234 #endif
235 235
236 // ------------------------------------------------------------------------- 236 // -------------------------------------------------------------------------
237 // Test of data cache line store. 237 // Test of data cache line store
238 // Just check that the macro compiles. 238 // o No semantic requirement.
239 // o Check that flushed data is written to memory.
240 // o Simple invocation check of macro.
239 #ifdef HAL_DCACHE_STORE 241 #ifdef HAL_DCACHE_STORE
240 static void test_dstore(void) 242 static void test_dstore(void)
241 { 243 {
242 volatile cyg_uint8* aligned_p; 244 volatile cyg_uint8* aligned_p;
243 cyg_int32 i; 245 cyg_int32 i;
258 260
259 aligned_p = (volatile cyg_uint8*) 261 aligned_p = (volatile cyg_uint8*)
260 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2]) 262 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
261 & ~(HAL_DCACHE_LINE_SIZE-1)); 263 & ~(HAL_DCACHE_LINE_SIZE-1));
262 264
263 aligned_p[0] = 42; 265 HAL_DISABLE_INTERRUPTS(oldints);
266
267 aligned_p[0] = 42 + aligned_p[1]; // Load causes cache to be used!
264 268
265 HAL_DCACHE_STORE(aligned_p, HAL_DCACHE_LINE_SIZE); 269 HAL_DCACHE_STORE(aligned_p, HAL_DCACHE_LINE_SIZE);
266 } 270
267 #endif 271 HAL_RESTORE_INTERRUPTS(oldints);
272
273 CYG_TEST_CHECK(42 == aligned_p[0],
274 "memory didn't contain flushed data");
275
276 HAL_DCACHE_INVALIDATE_ALL(); // Discard...
277
278 CYG_TEST_CHECK(42 == aligned_p[0],
279 "memory didn't contain flushed data after invalidate all");
280 }
281 #endif
282
283 // -------------------------------------------------------------------------
284 // Test of data cache total flush (sync).
285 // o No semantic requirement.
286 // o Check that flushed data is written to memory.
287 // o Simple invocation check of macro.
288 #ifdef HAL_DCACHE_LINE_SIZE // So we can find our way around memory
289 static void test_dsync(void)
290 {
291 volatile cyg_uint8* aligned_p;
292 cyg_int32 i;
293 register CYG_INTERRUPT_STATE oldints;
294
295 CYG_TEST_INFO("Data cache sync all");
296
297 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++)
298 m[i] = 0;
299
300 HAL_DISABLE_INTERRUPTS(oldints);
301 HAL_DCACHE_SYNC();
302 HAL_DCACHE_DISABLE();
303 HAL_DCACHE_SYNC();
304 HAL_DCACHE_INVALIDATE_ALL();
305 HAL_DCACHE_ENABLE();
306 HAL_RESTORE_INTERRUPTS(oldints);
307
308 aligned_p = (volatile cyg_uint8*)
309 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
310 & ~(HAL_DCACHE_LINE_SIZE-1));
311
312 HAL_DISABLE_INTERRUPTS(oldints);
313
314 aligned_p[0] = 42 + aligned_p[1]; // Load causes cache to be used!
315 aligned_p[HAL_DCACHE_LINE_SIZE] = 43 + aligned_p[HAL_DCACHE_LINE_SIZE + 1];
316
317 HAL_DCACHE_SYNC();
318
319 HAL_RESTORE_INTERRUPTS(oldints);
320
321 CYG_TEST_CHECK(42 == aligned_p[0],
322 "memory didn't contain flushed data");
323 CYG_TEST_CHECK(43 == aligned_p[HAL_DCACHE_LINE_SIZE],
324 "memory didn't contain flushed data next block");
325
326 HAL_DCACHE_INVALIDATE_ALL();
327
328 CYG_TEST_CHECK(42 == aligned_p[0],
329 "memory didn't contain flushed data after invalidate");
330 CYG_TEST_CHECK(43 == aligned_p[HAL_DCACHE_LINE_SIZE],
331 "memory didn't contain flushed data next block after invalidate");
332
333 HAL_DCACHE_DISABLE();
334
335 CYG_TEST_CHECK(42 == aligned_p[0],
336 "memory didn't contain flushed data after disable");
337 CYG_TEST_CHECK(43 == aligned_p[HAL_DCACHE_LINE_SIZE],
338 "memory didn't contain flushed data next block after disable");
339
340 HAL_DCACHE_ENABLE();
341 }
342 #endif // HAL_DCACHE_LINE_SIZE
268 343
269 // ------------------------------------------------------------------------- 344 // -------------------------------------------------------------------------
270 // Test of data cache line flush. 345 // Test of data cache line flush.
271 // o Requires write-back cache. 346 // o Requires write-back cache.
272 // o Check that flushed data is written to memory. 347 // o Check that flushed data is written to memory.
293 368
294 aligned_p = (volatile cyg_uint8*) 369 aligned_p = (volatile cyg_uint8*)
295 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2]) 370 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
296 & ~(HAL_DCACHE_LINE_SIZE-1)); 371 & ~(HAL_DCACHE_LINE_SIZE-1));
297 372
298 aligned_p[0] = 42; 373 HAL_DISABLE_INTERRUPTS(oldints);
299 aligned_p[HAL_DCACHE_LINE_SIZE] = 43; 374
375 aligned_p[0] = 42 + aligned_p[1]; // Load causes cache to be used!
376 aligned_p[HAL_DCACHE_LINE_SIZE] = 43 + aligned_p[HAL_DCACHE_LINE_SIZE + 1];
300 377
301 HAL_DCACHE_FLUSH(aligned_p, HAL_DCACHE_LINE_SIZE); 378 HAL_DCACHE_FLUSH(aligned_p, HAL_DCACHE_LINE_SIZE);
302 379
303 HAL_DCACHE_DISABLE(); 380 HAL_DCACHE_DISABLE();
381
382 HAL_RESTORE_INTERRUPTS(oldints);
304 383
305 CYG_TEST_CHECK(42 == aligned_p[0], 384 CYG_TEST_CHECK(42 == aligned_p[0],
306 "memory didn't contain flushed data"); 385 "memory didn't contain flushed data");
307 CYG_TEST_CHECK(0 == aligned_p[HAL_DCACHE_LINE_SIZE], 386 CYG_TEST_CHECK(0 == aligned_p[HAL_DCACHE_LINE_SIZE],
308 "flushed beyond region"); 387 "flushed beyond region");
309 388
310 HAL_DCACHE_ENABLE(); 389 HAL_DCACHE_ENABLE();
311 390 }
312 } 391 #endif
313 #endif 392
393 // -------------------------------------------------------------------------
394 // Test of data cache disable (which does NOT force contents out to RAM)
395 // o Requires write-back cache [so NOT invoked unconditionally]
396 // o Check that dirty data is not written to memory and is invalidated
397 // in the cache.
398 // o Simple invocation check of macro.
399 #ifdef HAL_DCACHE_QUERY_WRITE_MODE // only if we know this, can we test:
400 static void test_ddisable(void)
401 {
402 volatile cyg_uint8* aligned_p;
403 cyg_int32 i;
404 register CYG_INTERRUPT_STATE oldints;
405
406 CYG_TEST_INFO("Data cache gross disable");
407
408 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++)
409 m[i] = 0;
410
411 HAL_DISABLE_INTERRUPTS(oldints);
412 HAL_DCACHE_SYNC();
413 HAL_DCACHE_DISABLE();
414 HAL_DCACHE_SYNC();
415 HAL_DCACHE_INVALIDATE_ALL();
416 HAL_DCACHE_ENABLE();
417 HAL_RESTORE_INTERRUPTS(oldints);
418
419 aligned_p = (volatile cyg_uint8*)
420 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
421 & ~(HAL_DCACHE_LINE_SIZE-1));
422
423 HAL_DISABLE_INTERRUPTS(oldints);
424
425 aligned_p[0] = 43 + aligned_p[1]; // Load causes cache to be used!
426 aligned_p[HAL_DCACHE_LINE_SIZE-1] = 43;
427
428 aligned_p[HAL_DCACHE_LINE_SIZE] = 42 + aligned_p[HAL_DCACHE_LINE_SIZE + 1];
429
430 HAL_DCACHE_DISABLE();
431
432 HAL_RESTORE_INTERRUPTS(oldints);
433
434 CYG_TEST_CHECK(0 == aligned_p[0] &&
435 0 == aligned_p[HAL_DCACHE_LINE_SIZE-1],
436 "cache/memory contained invalidated data");
437 CYG_TEST_CHECK(0 == aligned_p[HAL_DCACHE_LINE_SIZE],
438 "next block contained invalidated data");
439
440 HAL_DCACHE_ENABLE();
441 }
442 #endif // def HAL_DCACHE_QUERY_WRITE_MODE
443
444 // -------------------------------------------------------------------------
445 // Test of data cache total invalidate.
446 // o Requires write-back cache.
447 // o Check that invalidated data is not written to memory and is invalidated
448 // in the cache.
449 // o Simple invocation check of macro.
450 #ifdef HAL_DCACHE_QUERY_WRITE_MODE // only if we know this, can we test:
451 #ifdef HAL_DCACHE_INVALIDATE_ALL
452 static void test_dinvalidate_all(void)
453 {
454 volatile cyg_uint8* aligned_p;
455 cyg_int32 i;
456 register CYG_INTERRUPT_STATE oldints;
457
458 CYG_TEST_INFO("Data cache invalidate all");
459
460 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++)
461 m[i] = 0;
462
463 HAL_DISABLE_INTERRUPTS(oldints);
464 HAL_DCACHE_SYNC();
465 HAL_DCACHE_DISABLE();
466 HAL_DCACHE_SYNC();
467 HAL_DCACHE_INVALIDATE_ALL();
468 HAL_DCACHE_ENABLE();
469 HAL_RESTORE_INTERRUPTS(oldints);
470
471 aligned_p = (volatile cyg_uint8*)
472 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
473 & ~(HAL_DCACHE_LINE_SIZE-1));
474
475 HAL_DISABLE_INTERRUPTS(oldints);
476
477 aligned_p[0] = 43 + aligned_p[1]; // Load causes cache to be used!
478 aligned_p[HAL_DCACHE_LINE_SIZE-1] = 43;
479
480 aligned_p[HAL_DCACHE_LINE_SIZE] = 42 + aligned_p[HAL_DCACHE_LINE_SIZE + 1];
481
482 HAL_DCACHE_INVALIDATE_ALL();
483
484 HAL_RESTORE_INTERRUPTS(oldints);
485
486 CYG_TEST_CHECK(0 == aligned_p[0] &&
487 0 == aligned_p[HAL_DCACHE_LINE_SIZE-1],
488 "cache/memory contained invalidated data");
489 CYG_TEST_CHECK(0 == aligned_p[HAL_DCACHE_LINE_SIZE],
490 "next block contained invalidated data");
491 }
492 #endif
493 #endif // def HAL_DCACHE_QUERY_WRITE_MODE
314 494
315 // ------------------------------------------------------------------------- 495 // -------------------------------------------------------------------------
316 // Test of data cache line invalidate. 496 // Test of data cache line invalidate.
317 // o Requires write-back cache. 497 // o Requires write-back cache.
318 // o Check that invalidated data is not written to memory and is invalidated 498 // o Check that invalidated data is not written to memory and is invalidated
319 // in the cache. 499 // in the cache.
320 // o Simple range check of macro. 500 // o Simple range check of macro.
501 #ifdef HAL_DCACHE_QUERY_WRITE_MODE // only if we know this, can we test:
321 #ifdef HAL_DCACHE_INVALIDATE 502 #ifdef HAL_DCACHE_INVALIDATE
322 static void test_dinvalidate(void) 503 static void test_dinvalidate(void)
323 { 504 {
324 volatile cyg_uint8* aligned_p; 505 volatile cyg_uint8* aligned_p;
325 cyg_int32 i; 506 cyg_int32 i;
340 521
341 aligned_p = (volatile cyg_uint8*) 522 aligned_p = (volatile cyg_uint8*)
342 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2]) 523 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
343 & ~(HAL_DCACHE_LINE_SIZE-1)); 524 & ~(HAL_DCACHE_LINE_SIZE-1));
344 525
345 aligned_p[0] = 43; 526 HAL_DISABLE_INTERRUPTS(oldints);
527
528 aligned_p[0] = 43 + aligned_p[1]; // Load causes cache to be used!
346 aligned_p[HAL_DCACHE_LINE_SIZE-1] = 43; 529 aligned_p[HAL_DCACHE_LINE_SIZE-1] = 43;
347 530
348 aligned_p[HAL_DCACHE_LINE_SIZE] = 42; 531 aligned_p[HAL_DCACHE_LINE_SIZE] = 42 + aligned_p[HAL_DCACHE_LINE_SIZE + 1];
349 532
350 HAL_DCACHE_INVALIDATE(aligned_p, HAL_DCACHE_LINE_SIZE); 533 HAL_DCACHE_INVALIDATE(aligned_p, HAL_DCACHE_LINE_SIZE);
534
535 HAL_RESTORE_INTERRUPTS(oldints);
351 536
352 CYG_TEST_CHECK(0 == aligned_p[0] && 537 CYG_TEST_CHECK(0 == aligned_p[0] &&
353 0 == aligned_p[HAL_DCACHE_LINE_SIZE-1], 538 0 == aligned_p[HAL_DCACHE_LINE_SIZE-1],
354 "cache/memory contained invalidated data"); 539 "cache/memory contained invalidated data");
355 CYG_TEST_CHECK(42 == aligned_p[HAL_DCACHE_LINE_SIZE], 540 CYG_TEST_CHECK(42 == aligned_p[HAL_DCACHE_LINE_SIZE],
356 "invalidated beyond range"); 541 "invalidated beyond range");
357 } 542
358 #endif 543 HAL_DCACHE_SYNC();
544 HAL_DCACHE_DISABLE();
545
546 CYG_TEST_CHECK(0 == aligned_p[0] &&
547 0 == aligned_p[HAL_DCACHE_LINE_SIZE-1],
548 "cache/memory contained invalidated data after SYNC/DIS");
549 CYG_TEST_CHECK(42 == aligned_p[HAL_DCACHE_LINE_SIZE],
550 "invalidated beyond range after SYNC/DIS");
551
552 HAL_DCACHE_ENABLE();
553 }
554 #endif
555 #endif // def HAL_DCACHE_QUERY_WRITE_MODE
359 556
360 // ------------------------------------------------------------------------- 557 // -------------------------------------------------------------------------
361 // Test of instruction cache locking. 558 // Test of instruction cache locking.
362 // o Time difference between repeatedly executing a bunch of instructions 559 // o Time difference between repeatedly executing a bunch of instructions
363 // with and without locking. 560 // with and without locking.
539 #endif // ifdef HAL_DCACHE_LOCK 736 #endif // ifdef HAL_DCACHE_LOCK
540 737
541 // ------------------------------------------------------------------------- 738 // -------------------------------------------------------------------------
542 static void entry0( cyg_addrword_t data ) 739 static void entry0( cyg_addrword_t data )
543 { 740 {
741 int numtests = 0;
544 #ifdef HAL_DCACHE_QUERY_WRITE_MODE 742 #ifdef HAL_DCACHE_QUERY_WRITE_MODE
545 int wmode; 743 int wmode;
546 #endif 744 #endif
547 #ifdef HAL_DCACHE_LOCK 745 #ifdef HAL_DCACHE_LOCK
548 time_dlock(); 746 time_dlock(); numtests++;
549 #endif 747 #endif
550 #ifdef HAL_ICACHE_LOCK 748 #ifdef HAL_ICACHE_LOCK
551 time_ilock(); 749 time_ilock(); numtests++;
750 #endif
751 #ifdef HAL_DCACHE_LINE_SIZE // So we can find our way around memory
752 test_dsync(); numtests++;
552 #endif 753 #endif
553 #ifdef HAL_DCACHE_STORE 754 #ifdef HAL_DCACHE_STORE
554 test_dstore(); 755 test_dstore(); numtests++;
555 #endif 756 #endif
556 #ifdef HAL_DCACHE_READ_HINT 757 #ifdef HAL_DCACHE_READ_HINT
557 test_dread_hint(); 758 test_dread_hint(); numtests++;
558 #endif 759 #endif
559 #ifdef HAL_DCACHE_WRITE_HINT 760 #ifdef HAL_DCACHE_WRITE_HINT
560 test_dwrite_hint(); 761 test_dwrite_hint(); numtests++;
561 #endif 762 #endif
562 #ifdef HAL_DCACHE_ZERO 763 #ifdef HAL_DCACHE_ZERO
563 test_dzero(); 764 test_dzero(); numtests++;
564 #endif 765 #endif
565 766
566 // The below tests only work on a copy-back cache. 767 // The below tests only work on a copy-back cache.
567 #ifdef HAL_DCACHE_QUERY_WRITE_MODE 768 #ifdef HAL_DCACHE_QUERY_WRITE_MODE
568 HAL_DCACHE_QUERY_WRITE_MODE( wmode ); 769 HAL_DCACHE_QUERY_WRITE_MODE( wmode );
569 770
570 if ( HAL_DCACHE_WRITEBACK_MODE == wmode ) { 771 if ( HAL_DCACHE_WRITEBACK_MODE == wmode ) {
772 test_ddisable(); numtests++;
773 #ifdef HAL_DCACHE_INVALIDATE
774 test_dinvalidate_all(); numtests++;
775 #endif
571 #ifdef HAL_DCACHE_FLUSH 776 #ifdef HAL_DCACHE_FLUSH
572 test_dflush(); 777 test_dflush(); numtests++;
573 #endif 778 #endif
574 #ifdef HAL_DCACHE_INVALIDATE 779 #ifdef HAL_DCACHE_INVALIDATE
575 test_dinvalidate(); 780 test_dinvalidate(); numtests++;
576 #endif 781 #endif
577 } 782 }
578 #endif // def HAL_DCACHE_QUERY_WRITE_MODE 783 #endif // def HAL_DCACHE_QUERY_WRITE_MODE
579 784 if ( numtests ) {
580 CYG_TEST_PASS_FINISH("End of test"); 785 CYG_TEST_PASS_FINISH("End of test");
786 }
787 else {
788 CYG_TEST_NA( "No applicable cache tests" );
789 }
581 } 790 }
582 791
583 // ------------------------------------------------------------------------- 792 // -------------------------------------------------------------------------
584 793
585 void kcache2_main( void ) 794 void kcache2_main( void )