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comparison packages/hal/mips/tx39/current/include/var_cache.h @ 18:7253dcc42a09 ecos-sw-1999-06-25

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Merge from eCos master repository on 1999-06-25-15:31:50-BST
author jlarmour
date Fri, 25 Jun 1999 08:28:05 +0000
parents d376b777e2ce
children 29bc183297e1
comparison
equal deleted inserted replaced
17:a658ec000d9f 18:7253dcc42a09
253 #define HAL_ICACHE_UNLOCK_ALL_DEFINED 253 #define HAL_ICACHE_UNLOCK_ALL_DEFINED
254 #define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0, HAL_ICACHE_SIZE) 254 #define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0, HAL_ICACHE_SIZE)
255 255
256 //----------------------------------------------------------------------------- 256 //-----------------------------------------------------------------------------
257 // Instruction cache line control 257 // Instruction cache line control
258 // On the TX39, the instruction cache must be disabled to use the index-invalidate
259 // cache operation.
260
261 // Invalidate the entire cache
262 // This uses the index-invalidate cache operation.
263 #define HAL_ICACHE_INVALIDATE_ALL_DEFINED
264 #define HAL_ICACHE_INVALIDATE_ALL() \
265 { \
266 register CYG_ADDRESS _baddr_ = 0x80000000; \
267 register CYG_ADDRESS _addr_ = 0x80000000; \
268 register CYG_WORD _state_; \
269 HAL_ICACHE_IS_ENABLED(_state_); \
270 HAL_ICACHE_DISABLE(); \
271 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
272 { \
273 asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); \
274 } \
275 if( _state_ ) HAL_ICACHE_ENABLE(); \
276 }
258 277
259 // Invalidate cache lines in the given range without writing to memory. 278 // Invalidate cache lines in the given range without writing to memory.
260 // This uses the index-invalidate cache operation since the TX39 does not 279 // This uses the index-invalidate cache operation since the TX39 does not
261 // have hit-invalidate on the instruction cache. 280 // have hit-invalidate on the instruction cache.
262 #define HAL_ICACHE_INVALIDATE_DEFINED 281 #define HAL_ICACHE_INVALIDATE_DEFINED
263 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \ 282 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
264 { \ 283 { \
265 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 284 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
266 register CYG_WORD _size_ = (_asize_); \ 285 register CYG_WORD _size_ = (_asize_); \
286 register CYG_WORD _state_; \
287 HAL_ICACHE_IS_ENABLED(_state_); \
267 HAL_ICACHE_DISABLE(); \ 288 HAL_ICACHE_DISABLE(); \
268 for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ 289 for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
269 { \ 290 { \
270 asm volatile ("cache 0,0(%0)" : : "r"(_addr_) ); \ 291 asm volatile ("cache 0,0(%0)" : : "r"(_addr_) ); \
271 } \ 292 } \
272 HAL_ICACHE_ENABLE(); \ 293 if( _state_ ) HAL_ICACHE_ENABLE(); \
273 } 294 }
274 295
275 #endif 296 #endif // CYGPKG_HAL_MIPS_TX3904
276 297
277 //----------------------------------------------------------------------------- 298 //-----------------------------------------------------------------------------
278 #endif // ifndef CYGONCE_IMP_CACHE_H 299 #endif // ifndef CYGONCE_IMP_CACHE_H
279 // End of imp_cache.h 300 // End of imp_cache.h