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comparison packages/hal/powerpc/quicc/current/src/quicc_smc1.c @ 101:c37d3a9e1b28 ecos-sw-2000-06-16

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Merge from eCos master repository on 2000-06-16-07:47:03-BST
author jlarmour
date Fri, 16 Jun 2000 16:43:59 +0000
parents 435cced73e2f
children 95f3e12a6327
comparison
equal deleted inserted replaced
100:991657282121 101:c37d3a9e1b28
54 // eCos headers decribing PowerQUICC: 54 // eCos headers decribing PowerQUICC:
55 #include <cyg/hal/quicc/ppc8xx.h> 55 #include <cyg/hal/quicc/ppc8xx.h>
56 56
57 #include <cyg/hal/quicc/quicc_smc1.h> 57 #include <cyg/hal/quicc/quicc_smc1.h>
58 58
59 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT 59 #if defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) \
60 || defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
60 #include <cyg/hal/hal_stub.h> // target_register_t 61 #include <cyg/hal/hal_stub.h> // target_register_t
61 #include <cyg/hal/hal_intr.h> // HAL_INTERRUPT_UNMASK(...) 62 #include <cyg/hal/hal_intr.h> // HAL_INTERRUPT_UNMASK(...)
63 #include <cyg/hal/hal_if.h> // Calling interface definitions
64 #include <cyg/hal/hal_misc.h> // Helper functions
65 #include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
62 #endif 66 #endif
63 67
64 #define UART_BIT_RATE(n) (((int)(CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/16)/n) 68 #define UART_BIT_RATE(n) (((int)(CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/16)/n)
65 #define UART_BAUD_RATE CYGNUM_HAL_QUICC_DIAG_BAUD 69 #define UART_BAUD_RATE CYGNUM_HAL_QUICC_DIAG_BAUD
66 70
179 * (Section 16.15.7.11) 183 * (Section 16.15.7.11)
180 */ 184 */
181 eppc->smc_regs[0].smc_smcmr = 0x4820; 185 eppc->smc_regs[0].smc_smcmr = 0x4820;
182 eppc->smc_regs[0].smc_smcmr = 0x4823; 186 eppc->smc_regs[0].smc_smcmr = 0x4823;
183 187
188 #ifndef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT // remove below
184 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT 189 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
185 HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_CPM_SMC1 ); 190 HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_CPM_SMC1 );
191 #endif
186 #endif 192 #endif
187 } 193 }
188 194
189 195
190 //#define UART_BUFSIZE 32 196 //#define UART_BUFSIZE 32
318 for (i = 0; i < 100000; i++); 324 for (i = 0; i < 100000; i++);
319 325
320 init_smc1_uart(); 326 init_smc1_uart();
321 } 327 }
322 328
329 #ifndef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT // the below should be removed
330
331
323 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT 332 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
324 // This ISR is called from the interrupt handler. This should only 333 // This ISR is called from the interrupt handler. This should only
325 // happen when there is no real serial driver, so the code shouldn't 334 // happen when there is no real serial driver, so the code shouldn't
326 // mess anything up. 335 // mess anything up.
327 int cyg_hal_gdb_isr( target_register_t pc ) 336 int cyg_hal_gdb_isr( target_register_t pc )
360 // Not caused by GDB. Call ISR proper. 369 // Not caused by GDB. Call ISR proper.
361 return 1; 370 return 1;
362 } 371 }
363 #endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT 372 #endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
364 373
374
375 #else // the below stays
376
377 #if defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) \
378 || defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
379
380 struct Hal_SavedRegisters *hal_saved_interrupt_state;
381
382 void
383 hal_ctrlc_isr_init(void)
384 {
385 HAL_INTERRUPT_UNMASK(CYGHWR_HAL_GDB_PORT_VECTOR);
386 }
387
388 cyg_uint32
389 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
390 {
391 EPPC *eppc = eppc_base();
392 struct cp_bufdesc *bd;
393 char ch;
394
395 eppc->smc_regs[0].smc_smce = 0xff;
396
397 /* rx buffer descriptors */
398 bd = (struct cp_bufdesc *)((char *)eppc_base() + Rxbd);
399
400 if ((bd->ctrl & QUICC_BD_CTL_Ready) == 0) {
401
402 // then there be a character waiting
403 ch = bd->buffer[0];
404 bd->length = 1;
405 bd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Wrap | QUICC_BD_CTL_Int;
406
407 if( cyg_hal_is_break( &ch , 1 ) )
408 cyg_hal_user_break( (CYG_ADDRWORD *)hal_saved_interrupt_state );
409
410 // Interrupt handled. Acknowledge it.
411 eppc->cpmi_cisr = 0x10;
412 return CYG_ISR_HANDLED;
413 }
414
415 eppc->cpmi_cisr = 0x10; // acknowledge the Rx event anyway
416 // in case it was left over from polled reception
417
418 // Not a serial interrupt
419 return 0;
420 }
421 #endif
422 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
423
365 #endif // CYGPKG_HAL_POWERPC_MPC860 424 #endif // CYGPKG_HAL_POWERPC_MPC860
366 // EOF quicc_smc1.c 425 // EOF quicc_smc1.c