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comparison packages/hal/powerpc/ppc60x/current/include/variant.inc @ 70:c5536bad4c24 ecos-sw-2000-02-11

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Merge from eCos master repository on 2000-02-11-15:46:40-GMT
author jlarmour
date Fri, 11 Feb 2000 16:47:32 +0000
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children 435cced73e2f
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69:9a9babddf7e7 70:c5536bad4c24
1 #ifndef CYGONCE_HAL_VARIANT_INC
2 #define CYGONCE_HAL_VARIANT_INC
3 ##=============================================================================
4 ##
5 ## variant.inc
6 ##
7 ## PPC60x family assembler header file
8 ##
9 ##=============================================================================
10 #####COPYRIGHTBEGIN####
11 #
12 # -------------------------------------------
13 # The contents of this file are subject to the Red Hat eCos Public License
14 # Version 1.1 (the "License"); you may not use this file except in
15 # compliance with the License. You may obtain a copy of the License at
16 # http://www.redhat.com/
17 #
18 # Software distributed under the License is distributed on an "AS IS"
19 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
20 # License for the specific language governing rights and limitations under
21 # the License.
22 #
23 # The Original Code is eCos - Embedded Configurable Operating System,
24 # released September 30, 1998.
25 #
26 # The Initial Developer of the Original Code is Red Hat.
27 # Portions created by Red Hat are
28 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
29 # All Rights Reserved.
30 # -------------------------------------------
31 #
32 #####COPYRIGHTEND####
33 ##=============================================================================
34 #######DESCRIPTIONBEGIN####
35 ##
36 ## Author(s): jskov
37 ## Contributors:jskov
38 ## Date: 2000-02-04
39 ## Purpose: MPC8xx family definitions.
40 ## Description: This file contains various definitions and macros that are
41 ## useful for writing assembly code for the PPC60x CPU family.
42 ## Usage:
43 ## #include <cyg/hal/variant.inc>
44 ## ...
45 ##
46 ##
47 ######DESCRIPTIONEND####
48 ##
49 ##=============================================================================
50
51 #include <pkgconf/hal.h>
52
53 #include <cyg/hal/ppc.inc>
54
55 ##-----------------------------------------------------------------------------
56 ## PPC60x defined vectors
57
58 .macro hal_extra_vectors
59 .endm
60
61 ##-----------------------------------------------------------------------------
62 ## PPC60x CPU initialization
63 ##
64 ## Initialize CPU to a post-reset state, ensuring the ground doesn''t
65 ## shift under us while we try to set things up.
66
67 .macro hal_cpu_init
68 # Set up MSR (disable MMU for now)
69 lwi r3,(CYG_MSR & ~(MSR_IR | MSR_DR))
70 sync
71 mtmsr r3
72 sync
73 .endm
74
75 ##-----------------------------------------------------------------------------
76 ## PPC60x monitor initialization
77
78 # FIXME: Need to generate these C/asm shared variables automatically
79 #define CYGNUM_HAL_VECTOR_INTERRUPT 5
80 #define CYGNUM_HAL_VECTOR_DECREMENTER 9
81 #define CYGNUM_HAL_VECTOR_NMI 31
82 #define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_NMI
83 #define CYGNUM_HAL_VSR_COUNT ( CYGNUM_HAL_VSR_MAX + 1 )
84
85
86 #ifndef CYGPKG_HAL_PPC_MON_DEFINED
87
88 #if defined(CYG_HAL_STARTUP_ROM) || \
89 ( defined(CYG_HAL_STARTUP_RAM) && \
90 !defined(CYGSEM_HAL_USE_ROM_MONITOR))
91
92 # If we are starting up from ROM, or we are starting in
93 # RAM and NOT using a ROM monitor, copy exception handler
94 # code to 0 and initialize the VSR table.
95
96 .macro hal_mon_init
97 # First copy exception vectors to RAM
98 lwi r3,rom_vectors # r3 = rom start
99 lwi r4,0 # r4 = ram start
100 lwi r5,rom_vectors_end # r5 = rom end
101 cmplw r3,r5 # skip if no vectors
102 beq 2f
103
104 subi r3,r3,4
105 subi r4,r4,4
106 subi r5,r5,4
107 1:
108 lwzu r0,4(r3) # get word from ROM
109 stwu r0,4(r4) # store in RAM
110 cmplw r3,r5 # compare
111 blt 1b # loop if not yet done
112 2:
113
114 # Initialize VSR table
115 # First fill with exception handlers
116 lwi r3,cyg_hal_default_exception_vsr
117 lwi r4,hal_vsr_table
118 subi r4,r4,4
119 li r5,CYGNUM_HAL_VSR_COUNT
120 1: stwu r3,4(r4)
121 subi r5,r5,1
122 cmpwi r5,0
123 bne 1b
124
125 # Then fill in the special vectors
126 lwi r3,cyg_hal_default_interrupt_vsr
127 lwi r4,hal_vsr_table
128 stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4)
129 stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4)
130 .endm
131
132 #elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
133
134 # Initialize the VSR table entries
135 # We only take control of the interrupt vectors,
136 # the rest are left to the ROM for now...
137
138 .macro hal_mon_init
139 lwi r3,cyg_hal_default_interrupt_vsr
140 lwi r4,hal_vsr_table
141 stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4)
142 stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4)
143 .endm
144
145
146 #else
147
148 .macro hal_mon_init
149
150 .endm
151
152 #endif
153
154
155 #define CYGPKG_HAL_PPC_MON_DEFINED
156
157 #endif // CYGPKG_HAL_PPC_MON_DEFINED
158
159
160 ##-----------------------------------------------------------------------------
161 ## Indicate that the ISR tables are defined in variant.S
162
163 ## Note: CYG_ISR_TABLE_SIZE must match CYG_ISR_COUNT defined in hal_intr.h.
164 #define CYG_ISR_TABLE_SIZE 2
165
166 #------------------------------------------------------------------------------
167 #endif // ifndef CYGONCE_HAL_VARIANT_INC
168 # end of variant.inc