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comparison packages/hal/mips/arch/current/include/hal_cache.h @ 10:d3fbcdfa1b2f ecos-sw-1999-05-29

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Merge from eCos master repository on 1999-05-29-00:13:11-BST
author jlarmour
date Fri, 28 May 1999 16:43:09 +0000
parents d376b777e2ce
children 7253dcc42a09
comparison
equal deleted inserted replaced
9:95cc44ea0068 10:d3fbcdfa1b2f
91 // Disable the data cache 91 // Disable the data cache
92 #ifndef HAL_DCACHE_DISABLE_DEFINED 92 #ifndef HAL_DCACHE_DISABLE_DEFINED
93 #define HAL_DCACHE_DISABLE() 93 #define HAL_DCACHE_DISABLE()
94 #endif 94 #endif
95 95
96 #ifndef HAL_DCACHE_IS_ENABLED_DEFINED
97 #define HAL_DCACHE_IS_ENABLED(_state_) (_state_) = 1;
98 #endif
99
96 // Invalidate the entire cache 100 // Invalidate the entire cache
97 // We simply use HAL_DCACHE_SYNC() to do this. For writeback caches this 101 // We simply use HAL_DCACHE_SYNC() to do this. For writeback caches this
98 // is not quite what we want, but there is no index-invalidate operation 102 // is not quite what we want, but there is no index-invalidate operation
99 // available. 103 // available.
100 #ifndef HAL_DCACHE_INVALIDATE_ALL_DEFINED 104 #ifndef HAL_DCACHE_INVALIDATE_ALL_DEFINED
107 #define HAL_DCACHE_SYNC() \ 111 #define HAL_DCACHE_SYNC() \
108 { \ 112 { \
109 register CYG_ADDRESS _baddr_ = 0x80000000; \ 113 register CYG_ADDRESS _baddr_ = 0x80000000; \
110 register CYG_ADDRESS _addr_ = 0x80000000; \ 114 register CYG_ADDRESS _addr_ = 0x80000000; \
111 register CYG_WORD _size_ = HAL_DCACHE_SIZE; \ 115 register CYG_WORD _size_ = HAL_DCACHE_SIZE; \
116 register CYG_WORD _state_; \
117 HAL_DCACHE_IS_ENABLED(_state_); \
112 HAL_DCACHE_DISABLE(); \ 118 HAL_DCACHE_DISABLE(); \
113 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 119 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
114 { \ 120 { \
115 asm volatile ("cache 0x01,0(%0)" : : "r"(_addr_) ); \ 121 asm volatile ("cache 0x01,0(%0)" : : "r"(_addr_) ); \
116 } \ 122 } \
117 HAL_DCACHE_ENABLE(); \ 123 if( _state_ ) HAL_DCACHE_ENABLE(); \
118 } 124 }
119 #endif 125 #endif
120 126
121 // Set the data cache refill burst size 127 // Set the data cache refill burst size
122 //#define HAL_DCACHE_BURST_SIZE(_size_) 128 //#define HAL_DCACHE_BURST_SIZE(_size_)
134 #define HAL_DCACHE_LOCK(_base_, _asize_) \ 140 #define HAL_DCACHE_LOCK(_base_, _asize_) \
135 CYG_MACRO_START \ 141 CYG_MACRO_START \
136 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 142 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
137 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 143 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
138 register CYG_WORD _size_ = (_asize_); \ 144 register CYG_WORD _size_ = (_asize_); \
145 register CYG_WORD _state_; \
146 HAL_DCACHE_IS_ENABLED(_state_); \
139 HAL_DCACHE_DISABLE(); \ 147 HAL_DCACHE_DISABLE(); \
140 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 148 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
141 { \ 149 { \
142 asm volatile ("cache 0x1d,0(%0)" : : "r"(_addr_) ); \ 150 asm volatile ("cache 0x1d,0(%0)" : : "r"(_addr_) ); \
143 } \ 151 } \
144 HAL_DCACHE_ENABLE(); \ 152 if( _state_ ) HAL_DCACHE_ENABLE(); \
145 CYG_MACRO_END 153 CYG_MACRO_END
146 #endif 154 #endif
147 155
148 // Undo a previous lock operation. 156 // Undo a previous lock operation.
149 // Do this by flushing the cache, which is defined to clear the lock bit. 157 // Do this by flushing the cache, which is defined to clear the lock bit.
172 #define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \ 180 #define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \
173 { \ 181 { \
174 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 182 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
175 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 183 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
176 register CYG_WORD _size_ = (_asize_); \ 184 register CYG_WORD _size_ = (_asize_); \
185 register CYG_WORD _state_; \
186 HAL_DCACHE_IS_ENABLED(_state_); \
177 HAL_DCACHE_DISABLE(); \ 187 HAL_DCACHE_DISABLE(); \
178 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 188 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
179 { \ 189 { \
180 asm volatile ("cache 0x15,0(%0)" : : "r"(_addr_) ); \ 190 asm volatile ("cache 0x15,0(%0)" : : "r"(_addr_) ); \
181 } \ 191 } \
182 HAL_DCACHE_ENABLE(); \ 192 if( _state_ ) HAL_DCACHE_ENABLE(); \
183 } 193 }
184 #endif 194 #endif
185 195
186 // Invalidate cache lines in the given range without writing to memory. 196 // Invalidate cache lines in the given range without writing to memory.
187 // This uses the hit-invalidate cache operation. 197 // This uses the hit-invalidate cache operation.
189 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \ 199 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
190 { \ 200 { \
191 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 201 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
192 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 202 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
193 register CYG_WORD _size_ = (_asize_); \ 203 register CYG_WORD _size_ = (_asize_); \
204 register CYG_WORD _state_; \
205 HAL_DCACHE_IS_ENABLED(_state_); \
194 HAL_DCACHE_DISABLE(); \ 206 HAL_DCACHE_DISABLE(); \
195 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 207 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
196 { \ 208 { \
197 asm volatile ("cache 0x11,0(%0)" : : "r"(_addr_) ); \ 209 asm volatile ("cache 0x11,0(%0)" : : "r"(_addr_) ); \
198 } \ 210 } \
199 HAL_DCACHE_ENABLE(); \ 211 if( _state_ ) HAL_DCACHE_ENABLE(); \
200 } 212 }
201 #endif 213 #endif
202 214
203 // Write dirty cache lines to memory for the given address range. 215 // Write dirty cache lines to memory for the given address range.
204 // This uses the hit-writeback cache operation. 216 // This uses the hit-writeback cache operation.
206 #define HAL_DCACHE_STORE( _base_ , _asize_ ) \ 218 #define HAL_DCACHE_STORE( _base_ , _asize_ ) \
207 { \ 219 { \
208 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 220 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
209 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 221 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
210 register CYG_WORD _size_ = (_asize_); \ 222 register CYG_WORD _size_ = (_asize_); \
223 register CYG_WORD _state_; \
224 HAL_DCACHE_IS_ENABLED(_state_); \
211 HAL_DCACHE_DISABLE(); \ 225 HAL_DCACHE_DISABLE(); \
212 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 226 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
213 { \ 227 { \
214 asm volatile ("cache 0x19,0(%0)" : : "r"(_addr_) ); \ 228 asm volatile ("cache 0x19,0(%0)" : : "r"(_addr_) ); \
215 } \ 229 } \
216 HAL_DCACHE_ENABLE(); \ 230 if( _state_ ) HAL_DCACHE_ENABLE(); \
217 } 231 }
218 #endif 232 #endif
219 233
220 // Preread the given range into the cache with the intention of reading 234 // Preread the given range into the cache with the intention of reading
221 // from it later. 235 // from it later.
238 #endif 252 #endif
239 253
240 // Disable the instruction cache 254 // Disable the instruction cache
241 #ifndef HAL_ICACHE_DISABLE_DEFINED 255 #ifndef HAL_ICACHE_DISABLE_DEFINED
242 #define HAL_ICACHE_DISABLE() 256 #define HAL_ICACHE_DISABLE()
257 #endif
258
259 #ifndef HAL_ICACHE_IS_ENABLED_DEFINED
260 #define HAL_ICACHE_IS_ENABLED(_state_) (_state_) = 1;
243 #endif 261 #endif
244 262
245 // Invalidate the entire cache 263 // Invalidate the entire cache
246 // This uses the index-invalidate cache operation. 264 // This uses the index-invalidate cache operation.
247 #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED 265 #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
248 #define HAL_ICACHE_INVALIDATE_ALL() \ 266 #define HAL_ICACHE_INVALIDATE_ALL() \
249 { \ 267 { \
250 register CYG_ADDRESS _baddr_ = 0x80000000; \ 268 register CYG_ADDRESS _baddr_ = 0x80000000; \
251 register CYG_ADDRESS _addr_ = 0x80000000; \ 269 register CYG_ADDRESS _addr_ = 0x80000000; \
270 register CYG_WORD _state_; \
271 HAL_ICACHE_IS_ENABLED(_state_); \
252 HAL_ICACHE_DISABLE(); \ 272 HAL_ICACHE_DISABLE(); \
253 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \ 273 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
254 { \ 274 { \
255 asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); \ 275 asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); \
256 } \ 276 } \
257 HAL_ICACHE_ENABLE(); \ 277 if( _state_ ) HAL_ICACHE_ENABLE(); \
258 } 278 }
259 #endif 279 #endif
260 280
261 // Synchronize the contents of the cache with memory. 281 // Synchronize the contents of the cache with memory.
262 // Simply force the cache to reload. 282 // Simply force the cache to reload.
274 #define HAL_ICACHE_LOCK(_base_, _asize_) \ 294 #define HAL_ICACHE_LOCK(_base_, _asize_) \
275 CYG_MACRO_START \ 295 CYG_MACRO_START \
276 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 296 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
277 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 297 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
278 register CYG_WORD _size_ = (_asize_); \ 298 register CYG_WORD _size_ = (_asize_); \
279 HAL_DCACHE_DISABLE(); \ 299 register CYG_WORD _state_; \
300 HAL_ICACHE_IS_ENABLED(_state_); \
301 HAL_ICACHE_DISABLE(); \
280 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 302 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
281 { \ 303 { \
282 asm volatile ("cache 0x1c,0(%0)" : : "r"(_addr_) ); \ 304 asm volatile ("cache 0x1c,0(%0)" : : "r"(_addr_) ); \
283 } \ 305 } \
284 HAL_DCACHE_ENABLE(); \ 306 if( _state_ ) HAL_ICACHE_ENABLE(); \
285 CYG_MACRO_END 307 CYG_MACRO_END
286 #endif 308 #endif
287 309
288 // Undo a previous lock operation. 310 // Undo a previous lock operation.
289 // Do this by invalidating the cache, which is defined to clear the lock bit. 311 // Do this by invalidating the cache, which is defined to clear the lock bit.
304 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \ 326 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
305 { \ 327 { \
306 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 328 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
307 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 329 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
308 register CYG_WORD _size_ = (_asize_); \ 330 register CYG_WORD _size_ = (_asize_); \
309 HAL_DCACHE_DISABLE(); \ 331 register CYG_WORD _state_; \
310 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 332 HAL_ICACHE_IS_ENABLED(_state_); \
333 HAL_ICACHE_DISABLE(); \
334 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
311 { \ 335 { \
312 asm volatile ("cache 0x10,0(%0)" : : "r"(_addr_) ); \ 336 asm volatile ("cache 0x10,0(%0)" : : "r"(_addr_) ); \
313 } \ 337 } \
314 HAL_DCACHE_ENABLE(); \ 338 HAL_ICACHE_ENABLE(); \
315 } 339 }
316 #endif 340 #endif
317 341
318 //----------------------------------------------------------------------------- 342 //-----------------------------------------------------------------------------
319 // Check that a supported configuration has actually defined some macros. 343 // Check that a supported configuration has actually defined some macros.