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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
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children d2c90368aeef
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207:74c807ddde34 208:e0c0827131d1
1 #ifndef CYGONCE_CERF_H
2 #define CYGONCE_CERF_H
3
4 /*=============================================================================
5 //
6 // cerfpda.h
7 //
8 // Platform specific support (register layout, etc)
9 //
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 //
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
19 //
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // for more details.
24 //
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 //
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
35 //
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
38 //
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
45 //
46 // Author(s): gthomas
47 // Contributors: gthomas
48 // Date: 2000-05-08
49 // Purpose: Intel SA1110/Assabet platform specific support routines
50 // Description:
51 // Usage: #include <cyg/hal/cerfpda.h>
52 //
53 //####DESCRIPTIONEND####
54 //
55 //===========================================================================*/
56
57
58 #ifndef __ASSEMBLER__
59 //
60 // Board Control Register
61 // Note: This register is write-only. Thus a shadow copy is provided so that
62 // it may be safely updated/shared by multiple threads.
63 //
64 extern unsigned long _cerfpda_BCR; // Shadow copy
65
66 extern void cerfpda_BCR(unsigned long mask, unsigned long value);
67
68 #endif
69
70 //
71 // Signal assertion levels
72 //
73 #define SA1110_LOGIC_ONE(m) (m & 0xFFFFFFFF)
74 #define SA1110_LOGIC_ZERO(m) (m & 0x00000000)
75
76 //
77 // SA1110/Cerf Board Control Register
78 //
79 #define SA1110_BOARD_CONTROL REG32_PTR(0x10000000)
80 #define SA1110_BCR_MIN 0x00000000 // Reset state
81
82 #define SA1110_BCR_CF_POWER 0x00000000 // 1 = CompactFlash power on (##### NA ######)
83 #define SA1110_BCR_CF_POWER_ON SA1110_LOGIC_ONE(SA1110_BCR_CF_POWER)
84 #define SA1110_BCR_CF_POWER_OFF SA1110_LOGIC_ZERO(SA1110_BCR_CF_POWER)
85 #define SA1110_BCR_CF_RESET 0x00000000 // 1 = CompactFlash reset (##### NA #####)
86 #define SA1110_BCR_CF_RESET_ENABLE SA1110_LOGIC_ONE(SA1110_BCR_CF_RESET)
87 #define SA1110_BCR_CF_RESET_DISABLE SA1110_LOGIC_ZERO(SA1110_BCR_CF_RESET)
88 #define SA1110_BCR_SOFT_RESET 0x00000004 // 0 = resets UCB1300, ADI7171, UDA1341
89 #define SA1110_BCR_IRDA_FREQ 0x00000008 // 0 = SIR, 1 = MIR/FIR
90 #define SA1110_BCR_IRDA_MD 0x00000030 // IrDA Mode & range
91 #define SA1110_BCR_IRDA_MD_MAX 0x00000000 // Max range and power
92 #define SA1110_BCR_IRDA_MD_OFF 0x00000010 // Shutdown
93 #define SA1110_BCR_IRDA_MD_23 0x00000020 // 2/3 power
94 #define SA1110_BCR_IRDA_MD_13 0x00000030 // 1/3 power
95 #define SA1110_BCR_STEREO_LB 0x00000040 // 1 = Stereo loopback on
96 #define SA1110_BCR_CF_BUS 0x00000000 // 0 = CompactFlash bus on (##### NA #####)
97 #define SA1110_BCR_CF_BUS_ON SA1110_LOGIC_ZERO(SA1110_BCR_CF_BUS)
98 #define SA1110_BCR_CF_BUS_OFF SA1110_LOGIC_ONE(SA1110_BCR_CF_BUS)
99 #define SA1110_BCR_AUDIO_ON 0x00000100 // 1 = UDA1341, MIC, DAA power on
100 #define SA1110_BCR_BACKLIGHT 0x00000200 // 1 = LCD backlight on
101 #define SA1110_BCR_LCD_BPP 0x00000400 // 1 = 16 RGB, 0 = 12 RGB
102 #define SA1110_BCR_LCD_16BPP SA1110_LOGIC_ONE(SA1110_BCR_LCD_BPP)
103 #define SA1110_BCR_LCD_12BPP SA1110_LOGIC_ZERO(SA1110_BCR_LCD_BPP)
104 #define SA1110_BCR_LCD 0x00000800 // 1 = LCD panel and controller on
105 #define SA1110_BCR_LCD_ON SA1110_LOGIC_ONE(SA1110_BCR_LCD)
106 #define SA1110_BCR_LCD_OFF SA1110_LOGIC_ZERO(SA1110_BCR_LCD)
107 #define SA1110_BCR_RS232_ENABLE 0x00001000 // 1 = Enable RS232 signals
108 #define SA1110_BCR_RED_LED 0x00000001 // 0 = Red LED on
109 #define SA1110_BCR_RED_LED_ON SA1110_LOGIC_ZERO(SA1110_BCR_RED_LED)
110 #define SA1110_BCR_RED_LED_OFF SA1110_LOGIC_ONE(SA1110_BCR_RED_LED)
111 #define SA1110_BCR_GREEN_LED 0x00000002 // 0 = Green LED on
112 #define SA1110_BCR_GREEN_LED_ON SA1110_LOGIC_ZERO(SA1110_BCR_GREEN_LED)
113 #define SA1110_BCR_GREEN_LED_OFF SA1110_LOGIC_ONE(SA1110_BCR_GREEN_LED)
114 #define SA1110_BCR_MOTOR 0x00000004 // 1 = Vibrator motor on
115 #define SA1110_BCR_MOTOR_ON SA1110_LOGIC_ONE(SA1110_BCR_MOTOR)
116 #define SA1110_BCR_MOTOR_OFF SA1110_LOGIC_ZERO(SA1110_BCR_MOTOR)
117 #define SA1110_BCR_COM_DTR 0x00010000 // COM port Data Terminal Ready
118 #define SA1110_BCR_COM_RTS 0x00020000 // COM port Request To Send
119 #define SA1110_BCR_RADIO_WAKE 0x00040000 // 1 = Wake up CPU with radio
120 #define SA1110_BCR_MUTE 0x00200000 // 1 = Audio muted
121
122 #define SA1110_BCR_ETH_SLEEP (1 << 27) // Output pin to put Crystal LAN in sleep mode.
123
124 //
125 // Special purpose GPIO interrupt mappings
126 //
127 #define SA1110_CF_IRQ CYGNUM_HAL_INTERRUPT_GPIO22
128 #define SA1110_CF_DETECT CYGNUM_HAL_INTERRUPT_GPIO23
129 #define SA1110_IRQ_GPIO_ETH CYGNUM_HAL_INTERRUPT_GPIO26
130 #define SA1110_IRQ_GPIO_16X5X CYGNUM_HAL_INTERRUPT_GPIO3
131 //
132 // GPIO layout
133 //
134 #define SA1110_GPIO_CF_DETECT 0x00800000 // 0 = Compact Flash detect
135 #define SA1110_GPIO_CF_PRESENT SA1110_LOGIC_ZERO(SA1110_GPIO_CF_DETECT)
136 //#define SA1110_GPIO_CF_ABSENT SA1110_LOGIC_ONE(SA1110_GPIO_CF_DETECT)
137
138 //
139 // LCD Controller
140 //
141 #define SA1110_LCCR0 SA11X0_REGISTER(0x30100000)
142 #define SA1110_LCSR SA11X0_REGISTER(0x30100004)
143 #define SA1110_DBAR1 SA11X0_REGISTER(0x30100010)
144 #define SA1110_DCAR1 SA11X0_REGISTER(0x30100014)
145 #define SA1110_DBAR2 SA11X0_REGISTER(0x30100018)
146 #define SA1110_DCAR2 SA11X0_REGISTER(0x3010001C)
147 #define SA1110_LCCR1 SA11X0_REGISTER(0x30100020)
148 #define SA1110_LCCR2 SA11X0_REGISTER(0x30100024)
149 #define SA1110_LCCR3 SA11X0_REGISTER(0x30100028)
150
151 /*---------------------------------------------------------------------------*/
152 /* end of cerfpda.h */
153 #endif /* CYGONCE_CERF_H */