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comparison packages/hal/sh/sh2/current/include/mod_regs_intc.h @ 208:e0c0827131d1 ecos

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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
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children d2c90368aeef
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207:74c807ddde34 208:e0c0827131d1
1 //=============================================================================
2 //
3 // mod_regs_intc.h
4 //
5 // INTC (interrupt controller) Module register definitions
6 //
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 //
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
16 //
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 // for more details.
21 //
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
25 //
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
32 //
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
35 //
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //=============================================================================
41 //#####DESCRIPTIONBEGIN####
42 //
43 // Author(s): jskov
44 // Contributors:jskov
45 // Date: 2002-01-15
46 //
47 //####DESCRIPTIONEND####
48 //
49 //=============================================================================
50
51 // NOTE: This'll need restructuring as other variants are added. Type 1 should
52 // be fewest common registers.
53
54 //--------------------------------------------------------------------------
55 // Interrupt registers, module type 1
56 #define CYGARC_REG_ICR 0xfffffee0
57 #define CYGARC_REG_IRQCSR 0xfffffee8
58 #define CYGARC_REG_IPRA 0xfffffee2
59 #define CYGARC_REG_IPRB 0xfffffe60
60 #define CYGARC_REG_IPRC 0xfffffee6
61 #define CYGARC_REG_IPRD 0xfffffe40
62 #define CYGARC_REG_IPRE 0xfffffec0
63
64 #define CYGARC_REG_VCRA 0xfffffe62
65 #define CYGARC_REG_VCRB 0xfffffe64
66 #define CYGARC_REG_VCRC 0xfffffe66
67 #define CYGARC_REG_VCRD 0xfffffe68
68 #define CYGARC_REG_VCRE 0xfffffe42
69 #define CYGARC_REG_VCRF 0xfffffe44
70 #define CYGARC_REG_VCRG 0xfffffe46
71 #define CYGARC_REG_VCRH 0xfffffe48
72 #define CYGARC_REG_VCRI 0xfffffe4a
73 #define CYGARC_REG_VCRJ 0xfffffe4c
74 #define CYGARC_REG_VCRK 0xfffffe4e
75 #define CYGARC_REG_VCRL 0xfffffe50
76 #define CYGARC_REG_VCRM 0xfffffe52
77 #define CYGARC_REG_VCRN 0xfffffe54
78 #define CYGARC_REG_VCRO 0xfffffe56
79 #define CYGARC_REG_VCRP 0xfffffec2
80 #define CYGARC_REG_VCRQ 0xfffffec4
81 #define CYGARC_REG_VCRR 0xfffffec6
82 #define CYGARC_REG_VCRS 0xfffffec8
83 #define CYGARC_REG_VCRT 0xfffffeca
84 #define CYGARC_REG_VCRU 0xfffffecc
85 #define CYGARC_REG_VCRWDT 0xfffffee4
86 #define CYGARC_REG_VCRDMA0 0xffffffa0 // 32 bit
87 #define CYGARC_REG_VCRDMA1 0xffffffa8 // 32 bit
88
89 #define CYGARC_REG_ICR_NMIL 0x8000
90 #define CYGARC_REG_ICR_NMIE 0x0100
91 #define CYGARC_REG_ICR_EXIMD 0x0002
92 #define CYGARC_REG_ICR_VECMD 0x0001
93
94 #define CYGARC_REG_IPRA_DMAC_MASK 0x0f00
95 #define CYGARC_REG_IPRA_DMAC_PRI1 0x0100
96 #define CYGARC_REG_IPRA_WDT_MASK 0x00f0
97 #define CYGARC_REG_IPRA_WDT_PRI1 0x0010
98
99 #define CYGARC_REG_IPRB_EDMAC_MASK 0xf000
100 #define CYGARC_REG_IPRB_EDMAC_PRI1 0x1000
101 #define CYGARC_REG_IPRB_FRT_MASK 0x0f00
102 #define CYGARC_REG_IPRB_FRT_PRI1 0x0100
103
104 #define CYGARC_REG_IPRC_IRQ3_MASK 0xf000
105 #define CYGARC_REG_IPRC_IRQ3_PRI1 0x1000
106 #define CYGARC_REG_IPRC_IRQ2_MASK 0x0f00
107 #define CYGARC_REG_IPRC_IRQ2_PRI1 0x0100
108 #define CYGARC_REG_IPRC_IRQ1_MASK 0x00f0
109 #define CYGARC_REG_IPRC_IRQ1_PRI1 0x0010
110 #define CYGARC_REG_IPRC_IRQ0_MASK 0x000f
111 #define CYGARC_REG_IPRC_IRQ0_PRI1 0x0001
112
113 #define CYGARC_REG_IPRD_TPU0_MASK 0xf000
114 #define CYGARC_REG_IPRD_TPU0_PRI1 0x1000
115 #define CYGARC_REG_IPRD_TPU1_MASK 0x0f00
116 #define CYGARC_REG_IPRD_TPU1_PRI1 0x0100
117 #define CYGARC_REG_IPRD_TPU2_MASK 0x00f0
118 #define CYGARC_REG_IPRD_TPU2_PRI1 0x0010
119 #define CYGARC_REG_IPRD_SCIF1_MASK 0x000f
120 #define CYGARC_REG_IPRD_SCIF1_PRI1 0x0001
121
122 #define CYGARC_REG_IPRE_SCIF2_MASK 0xf000
123 #define CYGARC_REG_IPRE_SCIF2_PRI1 0x1000
124 #define CYGARC_REG_IPRE_SIO0_MASK 0x0f00
125 #define CYGARC_REG_IPRE_SIO0_PRI1 0x0100
126 #define CYGARC_REG_IPRE_SIO1_MASK 0x00f0
127 #define CYGARC_REG_IPRE_SIO1_PRI1 0x0010
128 #define CYGARC_REG_IPRE_SIO2_MASK 0x000f
129 #define CYGARC_REG_IPRE_SIO2_PRI1 0x0001
130
131 // The (initial) IRQ mode is controlled by configuration.
132 #ifdef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
133 # define CYGARC_REG_ICR_INIT (CYGARC_REG_ICR_EXIMD)
134 #else
135 # define CYGARC_REG_ICR_INIT 0x0000
136 #endif
137
138 #define CYGARC_REG_IRQCSR_IRQ_LOWLEVEL 0
139 #define CYGARC_REG_IRQCSR_IRQ_RISING 1
140 #define CYGARC_REG_IRQCSR_IRQ_FALLING 2
141 #define CYGARC_REG_IRQCSR_IRQ_BOTHEDGES 3
142 #define CYGARC_REG_IRQCSR_IRQ_mask 3
143
144 #define CYGARC_REG_IRQCSR_IRQ3_mask 0xc000
145 #define CYGARC_REG_IRQCSR_IRQ3_shift 14
146 #define CYGARC_REG_IRQCSR_IRQ2_mask 0x3000
147 #define CYGARC_REG_IRQCSR_IRQ2_shift 12
148 #define CYGARC_REG_IRQCSR_IRQ1_mask 0x0c00
149 #define CYGARC_REG_IRQCSR_IRQ1_shift 10
150 #define CYGARC_REG_IRQCSR_IRQ0_mask 0x0300
151 #define CYGARC_REG_IRQCSR_IRQ0_shift 8
152
153 #define CYGARC_REG_IRQCSR_IRL3PS 0x0080
154 #define CYGARC_REG_IRQCSR_IRL2PS 0x0040
155 #define CYGARC_REG_IRQCSR_IRL1PS 0x0020
156 #define CYGARC_REG_IRQCSR_IRL0PS 0x0010
157
158 #define CYGARC_REG_IRQCSR_IRQ3F 0x0008
159 #define CYGARC_REG_IRQCSR_IRQ2F 0x0004
160 #define CYGARC_REG_IRQCSR_IRQ1F 0x0002
161 #define CYGARC_REG_IRQCSR_IRQ0F 0x0001