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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
parents 42f843b391aa
children d2c90368aeef
comparison
equal deleted inserted replaced
207:74c807ddde34 208:e0c0827131d1
5 ## variant.inc 5 ## variant.inc
6 ## 6 ##
7 ## SH4 variant assembler header file 7 ## SH4 variant assembler header file
8 ## 8 ##
9 ##============================================================================= 9 ##=============================================================================
10 #####COPYRIGHTBEGIN#### 10 #####ECOSGPLCOPYRIGHTBEGIN####
11 # 11 # -------------------------------------------
12 # ------------------------------------------- 12 # This file is part of eCos, the Embedded Configurable Operating System.
13 # The contents of this file are subject to the Red Hat eCos Public License 13 # Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 # Version 1.1 (the "License"); you may not use this file except in 14 #
15 # compliance with the License. You may obtain a copy of the License at 15 # eCos is free software; you can redistribute it and/or modify it under
16 # http://www.redhat.com/ 16 # the terms of the GNU General Public License as published by the Free
17 # 17 # Software Foundation; either version 2 or (at your option) any later version.
18 # Software distributed under the License is distributed on an "AS IS" 18 #
19 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the 19 # eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20 # License for the specific language governing rights and limitations under 20 # WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 # the License. 21 # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 # 22 # for more details.
23 # The Original Code is eCos - Embedded Configurable Operating System, 23 #
24 # released September 30, 1998. 24 # You should have received a copy of the GNU General Public License along
25 # 25 # with eCos; if not, write to the Free Software Foundation, Inc.,
26 # The Initial Developer of the Original Code is Red Hat. 26 # 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 # Portions created by Red Hat are 27 #
28 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc. 28 # As a special exception, if other files instantiate templates or use macros
29 # All Rights Reserved. 29 # or inline functions from this file, or you compile this file and link it
30 # ------------------------------------------- 30 # with other works to produce a work based on this file, this file does not
31 # 31 # by itself cause the resulting work to be covered by the GNU General Public
32 #####COPYRIGHTEND#### 32 # License. However the source code for this file must still be made available
33 # in accordance with section (3) of the GNU General Public License.
34 #
35 # This exception does not invalidate any other reasons why a work based on
36 # this file might be covered by the GNU General Public License.
37 #
38 # Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
39 # at http://sources.redhat.com/ecos/ecos-license
40 # -------------------------------------------
41 #####ECOSGPLCOPYRIGHTEND####
33 ##============================================================================= 42 ##=============================================================================
34 #######DESCRIPTIONBEGIN#### 43 #######DESCRIPTIONBEGIN####
35 ## 44 ##
36 ## Author(s): jskov 45 ## Author(s): jskov
37 ## Contributors:jskov 46 ## Contributors:jskov
50 59
51 #include <pkgconf/hal.h> 60 #include <pkgconf/hal.h>
52 #include <cyg/hal/sh_regs.h> 61 #include <cyg/hal/sh_regs.h>
53 62
54 #=========================================================================== 63 #===========================================================================
55 # SR initialization value 64 ## SR initialization value
56 # zero all bits except: 65 ## zero all bits except:
57 # MD = Processor operation mode field (privileged mode) 66 ## MD = Processor operation mode field (privileged mode)
58 # I0-3 = Mask out all interrupts but NMI. 67 ## I0-3 = Mask out all interrupts but NMI.
59 # 68 ##
60 # When saving or restoring the state of an exception or interrupt, the bit 69 ## When saving or restoring the state of an exception or interrupt, the bit
61 # CYGARC_REG_SR_RB is also set, switching the register bank. When this bit 70 ## CYGARC_REG_SR_RB is also set, switching the register bank. When this bit
62 # is set, interrupts must be disabled. 71 ## is set, interrupts must be disabled.
63 # 72 ##
64 # Note: We could also use the BL bit to prevent interrupts, but that would 73 ## Note: We could also use the BL bit to prevent interrupts, but that would
65 # also prevent the use of breakpoints. 74 ## also prevent the use of breakpoints.
66 75
67 #define CYG_SR (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK) 76 #define CYG_SR (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK)
68 #define CYG_SR_BANK1 (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK|CYGARC_REG_SR_RB) 77 #define CYG_SR_BANK1 (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK|CYGARC_REG_SR_RB)
69 78
70 ##----------------------------------------------------------------------------- 79 ##-----------------------------------------------------------------------------
91 mov.w r0,@r1 100 mov.w r0,@r1
92 mov.l $CYGARC_REG_IPRB,r1 101 mov.l $CYGARC_REG_IPRB,r1
93 mov.w r0,@r1 102 mov.w r0,@r1
94 mov.l $CYGARC_REG_IPRC,r1 103 mov.l $CYGARC_REG_IPRC,r1
95 mov.w r0,@r1 104 mov.w r0,@r1
105 #if (CYGARC_SH_MOD_INTC == 2)
106 mov.l $CYGARC_REG_IPRD,r1
107 mov.w r0,@r1
108 #endif
96 mov.w $nCYG_WTCSR,r0 ! Clear watchdog 109 mov.w $nCYG_WTCSR,r0 ! Clear watchdog
97 mov.l $nCYGARC_REG_WTCSR,r1 110 mov.l $nCYGARC_REG_WTCSR,r1
98 mov.w r0,@r1 111 mov.w r0,@r1
99 mov.w $nCYG_ICR_INIT,r0 112 mov.w $nCYG_ICR_INIT,r0
100 mov.l $CYGARC_REG_ICR,r1 ! Set interrupt controller to IRQ mode 113 mov.l $CYGARC_REG_ICR,r1 ! Set interrupt controller to IRQ mode
132 .long CYGARC_REG_IPRA 145 .long CYGARC_REG_IPRA
133 $CYGARC_REG_IPRB: 146 $CYGARC_REG_IPRB:
134 .long CYGARC_REG_IPRB 147 .long CYGARC_REG_IPRB
135 $CYGARC_REG_IPRC: 148 $CYGARC_REG_IPRC:
136 .long CYGARC_REG_IPRC 149 .long CYGARC_REG_IPRC
150 #if (CYGARC_SH_MOD_INTC == 2)
151 $CYGARC_REG_IPRD:
152 .long CYGARC_REG_IPRD
153 #endif
137 $nCYGARC_REG_WTCSR: 154 $nCYGARC_REG_WTCSR:
138 .long CYGARC_REG_WTCSR 155 .long CYGARC_REG_WTCSR
139 $CYGARC_REG_ICR: 156 $CYGARC_REG_ICR:
140 .long CYGARC_REG_ICR 157 .long CYGARC_REG_ICR
141 SYM_PTR_REF(_reset) 158 SYM_PTR_REF(_reset)
148 #define CYGPKG_HAL_SH_POST_RESET_INIT 165 #define CYGPKG_HAL_SH_POST_RESET_INIT
149 #endif 166 #endif
150 167
151 ##----------------------------------------------------------------------------- 168 ##-----------------------------------------------------------------------------
152 ## Interrupt decode macros 169 ## Interrupt decode macros
153 .macro hal_intc_decode tmp,inum 170 .macro hal_intc_decode tmp,inum
154 mov.l $nCYGARC_REG_INTEVT,\tmp 171 mov.l 1f,\tmp
155 mov.l @\tmp,\inum 172 mov.l @\tmp,\inum
156 mov #-5,\tmp ! divide cause by 0x20 173 mov #-5,\tmp ! divide cause by 0x20
157 shld \tmp,\inum 174 shld \tmp,\inum
158 add #-14,\inum ! adjust so NMI becomes 0 175 bra 2f
176 add #-14,\inum ! adjust so NMI becomes 0
177 .align 2
178 1: .long CYGARC_REG_INTEVT
179 2:
159 .endm 180 .endm
160 181
161 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN 182 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
162 .macro hal_intc_translate inum,vnum 183 .macro hal_intc_translate inum,vnum
163 mov #0,\vnum ! Just vector zero is supported 184 mov #0,\vnum ! Just vector zero is supported