--- a/packages/hal/arm/xscale/grg/current/include/hal_platform_setup.h
+++ b/packages/hal/arm/xscale/grg/current/include/hal_platform_setup.h
@@ -11,7 +11,7 @@
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
@@ -63,9 +63,27 @@
 #include <cyg/hal/hal_mm.h>             // more MMU definitions
 #include <cyg/hal/grg.h>                // Platform specific hardware definitions
 
+// ------------------------------------------------------------------------
+// Convenience macros for setting up page table
+// 
+.macro IXP_MAP_SDRAM va, c, b, x, p
+    XSCALE_MMU_SECTION SDRAM_PHYS_BASE>>20, \va>>20, SDRAM_SIZE>>20, \c, \b, 3, \x, \p
+.endm
+
+.macro IXP_MAP_EXP_V n, va, sz, c, b, x, p
+    XSCALE_MMU_SECTION (0x500 + ((IXP425_EXP_CS_SIZE * \n) >> 20)), \va>>20, \sz>>20, \c, \b, 3, \x, \p
+.endm
+
+.macro IXP_MAP_EXP n, sz, c, b, x, p
+    IXP_MAP_EXP_V \n, (0x50000000 + (IXP425_EXP_CS_SIZE * \n)), \sz, \c, \b, \x, \p
+.endm
+
+.macro IXP_MAP_IO addr, sz
+    XSCALE_MMU_SECTION \addr>>20, \addr>>20, \sz>>20, 0, 0, 3, 0, 0
+.endm
+
 #if defined(CYG_HAL_STARTUP_ROM)
 #define PLATFORM_SETUP1  _platform_setup1
-#define PLATFORM_EXTRAS  <cyg/hal/hal_platform_extras.h>
 #define CYGHWR_HAL_ARM_HAS_MMU
 
 // ------------------------------------------------------------------------
@@ -86,7 +104,7 @@
 // This macro represents the initial startup code for the platform        
 	.macro _platform_setup1
 
-#if CYGINT_HAL_ARM_BIGENDIAN
+#ifdef CYGHWR_HAL_ARM_BIGENDIAN
         // set big-endian
 	mrc	p15, 0, r0, c1, c0, 0
         orr	r0, r0, #0x80
@@ -201,6 +219,12 @@
         str	r1, [r0, #IXP425_SDRAM_IR]
 	DELAY   0x10000, r1
 
+        // Enable byte swapping control via page table P bit.    
+        ldr     r2, =IXP425_EXP_CFG_BASE
+        ldr     r1, [r2, #IXP425_EXP_CNFG1]
+        orr     r1, r1, #EXP_CNFG1_BYTE_SWAP_EN
+        str     r1, [r2, #IXP425_EXP_CNFG1]
+
 	// value to load into pc to jump to real runtime address
 	ldr     r0, =1f
 
@@ -226,20 +250,38 @@ icache_boundary:
     0:  b       0b
     1:
 
-	// Move mmu tables into RAM so page table walks by the cpu
+	// Build mmu tables into RAM so page table walks by the cpu
 	// don't interfere with FLASH programming.
-	ldr	r0, =mmu_table
-	add     r2, r0, #0x4000     	// End of tables
 	mov	r1, #SDRAM_PHYS_BASE
 	orr	r1, r1, #0x4000		// RAM tables
+	add     r2, r1, #0x4000     	// End of tables
 
-	// everything can go as-is
+	// First clear table
+	mov	r0, #0
     1:
-	ldr	r3, [r0], #4
-	str	r3, [r1], #4
-	cmp	r0, r2
+	str	r0, [r1], #4
+	cmp	r1, r2
 	bne	1b
 
+        // Build section mappings
+	IXP_MAP_SDRAM   SDRAM_BASE,           1, 0, 0, 0   // Cached SDRAM
+	IXP_MAP_SDRAM   SDRAM_ALIAS_BASE,     1, 0, 0, 0   // Cached SDRAM alias
+	IXP_MAP_SDRAM   SDRAM_UNCACHED_BASE,  0, 0, 0, 0   // Uncached SDRAM
+	IXP_MAP_SDRAM   SDRAM_DC_BASE,        1, 0, 0, 1   // Cached data coherent SDRAM
+
+	IXP_MAP_EXP 0, IXDP_FLASH_SIZE,       1, 0, 0, 0   // Flash
+	IXP_MAP_EXP 4, (1 << 20),             0, 0, 0, 0   // NPE use
+	IXP_MAP_EXP 5, (1 << 20),             0, 0, 0, 0   // NPE use
+
+	IXP_MAP_EXP_V 0, IXDP_FLASH_DC_BASE, IXDP_FLASH_SIZE, 1, 0, 0, 1  // data coherent flash
+
+	IXP_MAP_IO      IXP425_PCI_WINDOW_BASE,  IXP425_PCI_WINDOW_SIZE
+	IXP_MAP_IO      IXP425_QMGR_BASE,        IXP425_QMGR_SIZE
+	IXP_MAP_IO	IXP425_PCI_CFG_BASE,     IXP425_PCI_CFG_SIZE
+	IXP_MAP_IO	IXP425_EXP_CFG_BASE,     IXP425_EXP_CFG_SIZE
+	IXP_MAP_IO	IXP425_MISC_CFG_BASE,    IXP425_MISC_CFG_SIZE
+	IXP_MAP_IO	IXP425_SDRAM_CFG_BASE,   IXP425_SDRAM_CFG_SIZE
+
         mcr     p15, 0, r0, c7, c10, 4  // drain the write & fill buffers
         CPWAIT  r0