--- a/packages/hal/arm/cma230/current/include/hal_cache.h
+++ b/packages/hal/arm/cma230/current/include/hal_cache.h
@@ -33,7 +33,7 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):   nickg, gthomas
-// Contributors:        nickg, gthomas
+// Contributors:        nickg, gthomas, msalter
 // Date:        1998-09-28
 // Purpose:     Cache control API
 // Description: The macros defined here provide the HAL APIs for handling
@@ -49,6 +49,170 @@
 
 #include <cyg/infra/cyg_type.h>
 
+#ifdef __CMA222
+//-----------------------------------------------------------------------------
+// Cache dimensions
+
+#define HAL_UCACHE_SIZE                 0x2000   // Size of data cache in bytes
+#define HAL_UCACHE_LINE_SIZE            16       // Size of a data cache line
+#define HAL_UCACHE_WAYS                 4        // Associativity of the cache
+#define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
+
+#define HAL_CACHE_UNIFIED   // Let programs know the caches are combined
+
+//-----------------------------------------------------------------------------
+// Global control of caches
+
+// Note: the 'mrc' doesn't seem to work.
+#if 0
+// Enable the data cache
+//    mrc  MMU_CP,0,r1,MMU_Control,c0
+//    orr  r1,r1,#MMU_Control_C|MMU_Control_B
+//    mcr  MMU_CP,0,r1,MMU_Control,c0    
+
+#define HAL_UCACHE_ENABLE()                     \
+{                                               \
+    asm volatile ("mrc  p15,0,r1,c1,c0;"        \
+                  "orr  r1,r1,#0x000C;"         \
+                  "mcr  p15,0,r1,c1,c0;"        \
+                  :                             \
+                  :                             \
+                  : "r1" /* Clobber list */     \
+        );                                      \
+                                                \
+}
+
+// Disable the data cache
+#define HAL_UCACHE_DISABLE()                     \
+{                                               \
+    asm volatile ("mrc  p15,0,r1,c1,c0;"        \
+                  "bic  r1,r1,#0x000C;"         \
+                  "mcr  p15,0,r1,c1,c0;"        \
+                  :                             \
+                  :                             \
+                  : "r1" /* Clobber list */     \
+        );                                      \
+                                                \
+}
+#else
+#define HAL_UCACHE_ENABLE()                     \
+{                                               \
+    asm volatile ("mov  r1,#0x7D;"              \
+                  "mcr  p15,0,r1,c1,c0;"        \
+                  :                             \
+                  :                             \
+                  : "r1" /* Clobber list */     \
+        );                                      \
+                                                \
+}
+
+// Disable the data cache
+#define HAL_UCACHE_DISABLE()                    \
+{                                               \
+    asm volatile ("mov  r1,#0x71;"              \
+                  "mcr  p15,0,r1,c1,c0;"        \
+                  :                             \
+                  :                             \
+                  : "r1" /* Clobber list */     \
+        );                                      \
+                                                \
+}
+#endif
+
+// Is the cache turned on?
+#define HAL_UCACHE_IS_ENABLED(_state_) _state_ = 1;
+
+// Invalidate the entire cache
+//    mcr  MMU_CP,0,r1,MMU_InvalidateCache,c0
+#define HAL_UCACHE_INVALIDATE_ALL()                             \
+{                                                               \
+    asm volatile ("mcr p15,0,r1,c7,c0,0;" );                      \
+                                                                \
+}
+
+// Synchronize the contents of the cache with memory.
+#define HAL_UCACHE_SYNC()                                               \
+{                                                                       \
+    cyg_uint32 *ROM = (cyg_uint32 *)0xE0000000;                         \
+    int i;                                                              \
+    volatile cyg_uint32 val;                                            \
+    for (i = 0;  i < HAL_UCACHE_SETS;  i++) {                           \
+        val = *ROM;                                                     \
+        ROM += HAL_UCACHE_LINE_SIZE;                                    \
+    }                                                                   \
+}
+
+// Purge contents of data cache
+#define HAL_UCACHE_PURGE_ALL()  HAL_UCACHE_INVALIDATE_ALL()
+
+//-----------------------------------------------------------------------------
+// Data cache line control
+
+// Write dirty cache lines to memory and invalidate the cache entries
+// for the given address range.
+#define HAL_UCACHE_FLUSH( _base_ , _size_ )  HAL_UCACHE_SYNC()
+
+// Write dirty cache lines to memory for the given address range.
+#define HAL_UCACHE_STORE( _base_ , _size_ )  HAL_UCACHE_SYNC()
+
+#endif // ifdef __CMA222
+
+#ifdef HAL_CACHE_UNIFIED
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+#define HAL_DCACHE_SIZE                 HAL_UCACHE_SIZE
+#define HAL_DCACHE_LINE_SIZE            HAL_UCACHE_LINE_SIZE
+#define HAL_DCACHE_WAYS                 HAL_UCACHE_WAYS
+#define HAL_DCACHE_SETS                 HAL_UCACHE_SETS
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()             HAL_UCACHE_ENABLE()
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE()            HAL_UCACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL()     HAL_UCACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC()               HAL_UCACHE_SYNC()
+
+// Query the state of the data cache
+#define HAL_DCACHE_IS_ENABLED(_state_)  HAL_UCACHE_IS_ENABLED(_state_)
+
+//-----------------------------------------------------------------------------
+// Data cache line control
+
+// Write dirty cache lines to memory and invalidate the cache entries
+// for the given address range.
+#define HAL_DCACHE_FLUSH( _base_ , _size_ )  HAL_UCACHE_FLUSH( _base_ , _size_ )
+
+// Write dirty cache lines to memory for the given address range.
+#define HAL_DCACHE_STORE( _base_ , _size_ )  HAL_UCACHE_STORE( _base_ , _size_ )
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache - use Data cache controls since they
+// are not separatable.
+
+#define HAL_ICACHE_SIZE                 HAL_UCACHE_SIZE
+#define HAL_ICACHE_LINE_SIZE            HAL_UCACHE_LINE_SIZE
+#define HAL_ICACHE_WAYS                 HAL_UCACHE_WAYS
+#define HAL_ICACHE_SETS                 HAL_UCACHE_SETS
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()      HAL_UCACHE_ENABLE()
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE()     HAL_UCACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL()  HAL_UCACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC()        HAL_UCACHE_SYNC()
+
+#else
 //-----------------------------------------------------------------------------
 // Cache dimensions
 
@@ -65,6 +229,7 @@
 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
+
 //-----------------------------------------------------------------------------
 // Global control of data cache
 
@@ -165,5 +330,6 @@
 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
 
 //-----------------------------------------------------------------------------
+#endif // ifndef HAL_CACHE_UNIFIED
 #endif // ifndef CYGONCE_HAL_CACHE_H
 // End of hal_cache.h