diff packages/hal/mips/arch/current/include/hal_intr.h @ 90:70190fa0fe10 ecos-sw-2000-05-19

Merge from eCos master repository on 2000-05-19-07:47:03-BST
author jlarmour
date Fri, 19 May 2000 12:47:51 +0000
parents bf00f99aec69
children 02ea4320376c
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line diff
--- a/packages/hal/mips/arch/current/include/hal_intr.h
+++ b/packages/hal/mips/arch/current/include/hal_intr.h
@@ -92,6 +92,11 @@
 #define CYGNUM_HAL_VECTOR_OVERFLOW             12
 // Reserved
 #define CYGNUM_HAL_VECTOR_RESERVED_13          13
+// Division-by-zero [reserved vector]
+// This is caused by 'trap 0x7' which GCC puts in the code to check
+// for division by zero. The break_vsr_springboard in vectors.S is the
+// only caller of this vector.
+#define CYGNUM_HAL_VECTOR_DIV_BY_ZERO          14
 // Floating point exception
 #ifdef  CYGHWR_HAL_MIPS_FPU
 #define CYGNUM_HAL_VECTOR_FPE                  15
@@ -121,6 +126,7 @@
           CYGNUM_HAL_VECTOR_RESERVED_INSTRUCTION
 #define CYGNUM_HAL_EXCEPTION_COPROCESSOR    CYGNUM_HAL_VECTOR_COPROCESSOR
 #define CYGNUM_HAL_EXCEPTION_OVERFLOW       CYGNUM_HAL_VECTOR_OVERFLOW
+#define CYGNUM_HAL_EXCEPTION_DIV_BY_ZERO    CYGNUM_HAL_VECTOR_DIV_BY_ZERO
 
 // Min/Max exception numbers and how many there are
 #define CYGNUM_HAL_EXCEPTION_MIN                1
@@ -336,11 +342,14 @@ CYG_MACRO_END
 
 externC void __default_exception_vsr(void);
 externC void __default_interrupt_vsr(void);
+externC void __break_vsr_springboard(void);
 
 #define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) CYG_MACRO_START  \
     HAL_VSR_SET( _vector_, _vector_ == CYGNUM_HAL_VECTOR_INTERRUPT          \
                               ? (CYG_ADDRESS)__default_interrupt_vsr        \
-                              : (CYG_ADDRESS)__default_exception_vsr,       \
+                              : _vector_ == CYGNUM_HAL_VECTOR_BREAKPOINT    \
+                                ? (CYG_ADDRESS)__break_vsr_springboard      \
+                                : (CYG_ADDRESS)__default_exception_vsr,     \
                  _poldvsr_ );                                               \
 CYG_MACRO_END