--- a/packages/hal/mips/arch/current/include/hal_arch.h
+++ b/packages/hal/mips/arch/current/include/hal_arch.h
@@ -45,31 +45,50 @@
 #include <pkgconf/hal.h>
 #include <cyg/infra/cyg_type.h>
 
+#include <cyg/hal/var_arch.h>
+
 //--------------------------------------------------------------------------
 // Processor saved states:
 // The layout of this structure is also defined in "mips.inc", for assembly
 // code. Do not change this without changing that (or vice versa).
 
+#if defined(CYGHWR_HAL_MIPS_FPU)
+# if defined(CYGHWR_HAL_MIPS_FPU_64BIT)
+#  define CYG_HAL_FPU_REG CYG_WORD64
+# elif defined(CYGHWR_HAL_MIPS_FPU_32BIT)
+#  define CYG_HAL_FPU_REG CYG_WORD32
+# else
+# error MIPS FPU register size not defined
+# endif
+#endif
+
 typedef struct 
 {
     // These are common to all saved states
-    cyg_uint32  d[32];                  /* Data regs                    */
-    cyg_uint32  hi;                     /* hi word of mpy/div reg       */
-    cyg_uint32  lo;                     /* lo word of mpy/div reg       */
-
+    CYG_ADDRWORD        d[32];          /* Data regs                    */
+    CYG_ADDRWORD        hi;             /* hi word of mpy/div reg       */
+    CYG_ADDRWORD        lo;             /* lo word of mpy/div reg       */
+#ifdef CYGHWR_HAL_MIPS_FPU
+    CYG_HAL_FPU_REG     f[32];          /* FPU registers                */
+    CYG_ADDRWORD        fcr31;          /* FPU control/status register  */
+    CYG_ADDRWORD        fppad;          /* Dummy location to make this  */
+                                        /* structure a multiple of 8    */
+                                        /* bytes long.                  */
+#endif
+    
     // These are only saved for exceptions and interrupts
-    cyg_uint32  vector;                 /* Vector number                */
-    cyg_uint32  pc;                     /* Program Counter              */
-    cyg_uint32  sr;                     /* Status Reg                   */
-    cyg_uint32  cache;                  /* Cache control register       */
+    CYG_ADDRWORD        vector;         /* Vector number                */
+    CYG_ADDRWORD        pc;             /* Program Counter              */
+    CYG_ADDRWORD        sr;             /* Status Reg                   */
+    CYG_ADDRWORD        cache;          /* Cache control register       */
 
 
     // These are only saved for exceptions, and are not restored
     // when continued.
-    cyg_uint32  cause;                  /* Exception cause register     */
-    cyg_uint32  badvr;                  /* Bad virtual address reg      */
-    cyg_uint32  prid;                   /* Processor Version            */
-    cyg_uint32  config;                 /* Config register              */
+    CYG_ADDRWORD        cause;          /* Exception cause register     */
+    CYG_ADDRWORD        badvr;          /* Bad virtual address reg      */
+    CYG_ADDRWORD        prid;           /* Processor Version            */
+    CYG_ADDRWORD        config;         /* Config register              */
 } HAL_SavedRegisters;
 
 //--------------------------------------------------------------------------
@@ -93,20 +112,35 @@ externC cyg_uint32 hal_msbit_index(cyg_u
 
 //--------------------------------------------------------------------------
 // Context Initialization
+
+
+// Optional FPU context initialization
+#ifdef CYGHWR_HAL_MIPS_FPU
+#define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ )                     \
+{                                                                       \
+    for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->f[_i_] = (_id_)|_i_;      \
+    (_regs_)->fcr31 = 0;                                                \
+}
+#else
+#define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ )
+#endif
+
+
 // Initialize the context of a thread.
 // Arguments:
 // _sparg_ name of variable containing current sp, will be written with new sp
 // _thread_ thread object address, passed as argument to entry point
 // _entry_ entry point address.
 // _id_ bit pattern used in initializing registers, for debugging.
-
 #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ )        \
 {                                                                          \
     register CYG_WORD _sp_ = ((CYG_WORD)_sparg_)-56;                       \
     register HAL_SavedRegisters *_regs_;                                   \
     int _i_;                                                               \
-    _regs_ = (HAL_SavedRegisters *)((_sp_) - sizeof(HAL_SavedRegisters));  \
+    _sp_ = _sp_ & 0xFFFFFFF0;                                              \
+    _regs_ = (HAL_SavedRegisters *)(((_sp_) - sizeof(HAL_SavedRegisters))&0xFFFFFFF0);  \
     for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->d[_i_] = (_id_)|_i_;         \
+    HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ );                           \
     (_regs_)->d[29] = (CYG_WORD)(_sp_);       /* SP = top of stack      */ \
     (_regs_)->d[04] = (CYG_WORD)(_thread_);   /* R4 = arg1 = thread ptr */ \
     (_regs_)->lo = 0;                         /* LO = 0                 */ \
@@ -114,6 +148,7 @@ externC cyg_uint32 hal_msbit_index(cyg_u
     (_regs_)->d[30] = (CYG_WORD)(_sp_);       /* FP = top of stack      */ \
     (_regs_)->d[31] = (CYG_WORD)(_entry_);    /* LR(d[31]) = entry point*/ \
     (_regs_)->pc = (CYG_WORD)(_entry_);       /* PC = entry point       */ \
+    (_regs_)->sr  = 0x00000001;               /* SR = ls 3 bits only    */ \
     _sparg_ = (CYG_ADDRESS)_regs_;                                         \
 }
 
@@ -151,31 +186,11 @@ externC void hal_thread_load_context( CY
 // HAL_BREAKINST is the value of the breakpoint instruction and
 // HAL_BREAKINST_SIZE is its size in bytes.
 
-#ifdef CYG_HAL_MIPS_SIM
-#define  HAL_BREAKPOINT(_label_)                \
-    /* This code causes a fake breakpoint. */   \
-    asm volatile (                              \
-        "lui    $24,0x0000;"                    \
-        "ori    $24,0x0024;"                    \
-        "mtc0   $24,$13;"                       \
-        "lui    $25,%%hi(1f);"                  \
-        "ori    $25,$25,%%lo(1f);"              \
-        "j      other_vector;"                  \
-        "nop;"                                  \
-        ".global " #_label_ ";"                 \
-        #_label_":"                             \
-        "1: nop;"                               \
-        :                                       \
-        :                                       \
-        : "t8", "t9"                            \
-        );    
-#else
 #define HAL_BREAKPOINT(_label_)                 \
 asm volatile (" .globl  " #_label_ ";"          \
               #_label_":"                       \
               " break   5"                      \
     );
-#endif // CYG_HAL_MIPS_SIM
 
 #define HAL_BREAKINST           0x0005000d
 
@@ -184,33 +199,38 @@ asm volatile (" .globl  " #_label_ ";"  
 //--------------------------------------------------------------------------
 // Thread register state manipulation for GDB support.
 
+// Default to a 32 bit register size for GDB register dumps.
+#ifndef CYG_HAL_GDB_REG
+#define CYG_HAL_GDB_REG CYG_WORD32
+#endif
+
 // Translate a stack pointer as saved by the thread context macros above into
 // a pointer to a HAL_SavedRegisters structure.
-#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ )                  \
+#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ )          \
         (_regs_) = (HAL_SavedRegisters *)(_sp_)
 
 // Copy a set of registers from a HAL_SavedRegisters structure into a
 // GDB ordered array.    
-#define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ )                     \
-{                                                                       \
-    CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_);               \
-    int _i_;                                                            \
-                                                                        \
-    for( _i_ = 0; _i_ < 32; _i_++ )                                     \
-        _regval_[_i_] = (_regs_)->d[_i_];                               \
-                                                                        \
-    _regval_[32] = (_regs_)->sr;                                        \
-    _regval_[33] = (_regs_)->lo;                                        \
-    _regval_[34] = (_regs_)->hi;                                        \
-    _regval_[35] = (_regs_)->badvr;                                     \
-    _regval_[36] = (_regs_)->cause;                                     \
-    _regval_[37] = (_regs_)->pc;                                        \
+#define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ )             \
+{                                                               \
+    CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \
+    int _i_;                                                    \
+                                                                \
+    for( _i_ = 0; _i_ < 32; _i_++ )                             \
+        _regval_[_i_] = (_regs_)->d[_i_];                       \
+                                                                \
+    _regval_[32] = (_regs_)->sr;                                \
+    _regval_[33] = (_regs_)->lo;                                \
+    _regval_[34] = (_regs_)->hi;                                \
+    _regval_[35] = (_regs_)->badvr;                             \
+    _regval_[36] = (_regs_)->cause;                             \
+    _regval_[37] = (_regs_)->pc;                                \
 }
 
 // Copy a GDB ordered array into a HAL_SavedRegisters structure.
 #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ )             \
 {                                                               \
-    CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_);       \
+    CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \
     int _i_;                                                    \
                                                                 \
     for( _i_ = 0; _i_ < 32; _i_++ )                             \
@@ -276,11 +296,23 @@ externC void hal_idle_thread_action(cyg_
 // This is not a config option because it should not be adjusted except
 // under "enough rope" sort of disclaimers.
 
-// Worst case stack frame size: return link + 5 pushed registers.
-#define CYGNUM_HAL_STACK_FRAME_SIZE (24)
+// Typical case stack frame size: return link + 4 pushed registers + some locals.
+#define CYGNUM_HAL_STACK_FRAME_SIZE (48)
 
 // Stack needed for a context switch:
-#define CYGNUM_HAL_STACK_CONTEXT_SIZE (42*4)
+#if defined(CYGHWR_HAL_MIPS_FPU)
+# if defined(CYGHWR_HAL_MIPS_FPU_64BIT)
+#define CYGNUM_HAL_STACK_CONTEXT_SIZE (((32+12)*4)+(32*8))
+# elif defined(CYGHWR_HAL_MIPS_FPU_32BIT)
+#define CYGNUM_HAL_STACK_CONTEXT_SIZE (((32+12)*4)+(32*4))
+# else
+# error MIPS FPU register size not defined
+# endif
+#else
+#define CYGNUM_HAL_STACK_CONTEXT_SIZE ((32+10)*4)
+#endif
+
+
 
 // Interrupt + call to ISR, interrupt_end() and the DSR
 #define CYGNUM_HAL_STACK_INTERRUPT_SIZE (4+2*CYGNUM_HAL_STACK_CONTEXT_SIZE) 
@@ -293,7 +325,7 @@ externC void hal_idle_thread_action(cyg_
 
 #define CYGNUM_HAL_STACK_SIZE_MINIMUM (CYGNUM_HAL_STACK_CONTEXT_SIZE+      \
                                        CYGNUM_HAL_STACK_INTERRUPT_SIZE*2+  \
-                                       CYGNUM_HAL_STACK_FRAME_SIZE*4)
+                                       CYGNUM_HAL_STACK_FRAME_SIZE*8)
 #define CYGNUM_HAL_STACK_SIZE_TYPICAL (2048)
 
 #else // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK