--- a/packages/hal/mips/arch/current/src/context.S
+++ b/packages/hal/mips/arch/current/src/context.S
@@ -42,7 +42,7 @@
 
 #include <pkgconf/hal.h>
 
-#include <cyg/hal/mips.inc>
+#include <cyg/hal/arch.inc>
 
 	.set noat
 	
@@ -59,39 +59,39 @@ hal_thread_switch_context:
 
 	# store GPRs
 #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
-	sw	$0,(mipsreg_regs+0*4)(sp)
-	sw	$1,(mipsreg_regs+1*4)(sp)
-	sw	$2,(mipsreg_regs+2*4)(sp)
-	sw	$3,(mipsreg_regs+3*4)(sp)
-	sw	$4,(mipsreg_regs+4*4)(sp)
-	sw	$5,(mipsreg_regs+5*4)(sp)
-	sw	$6,(mipsreg_regs+6*4)(sp)
-	sw	$7,(mipsreg_regs+7*4)(sp)
-	sw	$8,(mipsreg_regs+8*4)(sp)
-	sw	$9,(mipsreg_regs+9*4)(sp)
-	sw	$10,(mipsreg_regs+10*4)(sp)
-	sw	$11,(mipsreg_regs+11*4)(sp)
-	sw	$12,(mipsreg_regs+12*4)(sp)
-	sw	$13,(mipsreg_regs+13*4)(sp)
-	sw	$14,(mipsreg_regs+14*4)(sp)
-	sw	$15,(mipsreg_regs+15*4)(sp)
-	sw	$24,(mipsreg_regs+24*4)(sp)
-	sw	$25,(mipsreg_regs+25*4)(sp)
-	sw	$28,(mipsreg_regs+28*4)(sp)	# == GP
+	sw	$0,(mipsreg_regs+0*mips_regsize)(sp)
+	sw	$1,(mipsreg_regs+1*mips_regsize)(sp)
+	sw	$2,(mipsreg_regs+2*mips_regsize)(sp)
+	sw	$3,(mipsreg_regs+3*mips_regsize)(sp)
+	sw	$4,(mipsreg_regs+4*mips_regsize)(sp)
+	sw	$5,(mipsreg_regs+5*mips_regsize)(sp)
+	sw	$6,(mipsreg_regs+6*mips_regsize)(sp)
+	sw	$7,(mipsreg_regs+7*mips_regsize)(sp)
+	sw	$8,(mipsreg_regs+8*mips_regsize)(sp)
+	sw	$9,(mipsreg_regs+9*mips_regsize)(sp)
+	sw	$10,(mipsreg_regs+10*mips_regsize)(sp)
+	sw	$11,(mipsreg_regs+11*mips_regsize)(sp)
+	sw	$12,(mipsreg_regs+12*mips_regsize)(sp)
+	sw	$13,(mipsreg_regs+13*mips_regsize)(sp)
+	sw	$14,(mipsreg_regs+14*mips_regsize)(sp)
+	sw	$15,(mipsreg_regs+15*mips_regsize)(sp)
+	sw	$24,(mipsreg_regs+24*mips_regsize)(sp)
+	sw	$25,(mipsreg_regs+25*mips_regsize)(sp)
+	sw	$28,(mipsreg_regs+28*mips_regsize)(sp)	# == GP
 #endif	
-	sw	$16,(mipsreg_regs+16*4)(sp)
-	sw	$17,(mipsreg_regs+17*4)(sp)	
-	sw	$18,(mipsreg_regs+18*4)(sp)
-	sw	$19,(mipsreg_regs+19*4)(sp)
-	sw	$20,(mipsreg_regs+20*4)(sp)
-	sw	$21,(mipsreg_regs+21*4)(sp)
-	sw	$22,(mipsreg_regs+22*4)(sp)
-	sw	$23,(mipsreg_regs+23*4)(sp)
-#	sw	$26,(mipsreg_regs+26*4)(sp)	# == K0
-#	sw	$27,(mipsreg_regs+27*4)(sp)	# == K1
-#	sw	$29,(mipsreg_regs+29*4)(sp)	# == SP
-	sw	$30,(mipsreg_regs+30*4)(sp)	# == FP
-	sw	$31,(mipsreg_regs+31*4)(sp)	# == RA
+	sw	$16,(mipsreg_regs+16*mips_regsize)(sp)
+	sw	$17,(mipsreg_regs+17*mips_regsize)(sp)	
+	sw	$18,(mipsreg_regs+18*mips_regsize)(sp)
+	sw	$19,(mipsreg_regs+19*mips_regsize)(sp)
+	sw	$20,(mipsreg_regs+20*mips_regsize)(sp)
+	sw	$21,(mipsreg_regs+21*mips_regsize)(sp)
+	sw	$22,(mipsreg_regs+22*mips_regsize)(sp)
+	sw	$23,(mipsreg_regs+23*mips_regsize)(sp)
+#	sw	$26,(mipsreg_regs+26*mips_regsize)(sp)	# == K0
+#	sw	$27,(mipsreg_regs+27*mips_regsize)(sp)	# == K1
+#	sw	$29,(mipsreg_regs+29*mips_regsize)(sp)	# == SP
+	sw	$30,(mipsreg_regs+30*mips_regsize)(sp)	# == FP
+	sw	$31,(mipsreg_regs+31*mips_regsize)(sp)	# == RA
 	sw	$31,(mipsreg_pc)(sp)		# == PC (to help with debugging)
 
 #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
@@ -103,9 +103,20 @@ hal_thread_switch_context:
 	
 #endif
 
+	hal_fpu_save_callee	sp
+
+#ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+
+	hal_fpu_save_caller	sp
+
+#endif
+	
 	addi	t0,sp,mipsreg_size		# save SP in reg dump
-	sw	t0,(mipsreg_regs+29*4)(sp)
+	sw	t0,(mipsreg_regs+29*mips_regsize)(sp)
 
+	mfc0	t1,status			# Save status register
+	sw	t1,mipsreg_sr(sp)
+	
 	sw	sp,0(a1)			# save sp in save loc
 	
 	# Now load the destination thread by dropping through
@@ -124,6 +135,14 @@ hal_thread_load_context:
 	lw	sp,0(a0)			# load new SP directly
 
 #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+
+	hal_fpu_load_caller sp	
+	
+#endif
+			
+	hal_fpu_load_callee sp
+	
+#ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
 	
 	lw	t0,mipsreg_hi(sp)		# load HI and LO regs
 	lw	t1,mipsreg_lo(sp)
@@ -131,47 +150,48 @@ hal_thread_load_context:
 	mtlo	t1
 
 #endif
-		
+
 	# load GPRs
-#	lw	$0,(mipsreg_regs+0*4)(sp)
-	lw	$4,(mipsreg_regs+4*4)(sp)	# A0, must load for thread startup
+#	lw	$0,(mipsreg_regs+0*mips_regsize)(sp)
+	lw	$4,(mipsreg_regs+4*mips_regsize)(sp)	# A0, must load for thread startup
 #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
-	lw	$1,(mipsreg_regs+1*4)(sp)
-	lw	$2,(mipsreg_regs+2*4)(sp)
-	lw	$3,(mipsreg_regs+3*4)(sp)
-	lw	$5,(mipsreg_regs+5*4)(sp)
-	lw	$6,(mipsreg_regs+6*4)(sp)
-	lw	$7,(mipsreg_regs+7*4)(sp)
-	lw	$8,(mipsreg_regs+8*4)(sp)
-	lw	$9,(mipsreg_regs+9*4)(sp)
-	lw	$10,(mipsreg_regs+10*4)(sp)
-	lw	$11,(mipsreg_regs+11*4)(sp)
-	lw	$12,(mipsreg_regs+12*4)(sp)
-	lw	$13,(mipsreg_regs+13*4)(sp)
-	lw	$14,(mipsreg_regs+14*4)(sp)
-	lw	$15,(mipsreg_regs+15*4)(sp)
-	lw	$24,(mipsreg_regs+24*4)(sp)
-	lw	$25,(mipsreg_regs+25*4)(sp)
+	lw	$1,(mipsreg_regs+1*mips_regsize)(sp)
+	lw	$2,(mipsreg_regs+2*mips_regsize)(sp)
+	lw	$3,(mipsreg_regs+3*mips_regsize)(sp)
+	lw	$5,(mipsreg_regs+5*mips_regsize)(sp)
+	lw	$6,(mipsreg_regs+6*mips_regsize)(sp)
+	lw	$7,(mipsreg_regs+7*mips_regsize)(sp)
+	lw	$8,(mipsreg_regs+8*mips_regsize)(sp)
+	lw	$9,(mipsreg_regs+9*mips_regsize)(sp)
+	lw	$10,(mipsreg_regs+10*mips_regsize)(sp)
+	lw	$11,(mipsreg_regs+11*mips_regsize)(sp)
+	lw	$12,(mipsreg_regs+12*mips_regsize)(sp)
+	lw	$13,(mipsreg_regs+13*mips_regsize)(sp)
+	lw	$14,(mipsreg_regs+14*mips_regsize)(sp)
+	lw	$15,(mipsreg_regs+15*mips_regsize)(sp)
+	lw	$24,(mipsreg_regs+24*mips_regsize)(sp)
+	lw	$25,(mipsreg_regs+25*mips_regsize)(sp)
 #endif	
-	lw	$16,(mipsreg_regs+16*4)(sp)
-	lw	$17,(mipsreg_regs+17*4)(sp)
-	lw	$18,(mipsreg_regs+18*4)(sp)
-	lw	$19,(mipsreg_regs+19*4)(sp)
-	lw	$20,(mipsreg_regs+20*4)(sp)
-	lw	$21,(mipsreg_regs+21*4)(sp)
-	lw	$22,(mipsreg_regs+22*4)(sp)
-	lw	$23,(mipsreg_regs+23*4)(sp)
-#	lw	$26,(mipsreg_regs+26*4)(sp)	# == K0
-#	lw	$27,(mipsreg_regs+27*4)(sp)	# == K1
-#	lw	$28,(mipsreg_regs+28*4)(sp)	# == GP
-#	lw	$29,(mipsreg_regs+29*4)(sp)	# == SP
-	lw	$30,(mipsreg_regs+30*4)(sp)	# == FP
-	lw	$31,(mipsreg_regs+31*4)(sp)	# == RA
+	lw	$16,(mipsreg_regs+16*mips_regsize)(sp)
+	lw	$17,(mipsreg_regs+17*mips_regsize)(sp)
+	lw	$18,(mipsreg_regs+18*mips_regsize)(sp)
+	lw	$19,(mipsreg_regs+19*mips_regsize)(sp)
+	lw	$20,(mipsreg_regs+20*mips_regsize)(sp)
+	lw	$21,(mipsreg_regs+21*mips_regsize)(sp)
+	lw	$22,(mipsreg_regs+22*mips_regsize)(sp)
+	lw	$23,(mipsreg_regs+23*mips_regsize)(sp)
+#	lw	$26,(mipsreg_regs+26*mips_regsize)(sp)	# == K0
+#	lw	$27,(mipsreg_regs+27*mips_regsize)(sp)	# == K1
+#	lw	$28,(mipsreg_regs+28*mips_regsize)(sp)	# == GP
+#	lw	$29,(mipsreg_regs+29*mips_regsize)(sp)	# == SP
+	lw	$30,(mipsreg_regs+30*mips_regsize)(sp)	# == FP
+	lw	$31,(mipsreg_regs+31*mips_regsize)(sp)	# == RA
 
-	# Note that the following lw  must go here and not
-	# in the jr delay slot, since it has a delay slot
-	# of its own.
-	lw	sp,(mipsreg_regs+29*4)(sp)	# load SP
+	lw	a2,mipsreg_sr(sp)		# A2 = saved SR
+	lw	sp,(mipsreg_regs+29*mips_regsize)(sp)	# SP = saved SP
+
+	hal_cpu_int_merge a2			# Merge with current SR
+	
 	jr	ra				# return via ra
 	nop					# delay slot - must be nop
 
@@ -200,18 +220,18 @@ hal_thread_load_context:
 	.globl	hal_setjmp
 	.ent	hal_setjmp
 hal_setjmp:
-	sw	$31,CYGARC_JMP_BUF_R31*4(a0)	# ra (link)
-	sw	$30,CYGARC_JMP_BUF_R30*4(a0)
-	sw	$28,CYGARC_JMP_BUF_R28*4(a0)	# gp, optimize out?
-	sw	$23,CYGARC_JMP_BUF_R23*4(a0)
-	sw	$22,CYGARC_JMP_BUF_R22*4(a0)
-	sw	$21,CYGARC_JMP_BUF_R21*4(a0)
-	sw	$20,CYGARC_JMP_BUF_R20*4(a0)
-	sw	$19,CYGARC_JMP_BUF_R19*4(a0)
-	sw	$18,CYGARC_JMP_BUF_R18*4(a0)
-	sw	$17,CYGARC_JMP_BUF_R17*4(a0)
-	sw	$16,CYGARC_JMP_BUF_R16*4(a0)
-	sw	sp,CYGARC_JMP_BUF_SP*4(a0)	# $29
+	sw	$31,CYGARC_JMP_BUF_R31*mips_regsize(a0)	# ra (link)
+	sw	$30,CYGARC_JMP_BUF_R30*mips_regsize(a0)
+	sw	$28,CYGARC_JMP_BUF_R28*mips_regsize(a0)	# gp, optimize out?
+	sw	$23,CYGARC_JMP_BUF_R23*mips_regsize(a0)
+	sw	$22,CYGARC_JMP_BUF_R22*mips_regsize(a0)
+	sw	$21,CYGARC_JMP_BUF_R21*mips_regsize(a0)
+	sw	$20,CYGARC_JMP_BUF_R20*mips_regsize(a0)
+	sw	$19,CYGARC_JMP_BUF_R19*mips_regsize(a0)
+	sw	$18,CYGARC_JMP_BUF_R18*mips_regsize(a0)
+	sw	$17,CYGARC_JMP_BUF_R17*mips_regsize(a0)
+	sw	$16,CYGARC_JMP_BUF_R16*mips_regsize(a0)
+	sw	sp,CYGARC_JMP_BUF_SP*mips_regsize(a0)	# $29
 	li	v0,0
 	jr	ra
 	nop			# delay slot
@@ -220,18 +240,18 @@ hal_setjmp:
 	.globl	hal_longjmp
 	.ent	hal_longjmp
 hal_longjmp:	
-	lw	$31,CYGARC_JMP_BUF_R31*4(a0)	# ra (link)
-	lw	$30,CYGARC_JMP_BUF_R30*4(a0)
-	lw	$28,CYGARC_JMP_BUF_R28*4(a0)	# gp, optimize out?
-	lw	$23,CYGARC_JMP_BUF_R23*4(a0)
-	lw	$22,CYGARC_JMP_BUF_R22*4(a0)
-	lw	$21,CYGARC_JMP_BUF_R21*4(a0)
-	lw	$20,CYGARC_JMP_BUF_R20*4(a0)
-	lw	$19,CYGARC_JMP_BUF_R19*4(a0)
-	lw	$18,CYGARC_JMP_BUF_R18*4(a0)
-	lw	$17,CYGARC_JMP_BUF_R17*4(a0)
-	lw	$16,CYGARC_JMP_BUF_R16*4(a0)
-	lw	sp,CYGARC_JMP_BUF_SP*4(a0)	# $29
+	lw	$31,CYGARC_JMP_BUF_R31*mips_regsize(a0)	# ra (link)
+	lw	$30,CYGARC_JMP_BUF_R30*mips_regsize(a0)
+	lw	$28,CYGARC_JMP_BUF_R28*mips_regsize(a0)	# gp, optimize out?
+	lw	$23,CYGARC_JMP_BUF_R23*mips_regsize(a0)
+	lw	$22,CYGARC_JMP_BUF_R22*mips_regsize(a0)
+	lw	$21,CYGARC_JMP_BUF_R21*mips_regsize(a0)
+	lw	$20,CYGARC_JMP_BUF_R20*mips_regsize(a0)
+	lw	$19,CYGARC_JMP_BUF_R19*mips_regsize(a0)
+	lw	$18,CYGARC_JMP_BUF_R18*mips_regsize(a0)
+	lw	$17,CYGARC_JMP_BUF_R17*mips_regsize(a0)
+	lw	$16,CYGARC_JMP_BUF_R16*mips_regsize(a0)
+	lw	sp,CYGARC_JMP_BUF_SP*mips_regsize(a0)	# $29
 	move	v0,a1
 	jr	ra
 	nop			# delay slot