# HG changeset patch
# User jlarmour
# Date 1333245688 0
# Node ID 180ded1a8753eb6084406c0204fe802bac5f00e2
# Parent  53660cdf5b2219afc218c90925929f3341d49750
* cdl/wallclock_stm32.cdl: Ensure this driver is only active for F1
parts.
* src/stm32_wallclock.cxx (Cyg_WallClock::init_hw_seconds): Add
enables for clocks of devices used by this device.

diff --git a/packages/devs/wallclock/cortexm/stm32/current/ChangeLog b/packages/devs/wallclock/cortexm/stm32/current/ChangeLog
--- a/packages/devs/wallclock/cortexm/stm32/current/ChangeLog
+++ b/packages/devs/wallclock/cortexm/stm32/current/ChangeLog
@@ -1,3 +1,13 @@
+2012-01-19  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/wallclock_stm32.cdl: Ensure this driver is only active for F1
+	parts.
+
+2009-06-29  Nick Garnett  <nickg@ecoscentric.com>
+
+	* src/stm32_wallclock.cxx (Cyg_WallClock::init_hw_seconds): Add
+	enables for clocks of devices used by this device.
+
 2008-11-12  Simon Kallweit  <simon.kallweit@intefo.ch>
 
 	* src/stm32_wallclock.cxx: Using new CYGHWR_HAL_STM32_BD_PROTECT
diff --git a/packages/devs/wallclock/cortexm/stm32/current/cdl/wallclock_stm32.cdl b/packages/devs/wallclock/cortexm/stm32/current/cdl/wallclock_stm32.cdl
--- a/packages/devs/wallclock/cortexm/stm32/current/cdl/wallclock_stm32.cdl
+++ b/packages/devs/wallclock/cortexm/stm32/current/cdl/wallclock_stm32.cdl
@@ -50,12 +50,12 @@
 cdl_package CYGPKG_DEVS_WALLCLOCK_STM32 {
     display       "STM32 RTC wallclock support"
     description   "
-        Wallclock support for on-chip RTC on STM32 devices.driver for the
-        STM32 controller and compatibles"
+        Wallclock support for on-chip RTC on STM32 devices."
 
     parent        CYGPKG_IO_WALLCLOCK
     active_if     CYGPKG_IO_WALLCLOCK
     active_if     CYGPKG_HAL_CORTEXM_STM32
+    active_if     { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F1" }
 
     compile       stm32_wallclock.cxx
 
@@ -77,3 +77,5 @@ cdl_package CYGPKG_DEVS_WALLCLOCK_STM32 
         legal_values        { "LSE" "LSI" "HSE_128" }
     }
 }
+
+# End of wallclock_stm32.cdl
diff --git a/packages/devs/wallclock/cortexm/stm32/current/src/stm32_wallclock.cxx b/packages/devs/wallclock/cortexm/stm32/current/src/stm32_wallclock.cxx
--- a/packages/devs/wallclock/cortexm/stm32/current/src/stm32_wallclock.cxx
+++ b/packages/devs/wallclock/cortexm/stm32/current/src/stm32_wallclock.cxx
@@ -129,6 +129,10 @@ Cyg_WallClock::init_hw_seconds(void)
     cyg_uint32 bdcr, csr;
     cyg_uint32 prescaler = CYGHWR_DEVS_WALLCLOCK_STM32_CLOCK - 1;
     
+    // Enable backup domain and power control
+    CYGHWR_HAL_STM32_CLOCK_ENABLE( CYGHWR_HAL_STM32_CLOCK_BKP );
+    CYGHWR_HAL_STM32_CLOCK_ENABLE( CYGHWR_HAL_STM32_CLOCK_PWR );
+    
     // Reset the backup domain if clock source does not match as
     // RTCSEL can only be written to backup domain once
     HAL_READ_UINT32( rcc+CYGHWR_HAL_STM32_RCC_BDCR, bdcr );