# HG changeset patch # User vae # Date 1366995855 0 # Node ID 1a05365e93b43460bbe2833e6dbabc562150f425 # Parent e81ceb154dcd7e7fa43fdc14dc53374af3e4360f Add Freescale I2C driver and I2C driver entries for Kinetis targets diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog b/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog --- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog +++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog @@ -1,3 +1,9 @@ +2013-04-09 Ilija Kocho + + * cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: + * include/plf_io.h: + Implemented support for I2C [Bugzilla 1001397] + 2013-04-01 Ilija Kocho * src/twr_k70f120m_misc.c: Clock gating synchronised with variant. diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl b/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl --- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl +++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl @@ -80,9 +80,11 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T CYGNUM_DEVS_KINETIS_FLASH_LONGWORD_SIZE == 8 } implements CYGINT_IO_SERIAL_FREESCALE_UART2 - + implements CYGINT_IO_FREESCALE_I2C0 + implements CYGINT_HAL_FREESCALE_UART2 implements CYGINT_HAL_CORTEXM_KINETIS_RTC + implements CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 implements CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1 implements CYGINT_HAL_CORTEXM_KINETIS_150 diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_io.h b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_io.h --- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_io.h +++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_io.h @@ -143,6 +143,12 @@ #define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4 CYGHWR_HAL_KINETIS_PIN_NONE #define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5 CYGHWR_HAL_KINETIS_PIN_NONE +// I2C +// I2C Pins + +# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(E, 18, 4, 0) +# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(E, 19, 4, 0) + //============================================================================= // Memory access checks. // diff --git a/packages/hal/cortexm/kinetis/var/current/ChangeLog b/packages/hal/cortexm/kinetis/var/current/ChangeLog --- a/packages/hal/cortexm/kinetis/var/current/ChangeLog +++ b/packages/hal/cortexm/kinetis/var/current/ChangeLog @@ -1,3 +1,9 @@ +2013-04-09 Tomas Frydrych + + * cdl/kinetis_irq_scheme.cdl: + * include/var_io_devs.h: + Implemented support for I2C [Bugzilla 1001397] + 2013-04-01 Ilija Kocho * include/var_io.h, include/var_io_clkgat.h, include/var_io_devs.h, diff --git a/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl b/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl --- a/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl +++ b/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl @@ -177,6 +177,25 @@ default_value 0xD0 } } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_I2C { + display "I2C interrupt priorities" + flavor none + no_define + + for { set ::bus 0 } { $::bus < 2 } { incr ::bus } { + + cdl_option CYGNUM_DEVS_FREESCALE_I2C[set ::bus]_IRQ_PRIORITY { + display "I2C bus [set ::bus] interrupt priority" + flavor data + active_if CYGHWR_DEVS_FREESCALE_I2C[set ::bus] + default_value 0x90 + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + } + } + } + # } diff --git a/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h b/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h --- a/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h +++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h @@ -214,6 +214,40 @@ CYGHWR_HAL_KINETIS_PORT_PCR_PS_M) #endif +//--------------------------------------------------------------------------- +// I2C +// Lend some HAL dependent macros to I2C device driver +// Base pointers +#define CYGADDR_IO_I2C_FREESCALE_I2C0_BASE (0x40066000) +#define CYGADDR_IO_I2C_FREESCALE_I2C1_BASE (0x40067000) +// Clocking +#define CYGHWR_IO_I2C_FREESCALE_I2C_CLOCK hal_get_peripheral_clock() +#define CYGHWR_IO_FREESCALE_I2C0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_I2C0 +#define CYGHWR_IO_FREESCALE_I2C1_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_I2C1 +// Pins +# define CYGHWR_IO_FREESCALE_I2C_PIN(__pin) hal_set_pin_function(__pin) + +# ifndef CYGHWR_IO_FREESCALE_I2C_FREQUENCY_TABLE +// Fix an error in Kinetis I2C Manual. There is an unconfirmed +// error in Kinetis I2C divider and hold value table. +#if 0 // Values as are in Kinetis Reference Manuals +#define I2C_FREQ_TABLE_ENTRY_8 28 +#define I2C_FREQ_TABLE_ENTRY_9 32 +#else // Values that give correct result according to measurements +#define I2C_FREQ_TABLE_ENTRY_8 30 +#define I2C_FREQ_TABLE_ENTRY_9 34 +#endif +typedef cyg_uint16 dev_i2c_freescale_frequency_entry_t; +# define CYGHWR_IO_FREESCALE_I2C_FREQUENCY_TABLE \ + 20, 22, 24, 26, 28, 30, 34, 40, I2C_FREQ_TABLE_ENTRY_8, I2C_FREQ_TABLE_ENTRY_9, \ + 36, 40, 44, 48, 56, 68, 48, 56, 64, \ + 72, 80, 88, 104, 128, 80, 96, 112, 128, 144, 160, 192, 240, 160, 192, 224, \ + 256, 288, 320, 384, 480, 320, 384, 448, 512, 576, 640, 768, 960, 640, 768, \ + 896, 1024, 1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840 + + +# endif // CYGHWR_IO_FREESCALE_I2C_FREQUENCY_TABLE + // DMA MUX ------------------------------------------------------------------ // DMAMUX DMA request sources #define FREESCALE_DMAMUX_SRC_KINETIS_DISABLE 0