# HG changeset patch
# User gthomas
# Date 1068064313 0
# Node ID 2aef5613bac93181d34221975e40e2ba4853b39b
# Parent  83bf536405e05fc656082e8f91adec4fe6a449e4
Some CERF cube cleanups

diff --git a/packages/hal/arm/sa11x0/cerf/current/ChangeLog b/packages/hal/arm/sa11x0/cerf/current/ChangeLog
--- a/packages/hal/arm/sa11x0/cerf/current/ChangeLog
+++ b/packages/hal/arm/sa11x0/cerf/current/ChangeLog
@@ -1,3 +1,9 @@
+2003-11-01  Gary Thomas  <gary@mlbassoc.com>
+
+	* cdl/hal_arm_sa11x0_cerf.cdl: Make port 1 (uart3) be default
+	console/debug channel.  This is because the CerfCube only has
+	uart3 [physically] exposed, while the CerfBoard has uart1 as well.
+
 2003-09-21  Gary Thomas  <gary@mlbassoc.com>
 
 	* misc/redboot_RAM.ecm: 
diff --git a/packages/hal/arm/sa11x0/cerf/current/cdl/hal_arm_sa11x0_cerf.cdl b/packages/hal/arm/sa11x0/cerf/current/cdl/hal_arm_sa11x0_cerf.cdl
--- a/packages/hal/arm/sa11x0/cerf/current/cdl/hal_arm_sa11x0_cerf.cdl
+++ b/packages/hal/arm/sa11x0/cerf/current/cdl/hal_arm_sa11x0_cerf.cdl
@@ -136,7 +136,7 @@ cdl_package CYGPKG_HAL_ARM_SA11X0_CERF {
         active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
         flavor data
         legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
-        default_value    0
+        default_value    CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
         description      "
             The cerf board has 3 serial ports. This option
             chooses which port will be used to connect to a host
@@ -146,8 +146,8 @@ cdl_package CYGPKG_HAL_ARM_SA11X0_CERF {
      cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
          display      "Default console channel."
          flavor       data
-         legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
-         calculated   0
+         legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+         calculated   1
      }
  
      cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
diff --git a/packages/hal/arm/sa11x0/cerf/current/misc/redboot_RAM.ecm b/packages/hal/arm/sa11x0/cerf/current/misc/redboot_RAM.ecm
--- a/packages/hal/arm/sa11x0/cerf/current/misc/redboot_RAM.ecm
+++ b/packages/hal/arm/sa11x0/cerf/current/misc/redboot_RAM.ecm
@@ -30,6 +30,7 @@ cdl_configuration eCos {
     package -template CYGPKG_REDBOOT current ;
     package -template CYGPKG_ISOINFRA current ;
     package -template CYGPKG_LIBC_STRING current ;
+    package -template CYGPKG_CRC current ;
     package CYGPKG_NS_DNS current ;
     package CYGPKG_IO_FLASH current ;
     package CYGPKG_IO_ETH_DRIVERS current ;
@@ -84,6 +85,10 @@ cdl_component CYGPKG_REDBOOT_NETWORKING 
     user_value 1
 };
 
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+    user_value 0x00040000
+};
+
 cdl_component CYGSEM_REDBOOT_FLASH_CONFIG {
     user_value 1
 };
diff --git a/packages/hal/arm/sa11x0/cerf/current/misc/redboot_ROM.ecm b/packages/hal/arm/sa11x0/cerf/current/misc/redboot_ROM.ecm
--- a/packages/hal/arm/sa11x0/cerf/current/misc/redboot_ROM.ecm
+++ b/packages/hal/arm/sa11x0/cerf/current/misc/redboot_ROM.ecm
@@ -30,6 +30,7 @@ cdl_configuration eCos {
     package -template CYGPKG_REDBOOT current ;
     package -template CYGPKG_ISOINFRA current ;
     package -template CYGPKG_LIBC_STRING current ;
+    package -template CYGPKG_CRC current ;
     package CYGPKG_NS_DNS current ;
     package CYGPKG_IO_FLASH current ;
     package CYGPKG_IO_ETH_DRIVERS current ;
@@ -88,6 +89,10 @@ cdl_component CYGPKG_REDBOOT_NETWORKING 
     user_value 1
 };
 
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+    user_value 0x00040000
+};
+
 cdl_component CYGSEM_REDBOOT_FLASH_CONFIG {
     user_value 1
 };
diff --git a/packages/hal/arm/sa11x0/cerf/current/src/cerf_misc.c b/packages/hal/arm/sa11x0/cerf/current/src/cerf_misc.c
--- a/packages/hal/arm/sa11x0/cerf/current/src/cerf_misc.c
+++ b/packages/hal/arm/sa11x0/cerf/current/src/cerf_misc.c
@@ -131,10 +131,16 @@ cerf_BCR(unsigned long mask, unsigned lo
 void
 plf_hardware_init(void)
 {
+#if 0 // Is this correct?
     // Force "alternate" use of GPIO pins used for LCD screen
     *SA11X0_GPIO_ALTERNATE_FUNCTION |= 0x080003FC;  // Bits 2..9
     *SA11X0_GPIO_PIN_DIRECTION |= 0x080003FC;  // Bits 2..9
     *SA11X0_GPIO_PIN_OUTPUT_CLEAR = 0x080003FC;  // Bits 2..9
+#else
+    // Force "alternate" use of GPIO pins
+    *SA11X0_GPIO_ALTERNATE_FUNCTION  = 0x08000000;
+    *SA11X0_GPIO_PIN_DIRECTION       = 0x0B20000F;
+#endif
     *SA11X0_GPIO_PIN_OUTPUT_SET = 0x08000000;  // CRYSTAL WAKEUP(GPIO27)
 
     // Toggle A0 connected to the SBHE line on the Crystal chip.