# HG changeset patch
# User gthomas
# Date 1066059375 0
# Node ID 2d5ff91b40f81c6f21ff8c85a7ef76ee054717fc
# Parent  b770a5c7205040d955c2bf8e2695eac06f44ffce
Fix problem where serial drivers cause debug lock up

diff --git a/packages/devs/serial/powerpc/quicc/current/ChangeLog b/packages/devs/serial/powerpc/quicc/current/ChangeLog
--- a/packages/devs/serial/powerpc/quicc/current/ChangeLog
+++ b/packages/devs/serial/powerpc/quicc/current/ChangeLog
@@ -1,3 +1,8 @@
+2003-10-13  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/quicc_smc_serial.c: Add some I/O barriers to make sure that
+	operations happen in the correct order.  Fixes BUG #90391
+
 2003-10-08  Gary Thomas  <gary@mlbassoc.com>
 
 	* src/quicc_smc_serial.c: Fix compile error for Adder-II (852T)
diff --git a/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c b/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
--- a/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
+++ b/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
@@ -343,17 +343,20 @@ quicc_smc_serial_config_port(serial_chan
     if (baud_divisor == 0) return false;
     // Disable channel during setup
     ctl->smc_smcmr = QUICC_SMCMR_UART;  // Disabled, UART mode
+    HAL_IO_BARRIER();  // Inforce I/O ordering
     // Disable port interrupts while changing hardware
     _lcr = smc_select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | 
         smc_select_stop_bits[new_config->stop] |
         smc_select_parity[new_config->parity];
     // Stop transmitter while changing baud rate
     eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_StopTx;
+    HAL_IO_BARRIER();  // Inforce I/O ordering
     // Set baud rate generator
     *smc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1);
 
     // Enable channel with new configuration
     ctl->smc_smcmr = QUICC_SMCMR_UART|QUICC_SMCMR_TEN|QUICC_SMCMR_REN|_lcr;
+    HAL_IO_BARRIER();  // Inforce I/O ordering
     eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_RestartTx;
     if (new_config != &chan->config) {
         chan->config = *new_config;
@@ -376,15 +379,16 @@ quicc_smc_serial_init_info(quicc_sxx_ser
     EPPC *eppc = eppc_base();
     struct cp_bufdesc *txbd, *rxbd;
     int i;
-
-    // Disable channel during setup
-    ctl->smc_smcmr = QUICC_SMCMR_UART;  // Disabled, UART mode
+    
     smc_chan->pram = (void *)uart_pram;
     smc_chan->ctl = (void *)ctl;
 
     // Set up baud rate generator
     smc_chan->brg = _mpc8xx_allocate_brg(port);
 
+    // Disable channel during setup
+    ctl->smc_smcmr = QUICC_SMCMR_UART;  // Disabled, UART mode
+
     /*
      *  Set up the PortB pins for UART operation.
      *  Set PAR and DIR to allow SMCTXDx and SMRXDx
@@ -449,7 +453,9 @@ quicc_smc_serial_init_info(quicc_sxx_ser
     /*
      *  Reset Rx & Tx params
      */
+    HAL_IO_BARRIER();  // Inforce I/O ordering
     eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_InitTxRx;
+    HAL_IO_BARRIER();  // Inforce I/O ordering
     /*
      *  Clear any previous events. Enable interrupts.
      *  (Section 16.15.7.14 and 16.15.7.15)
@@ -471,6 +477,7 @@ quicc_scc_serial_config_port(serial_chan
     // Set baud rate generator
     *scc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1);
     // Disable channel during setup
+    HAL_IO_BARRIER();  // Inforce I/O ordering
     regs->scc_gsmr_l = 0;
     regs->scc_psmr = QUICC_SCC_PSMR_ASYNC | 
         scc_select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | 
@@ -484,8 +491,10 @@ quicc_scc_serial_config_port(serial_chan
     /*
      *  Init Rx & Tx params for SCCX
      */
+    HAL_IO_BARRIER();  // Inforce I/O ordering
     eppc->cp_cr = QUICC_CPM_CR_INIT_TXRX | scc_chan->channel | QUICC_CPM_CR_BUSY;
 
+    HAL_IO_BARRIER();  // Inforce I/O ordering
     regs->scc_gsmr_l |= (QUICC_SCC_GSMR_L_Tx | QUICC_SCC_GSMR_L_Rx);  // Enable Rx, Tx
     if (new_config != &chan->config) {
         chan->config = *new_config;
@@ -594,11 +603,13 @@ quicc_scc_serial_init_info(quicc_sxx_ser
     /*
      *  Reset Rx & Tx params
      */
+    HAL_IO_BARRIER();  // Inforce I/O ordering
     eppc->cp_cr = scc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_InitTxRx;
     /*
      *  Clear any previous events. Enable interrupts.
      *  (Section 16.15.7.14 and 16.15.7.15)
      */
+    HAL_IO_BARRIER();  // Inforce I/O ordering
     ctl->scc_scce = 0xFFFF;
     ctl->scc_sccm = (QUICC_SCCE_BSY | QUICC_SCCE_TX | QUICC_SCCE_RX);
 }