# HG changeset patch
# User vae
# Date 1366994568 0
# Node ID 50ae55e2e856be823735610f7cfea3bf812cb125
# Parent  c0f0661703ee2468f3d9f7daa1ba49777c80da5f
Implemented support for I2C  [Bugzilla 1001397]

diff --git a/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog b/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog
--- a/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog
@@ -1,3 +1,9 @@
+2013-04-09  Tomas Frydrych <tomas@sleepfive.com>
+
+	* cdl/hal_cortexm_kinetis_kwikstik.cdl:
+	* include/plf_io.h:
+	Implemented support for I2C  [Bugzilla 1001397]
+
 2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* src/kwikstik_misc.c: Clock gating synchronised with variant.
diff --git a/packages/hal/cortexm/kinetis/kwikstik/current/cdl/hal_cortexm_kinetis_kwikstik.cdl b/packages/hal/cortexm/kinetis/kwikstik/current/cdl/hal_cortexm_kinetis_kwikstik.cdl
--- a/packages/hal/cortexm/kinetis/kwikstik/current/cdl/hal_cortexm_kinetis_kwikstik.cdl
+++ b/packages/hal/cortexm/kinetis/kwikstik/current/cdl/hal_cortexm_kinetis_kwikstik.cdl
@@ -69,6 +69,7 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_K
                     implies CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 4096 }
 
     implements    CYGINT_IO_SERIAL_FREESCALE_UART5
+    implements    CYGINT_IO_FREESCALE_I2C1
     implements    CYGINT_HAL_FREESCALE_UART5
     implements    CYGINT_HAL_CORTEXM_KINETIS_RTC
 
diff --git a/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_io.h b/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_io.h
--- a/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_io.h
+++ b/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_io.h
@@ -86,12 +86,8 @@
 #endif
 
 // I2C pins
-#ifndef CYGHWR_HAL_I2C0_PIN_SDA
-# define CYGHWR_HAL_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(B, 1, 2, 0)
-# define CYGHWR_HAL_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(B, 0, 2, 0)
-# define CYGHWR_HAL_I2C1_PIN_SDA CYGHWR_HAL_KINETIS_PIN(C, 11, 2, 0)
-# define CYGHWR_HAL_I2C1_PIN_SCL CYGHWR_HAL_KINETIS_PIN(C, 10, 2, 0)
-#endif
+# define CYGHWR_HAL_I2C1_PIN_SDA CYGHWR_HAL_KINETIS_PIN(E, 0, 6, 0)
+# define CYGHWR_HAL_I2C1_PIN_SCL CYGHWR_HAL_KINETIS_PIN(E, 1, 6, 0)
 
 //=============================================================================
 // Memory access checks.
diff --git a/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog b/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog
--- a/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog
@@ -1,3 +1,9 @@
+2013-04-09  Tomas Frydrych <tomas@sleepfive.com>
+
+	* cdl/hal_cortexm_kinetis_twr_k40x256.cdl:
+	* include/plf_io.h:
+	Implemented support for I2C  [Bugzilla 1001397]
+
 2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* src/twr_k40x256_misc.c: Clock gating synchronised with variant.
diff --git a/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl b/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl
--- a/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl
+++ b/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl
@@ -68,6 +68,9 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T
                     implies CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 4096 }
 
     implements    CYGINT_IO_SERIAL_FREESCALE_UART3
+    implements    CYGINT_IO_FREESCALE_I2C0
+    implements    CYGINT_IO_FREESCALE_I2C1
+    
     implements    CYGINT_HAL_FREESCALE_UART3
     implements    CYGINT_HAL_CORTEXM_KINETIS_RTC
 
diff --git a/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_io.h b/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_io.h
--- a/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_io.h
+++ b/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_io.h
@@ -84,6 +84,14 @@
 #define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4  CYGHWR_HAL_KINETIS_PIN_NONE
 #define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5  CYGHWR_HAL_KINETIS_PIN_NONE
 
+// I2C
+// I2C Pins
+
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(B, 2, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(B, 3, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C1_PIN_SDA CYGHWR_HAL_KINETIS_PIN(C, 11, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C1_PIN_SCL CYGHWR_HAL_KINETIS_PIN(C, 10, 2, 0)
+
 //=============================================================================
 // Memory access checks.
 //
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog b/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog
--- a/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog
@@ -1,3 +1,9 @@
+2013-04-09  Tomas Frydrych <tomas@sleepfive.com>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512.cdl:
+	* include/plf_io.h:
+	Implemented support for I2C  [Bugzilla 1001397]
+
 2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* src/twr_k60n512_misc.c: Clock gating synchronised with variant.
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512/current/cdl/hal_cortexm_kinetis_twr_k60n512.cdl b/packages/hal/cortexm/kinetis/twr_k60n512/current/cdl/hal_cortexm_kinetis_twr_k60n512.cdl
--- a/packages/hal/cortexm/kinetis/twr_k60n512/current/cdl/hal_cortexm_kinetis_twr_k60n512.cdl
+++ b/packages/hal/cortexm/kinetis/twr_k60n512/current/cdl/hal_cortexm_kinetis_twr_k60n512.cdl
@@ -58,10 +58,11 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T
                   implies CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" }
 
     implements    CYGINT_IO_SERIAL_FREESCALE_UART3
+    implements    CYGINT_IO_FREESCALE_I2C0
+    
     implements    CYGINT_HAL_FREESCALE_UART3
     implements    CYGINT_HAL_CORTEXM_KINETIS_RTC
 
-
     description   "
         The Freescale TWR K60N512 Platform HAL package provides the support
         needed to run eCos on the TWR K60N512 development system. This package
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_io.h b/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_io.h
--- a/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_io.h
+++ b/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_io.h
@@ -124,7 +124,11 @@
 #define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4  CYGHWR_HAL_KINETIS_PIN_NONE
 #define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5  CYGHWR_HAL_KINETIS_PIN_NONE
 
+// I2C
+// I2C Pins
 
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(D, 9, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(D, 8, 2, 0)
 
 //=============================================================================
 // Memory access checks.
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog
@@ -1,3 +1,9 @@
+2013-04-09  Ilija Kocho <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl:
+	* include/plf_io.h:
+	Implemented support for I2C  [Bugzilla 1001397]
+
 2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* src/twr_k60n512_fxm_misc.c: Clock gating synchronised with variant.
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl
@@ -55,6 +55,7 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T
     requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
 
     implements    CYGINT_HAL_CORTEXM_KINETIS_RTC
+    implements    CYGINT_IO_FREESCALE_I2C0
 
     description   "
     The Freescale TWR K60N512 FXM Platform package provides the support
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_io.h b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_io.h
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_io.h
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_io.h
@@ -169,6 +169,11 @@
 #define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4  CYGHWR_HAL_KINETIS_PIN_NONE
 #define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5  CYGHWR_HAL_KINETIS_PIN_NONE
 
+// I2C
+// I2C Pins
+
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(D, 9, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(D, 8, 2, 0)
 
 //=============================================================================
 // Memory access checks.