Description

# HG changeset patch # User vae # Date 1337376443 0 # Node ID 58eda6fed5a511bb7eda7892da1bce3dc6181e2d # Parent 7c9ce2220671936f4d9cd863a262b333d5b58f05 New files -- Kinetis variant documentation. [Bug 1001580] diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog b/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog --- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog +++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog @@ -1,3 +1,8 @@ +2012-05-18 Ilija Kocho + + * doc/twr_k70f120m.sgml: + New file -- TWR-K70F120M platform documentation. [Bug 1001580] + 2012-05-17 Ilija Kocho * cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/doc/twr_k70f120m.sgml b/packages/hal/cortexm/kinetis/twr_k70f120m/current/doc/twr_k70f120m.sgml new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/doc/twr_k70f120m.sgml @@ -0,0 +1,165 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + TWR-K70F120M Development kit + + + CYGPKG_HAL_CORTEXM_KINETIS_TWR_K70F120M + eCos Support for Freescale TWR-K70F120M development kit + + + Description + + The Freescale TWR-K70F120M is a development kit for + Freescale Kinetis Cortex-M4 based micro-controllers. It covers K70, K60, K10 and K20 + microcontroller subfamilies. K70FN1M0 is a high end member comprising on-chip 1 MiB FLASH + and 128 KiB SRAM memory as well as a 16 KiB unified cache. + K70 parts are equipped with a rich set of communication interfaces including Ethernet USB, UARTs + CAN, SPI and I2C. They also have a Graphics controller and a DMA controller, as well as FlexBus and SDRAM + external memory interfaces. They are mixed signal devices featuring a 16 bit ADC and a 12 bit DAC. + + + Configuration + Hardware Setup + TWR-K70F120M setup + + Factory jumper settings on TWR-K70F120M are fitted for standalone operation of the board. + In order to use it with the Ethernet PHY from TWR-SER, some jumpers have to be changed + on both TWR-K70F120M and TWR-SER. Jumper settings for TWR-SER are given in + TWR-K60N512 Configuration and here are the TWR-K70F120M + settings. + + TWR-K70F120M Jumper setting + + + + + + + Jumper + Setting + Description + + + + + J19 + OFF + On board 50MHz oscillator is not powered + + + +

+ + + eCos Configuration + Clocking + + The TWR-K70F120M package defines requirements for the platform clocking. + + + Memory + + The K70 has two 64 KiB SRAM banks giving a total of 128KiB on chip SRAM. In addition, on-board there is + 128 MiB of external RAM (SDRAM) and 256 MiB of NAND Flash. + External RAM is divided in two regions: + + + + ram + Regular RAM. + + + ramnc + Non cached RAM. This region contains .noncache section. + + + + + Memory layouts + + Additional platform memory layouts follow the variant + ones only by putting all RAM sections except .sram in the ram region. + The linker file names incorporate the segment _extram_. + + Linker + Script Location + + Linker scripts are found at: + hal/kinetis/twr-k70f120m/<version>/include/pkgconf + + + Linker Script Naming + + Linker script file names have following form: + mlt_kinetis_<NVM>_<SRAM>_<STARTUP_extram.ldi + where PLF is an optional extension for platform specific scripts and + other segments have meaning as described here. + + + + Startup types + + The platform startup CYG_HAL_STARTUP_PLF offers the following startups: + + + + ROM (Platform) + Normal startup for stand-alone operation. The eCos image has to be flashed + in internal flash. External RAM is used as main memory. + + + Note: This startup has a name like the one in the variant but generates different images + by invoking a different set of linker scripts. + + + RAM (Platform) + The image is loaded in external RAM by means of RedBoot. + + + ByVariant + Activates the variant startup types. + + + + + + + diff --git a/packages/hal/cortexm/kinetis/var/current/ChangeLog b/packages/hal/cortexm/kinetis/var/current/ChangeLog --- a/packages/hal/cortexm/kinetis/var/current/ChangeLog +++ b/packages/hal/cortexm/kinetis/var/current/ChangeLog @@ -1,3 +1,10 @@ +2012-05-18 Ilija Kocho + + * doc/kinetis_begin.sgml: + * doc/kinetis_end.sgml: + * doc/kinetis.sgml: + New files -- Kinetis variant documentation. [Bug 1001580] + 2012-05-17 Ilija Kocho * cdl/hal_cortexm_kinetis.cdl: @@ -16,8 +23,8 @@ 2012-05-04 Ilija Kocho @@ -31,7 +38,7 @@ 2012-01-11 Tomas Frydrych * cdl/kinetis_irq_scheme.cdl - Centralized IRQ priority scheme. + Centralized IRQ priority scheme. * cdl/hal_cortexm_kinetis.cdl: * cdl/kinetis_flexbus.cdl diff --git a/packages/hal/cortexm/kinetis/var/current/doc/kinetis.sgml b/packages/hal/cortexm/kinetis/var/current/doc/kinetis.sgml new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/doc/kinetis.sgml @@ -0,0 +1,303 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Freescale Kinetis Variant + + + CYGPKG_HAL_CORTEXM_KINETIS + eCos Support for Freescale Kinetis Micro-controllers + + + Description + + Kinetis is a Freescale microcontroller family based on the ARM Cortex-M4 core. The + family consists of subfamilies: K10, K20, K30, K40, K50, K60 and K70 + that gradually add-on performance and features. + + + The Kinetis variant HAL provides generic support for hardware found on some + or all Kinetis members. The variant package CYGPKG_HAL_CORTEXM_KINETIS + provides configurable components that aim to support the complete set of options + found in the Kinetis family. + + + What's supported + + The current Kinetis software includes a Kinetis variant HAL, some Platform BSPs, + as well as DMA, UART, Wallclock, Ethernet and SPI support. + + + Configuration + Kinetis is a set of families of micro-controllers packed with highly configurable components. + In order to facilitate system configuration for the user, the CDL configuration items are organized as a set of + expert components. Typically, for a given peripheral, the user chooses the required hardware + options and desirable parameters, and the respective CDL configuration options and settings are calculated from these. + If it is not possible to achieve exact values, the configurator attempts to provide + approximate settings, then the user can manually do the fine tuning. + Kinetis Part Selection + + Within a family and/or across families the chips are further differentiated by their features + such as: optional FPU, amount of memory, etc. The family member options are reflected in the + controller naming scheme (see respective Freescale Kinetis product brief(s) and reference manual(s)). + The Kinetis part builder CYGHWR_HAL_CORTEXM_KINETIS, respects this naming scheme and + enables the user to interactively configure eCos for the desired part by selecting + the requested part's name segments. + Based on user input, the CDL computes the part-specific eCos configuration. This includes calculation + of on-chip FLASH and SRAM layout as well as the activation/deactivation of options such as FPU and + Ethernet. + + + Clocking + + Kinetis is packed with a rich set of clocking options provided by the Multipurpose Clock Generator - MCG. + Dependent on the part, MCG can have outlets for one or two external frequency reference sources + OSC and OSC1 and one + or two PLL oscillators PLL and PLL1. + Each of the external frequency reference sources can be either a crystal or external + oscillator and associated with either or both PLL oscillators. OSC can also be a + reference source for the FLL oscillator. + Besides OSC and OSC1, there are additional clock sources + including two RC oscillators and a (battery backed) RTC clock with it's own 32768 Hz crystal oscillator. + MCG gives the user a wide choice of system and peripheral clock source(s) that can be + external clock(s), internal clocks, a PLL or the FLL. An external or on-chip + oscillator can be used as a system clock or as a reference for PLL/FLL oscillator(s). + + In the documentation of Kinetis parts with two oscillators, OSC + and PLL are described as OSC0 and PLL0 respectively. + + + Clocking component CYGHWR_HAL_CORTEXM_KINETIS_CLOCKING provides some expert + functionality in order to facilitate clock system configuration. Normally, the user sets requirements: + clock source, clock reference, desired core frequency and upper limits for peripheral + clock frequencies. The component automatically calculates MCG and other peripheral register + settings in order to achieve the required clock frequencies. This setting is not always perfect but + fits (exactly or close) for commonly used frequencies. If necessary, the user can fine tune the + clock settings interactively using the eCos Configuration Tool. + The two clock sources are named: + + + + System clock + The clock source that provides the clock for the Cortex-M core. + It may also provide the clock for some peripherals. + + + Auxiliary clock + This is optional and may provide a clock for peripherals but not for the Cortex-M core. + + + + The user can select which source is the system clock. The choices for system clock are: PLL, + FLL, External reference clock and, when available, PLL1. + The auxiliary clock, when available is: PLL if PLL1 is selected + for system the clock or PLL1 if any other source is selected for the system clock. + + + Memory layouts + + The memory layouts and startup types which don't employ external memory should be applicable to all + Kinetis platforms so they are defined and maintained at the variant level. + This is somewhat different than common eCos practice but has some advantages brought by universal, + single copy linker scripts for single chip configurations. The linker scripts are further enhanced/generalized + by utilization of macros provided by CDL and calculated on the basis of the + selected Kinetis part. + + Variant Linker + Script Location + + Variant linker scripts are found at: + hal/kinetis/var/<version>/include/pkgconf + + + Linker Script Naming + + Linker script file names are composed of segments + mlt_kinetis_<NVM>_<SRAM>_<STARTUP>[_<PLF>].ldi + where PLF is an optional extension for platform specific scripts and + other segments have meanings as described in the following table. + + Linker script name segments + + + + + + + Segment + Description + Values + + + + + NVM + Kinetis non-volatile memory configuration + + flash, + flexnvm + + + + SRAM + SRAM memory sectioning + + unisram, + sram2s + + + + STARTUP + Startup type + + rom, + sram + + + + +

+ + Never attempt to flash Kinetis with an image for SRAM startup. SRAM startup images + do not contain a .flash_conf section so random contents may be written in + flash protection area and lock your Kinetis device. This lock-out can be permanent. + + + Platform Specific Memory Layouts + + Platforms, if needed, can provide their own layouts in addition to the variant ones. Typically + they will cover systems with external memory. The + startup type implicitly determines whether variant and platform defined + layout shall be used. + + + On-chip SRAM + + Kinetis on chip SRAM memory consists of two equal banks that occupy consecutive locations anchored + below and above 0x20000000. This fact is reflected in memory layout scripts. + There are linker scripts that treat SRAM as a single section (unisram) or as + 2 separate sections (sram2s). + + + On-chip FLASH + + Kinetis on-chip flash contains a special area [0x400-0x40F] + that holds the flash security configuration. In order to preserve this area from + accidental writing and at the same time provide regular access, + a custom linker section .flash_conf is created. In addition, in order + to utilize the FLASH pool below 0x400 the USER_SECTION + .kinetis_misc is defined. This section typically contains + code parts from kinetis_misc.c. + + + Cache + + Kinetis members with operating frequencies of 120 MHz and 150 MHz are equipped with cache memory. + Due to the Harvard architecture, there are two unified cache memories connected to code + - PC and system - PS buses respectively. One of the + issues with caching is operation with bus masters such as DMA, Ethernet controller, etc. + In order to keep shared data such + as buffers and transfer descriptors synchronous, a part of cached data may have to be flushed + and/or invalidated. In some cases, an alternative can be the usage of non-cacheable memory + regions. CYGHWR_HAL_NON_CACHABLE provides for the configuration of non-cacheable + memory. If some bus masters have provision for non-cacheable memory, such configuration options + can be parented by CYGHWR_HAL_NON_CACHABLE. + + + Startup types + + There are two levels of startup type: + + + + Variant CYG_HAL_STARTUP_VAR + This is always present and provides startup + types for systems without external memory. + + + Platform CYG_HAL_STARTUP_PLF + This is optional and is + provided by a platform package. Typically it provides startup types for systems + that employ external memory. + + + + + + When present, the platform startup overloads the variant startup and has precedence over it. + User can activate the variant startup by setting platform startup to + ByVariant. + + Startup types provided variant + + The following startup types are provided for Kinetis at the variant level: + + + + ROM + Normal startup for stand-alone operation. eCos image has to be flashed + in internal flash; + + + SRAM + Image is loaded in internal SRAM by means of JTAG/SWD and executed + under debugger control. + + + (IMPORTANT) Never, ever attempt to flash Kinetis with an image for SRAM startup. + SRAM startup images do not contain a .flash_conf section so random contents + may be written to the flash protection area and lock your Kinetis device. This lock-out can be permanent. + + + + Interrupt priority scheme + + In case of multiple simultaneous interrupts, interrupt service request resolution is based + on a relative comparison of interrupt priorities, rather than on individual interrupt priority values. + Interrupt priority scheme gives a consolidated overview and control + of priorities of all interrupt sources. Interrupt priorities can be provided by either variant + CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR + or platform CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME. + + + + + + + diff --git a/packages/hal/cortexm/kinetis/var/current/doc/kinetis_begin.sgml b/packages/hal/cortexm/kinetis/var/current/doc/kinetis_begin.sgml new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/doc/kinetis_begin.sgml @@ -0,0 +1,37 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Freescale Kinetis Family Support diff --git a/packages/hal/cortexm/kinetis/var/current/doc/kinetis_end.sgml b/packages/hal/cortexm/kinetis/var/current/doc/kinetis_end.sgml new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/doc/kinetis_end.sgml @@ -0,0 +1,37 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +