# HG changeset patch
# User vae
# Date 1327525959 0
# Node ID 5a84386f040d5609def6fd6b731e8f75d6cb68ea
# Parent  3a95d9066d91e8f52b5c9f065fa349ddd69800d0
Fixed interrupt priority. [ Bugzilla 1001432 ]

diff --git a/packages/devs/serial/arm/lpc24xx/current/ChangeLog b/packages/devs/serial/arm/lpc24xx/current/ChangeLog
--- a/packages/devs/serial/arm/lpc24xx/current/ChangeLog
+++ b/packages/devs/serial/arm/lpc24xx/current/ChangeLog
@@ -1,3 +1,8 @@
+2011-12-21  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/ser_arm_lpc24xx.cdl:
+	Fixed interrupt priority. [ Bugzilla 1001432 ]
+	
 2010-12-29  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* cdl/ser_arm_lpc24xx.cdl:
diff --git a/packages/devs/serial/arm/lpc24xx/current/cdl/ser_arm_lpc24xx.cdl b/packages/devs/serial/arm/lpc24xx/current/cdl/ser_arm_lpc24xx.cdl
--- a/packages/devs/serial/arm/lpc24xx/current/cdl/ser_arm_lpc24xx.cdl
+++ b/packages/devs/serial/arm/lpc24xx/current/cdl/ser_arm_lpc24xx.cdl
@@ -83,13 +83,13 @@ cdl_package CYGPKG_IO_SERIAL_ARM_LPC24XX
     }
 
     # For backward compatibility with LPC24XX platforms
-    cdl_option CYGNUM_IO_SERIAL_IRQ_PRIORITY_LEVELS {
+    cdl_option CYGNUM_IO_SERIAL_IRQ_PRIORITY_MIN {
         display       "Interrupt priority levels"
         flavor        data
-        calculated    { CYGNUM_HAL_IRQ_PRIORITY_LEVELS ? CYGNUM_HAL_IRQ_PRIORITY_LEVELS : 15 }
+        calculated    { CYGNUM_HAL_IRQ_PRIORITY_MIN ? CYGNUM_HAL_IRQ_PRIORITY_MIN : 15 }
         description   "
             For backward compatibility with LPC 24XX plarforms that
-            do not have CYGNUM_HAL_IRQ_PRIORITY_LEVELS defined."
+            do not have CYGNUM_HAL_IRQ_PRIORITY_MIN defined."
     }
 
     # Support up to 4 on-chip UART modules. The number may vary between
@@ -154,15 +154,11 @@ cdl_package CYGPKG_IO_SERIAL_ARM_LPC24XX
             cdl_option CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL[set ::channel]_INTPRIO {
                 display       "Interrupt priority of UART [set ::channel]"
                 flavor        data
-                legal_values  0 to CYGNUM_IO_SERIAL_IRQ_PRIORITY_LEVELS-1
-                default_value CYGNUM_IO_SERIAL_IRQ_PRIORITY_LEVELS-1
+                legal_values  0 to CYGNUM_IO_SERIAL_IRQ_PRIORITY_MIN
+                default_value CYGNUM_IO_SERIAL_IRQ_PRIORITY_MIN
                 description   "
                     This option selects the interupt priority for
-                    the UART [set ::channel] interrupts. There are
-                    CYGNUM_IO_SERIAL_IRQ_PRIORITY_LEVELS priority
-                    levels corresponding to the values 0 through
-                    CYGNUM_IO_SERIAL_IRQ_PRIORITY_LEVELS-1 decimal, of
-                    which the highest value is the lowest priority. The
+                    the UART [set ::channel] interrupts. The
                     reset value of these registers defaults all interrupt
                     to the lowest priority, allowing a single write to
                     elevate the priority of an individual interrupt."