# HG changeset patch
# User vae
# Date 1337366138 0
# Node ID 7c9ce2220671936f4d9cd863a262b333d5b58f05
# Parent  7e86d66e57e3b1f362a3a576b435124a5547fd28
Bug fix: Do not implement external memory interface if Platform startup is not selected. [ Bugzilla 1001590 ]

diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog b/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog
--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog
@@ -1,3 +1,9 @@
+2012-05-17  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl:
+	Bug fix: Do not implement external memory interface if Platform startup is
+	not selected. [ Bugzilla 1001590 ]
+
 2012-02-25  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl:
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl b/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl
--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl
@@ -56,9 +56,6 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T
     requires      { is_active(CYGPKG_DEVS_ETH_FREESCALE_ENET)
                   implies CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" }
 
-#    implements    CYGINT_HAL_CORTEXM4_CODE
-#    implements    CYGINT_HAL_CORTEXM_FPV4_SP_D16
-#    implements    CYGINT_HAL_CORTEXM_FPU_CODE
     implements    CYGINT_HAL_CACHE
 
     requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM == 70 }
@@ -66,7 +63,7 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T
     requires      { CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 }
 
     implements    CYGINT_IO_SERIAL_FREESCALE_UART2
-    implements    CYGINT_HAL_CORTEXM_KINETIS_DDRAM
+
     implements    CYGINT_HAL_FREESCALE_UART2
     implements    CYGINT_HAL_CORTEXM_KINETIS_RTC
     implements    CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1
@@ -138,15 +135,18 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T
     cdl_option CYGHWR_MEMORY_LAYOUT_PLF {
         display "Memory layout by platform"
         flavor data
+        active_if { CYG_HAL_STARTUP_PLF != "ByVariant" }
+        implements CYGINT_HAL_CORTEXM_KINETIS_DDRAM
         no_define
         parent  CYGHWR_MEMORY_LAYOUT
         calculated {
-            (CYG_HAL_STARTUP_PLF == "ByVariant" ) ? 0 :
+            (CYG_HAL_STARTUP_PLF == "ByVariant" ) ? "by variant" :
             (CYG_HAL_STARTUP == "RAM") ? "kinetis_"
             . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT  . "_extram_ram" :
             (CYG_HAL_STARTUP == "ROM") ? "kinetis_"
             . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT  . "_extram_rom" :
-            "undefined_by_PLF" }
+            "Error!"
+        }
         description "
             Combination of 'Startup type' and 'Kinetis member in use'
             produces the memory layout."