# HG changeset patch
# User vae
# Date 1337365935 0
# Node ID 7e86d66e57e3b1f362a3a576b435124a5547fd28
# Parent  7446751761c7149b0f51b90eb4ad7df8d8968eed
Bug fix: Do not refer external memory if Platform startup is not selected.  [ Bugzilla 1001590 ]

diff --git a/packages/hal/cortexm/kinetis/var/current/ChangeLog b/packages/hal/cortexm/kinetis/var/current/ChangeLog
--- a/packages/hal/cortexm/kinetis/var/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/var/current/ChangeLog
@@ -1,3 +1,9 @@
+2012-05-17  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis.cdl:
+	Bug fix: Do not refer external memory if Platform startup is
+	not selected.  [ Bugzilla 1001590 ]
+
 2012-05-04  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* cdl/hal_cortexm_kinetis.cdl:
diff --git a/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl b/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl
--- a/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl
+++ b/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl
@@ -100,8 +100,7 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS {
         cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FPU {
             display          "Floating Point Unit option"
             flavor           bool
-            implements       CYGINT_HAL_CORTEXM_FPV4_SP_D16
-            default_value    { CYGINT_HAL_CORTEXM_FPV4_SP_D16 }
+            default_value 0
             description "Select whether the chip has Floating Point Unit."
         }
 
@@ -505,11 +504,14 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS {
             active_if (CYGINT_HAL_CACHE)
 
             cdl_component CYGHWR_HAL_NON_CACHABLE {
-                display "Non cacheable memory regions"
+                display "Non cacheable RAM memory regions"
                 flavor data
-                active_if CYGINT_HAL_HAS_NONCACHEABLE
+                active_if  CYGINT_HAL_HAS_NONCACHEABLE
                 legal_values { "\".sram\"" "\".noncache\"" }
                 default_value { "\".noncache\"" }
+                description "
+                    Non cacheable memory sections may be used as shared memory
+                    between CPU and other bus masters such as DMA, ENET, etc."
 
                 cdl_option CYGHWR_HAL_ENET_TCD_SECTION {
                     display "Ethernet buffer descriptor memory section"