# HG changeset patch
# User sergeig
# Date 1302108856 0
# Node ID 9aec6a8ff9b92bcfff4852e47355e64494ec9ca8
# Parent  ca5a6d972d840ecb816ee592e387bb7272daaaac
* cdl/cortexm.cdl: Remove M1 CPU family from architecture config
  file (as not supported for now). [Bugzilla 1001186]
* cdl/cortexm.cdl: Add M4 CPU family to CYGHWR_HAL_CORTEXM. Add
  FPU (Floating Point Unit) interface.
* include/hal_io.h: Add CYGHWR_HAL_CORTEXM_M4 to some preprocessor
  conditions. [Bugzilla 1001186]

diff --git a/packages/hal/cortexm/arch/current/ChangeLog b/packages/hal/cortexm/arch/current/ChangeLog
--- a/packages/hal/cortexm/arch/current/ChangeLog
+++ b/packages/hal/cortexm/arch/current/ChangeLog
@@ -1,3 +1,14 @@
+2011-04-06  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/cortexm.cdl: Remove M1 CPU family from architecture config
+	file (as not supported for now). [Bugzilla 1001186]
+
+2011-04-02  Ilija Kocho  <ilijak@siva.com.mk>
+	* cdl/cortexm.cdl: Add M4 CPU family to CYGHWR_HAL_CORTEXM. Add
+	FPU (Floating Point Unit) interface.
+	* include/hal_io.h: Add CYGHWR_HAL_CORTEXM_M4 to some preprocessor
+	conditions. [Bugzilla 1001186]
+
 2011-04-01  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* include/hal_intr.h: Remove double inclusion of var_intr.h
diff --git a/packages/hal/cortexm/arch/current/cdl/hal_cortexm.cdl b/packages/hal/cortexm/arch/current/cdl/hal_cortexm.cdl
--- a/packages/hal/cortexm/arch/current/cdl/hal_cortexm.cdl
+++ b/packages/hal/cortexm/arch/current/cdl/hal_cortexm.cdl
@@ -98,14 +98,14 @@ cdl_package CYGPKG_HAL_CORTEXM {
     cdl_option CYGHWR_HAL_CORTEXM {
         display          "Cortex-M CPU family"
         flavor           data
-        legal_values     { "M1" "M3" }
+        legal_values     { "M3" "M4" }
         default_value    { "M3" }
         description      "
-            The Cortex-M architecture has two variants at present. The M1 is
-            base on the ARMV6 architecture specification and executes an extended
-            variant of the Thumb instruction set and has some differences in
-            the interrupt controller. The M3 is based on the ARMV7 architecture
-            specification and executes the Thumb2 instruction set."
+            The Cortex-M architecture has two variants at present. The
+            M3 and M4 are based on the ARMV7 architecture specification
+            and execute the Thumb2 instruction set. The M4 in addition
+            to M3 instruction set has SIMD and optional single precision
+            floating point instructions."
     }
 
     cdl_option CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE {
@@ -117,6 +117,18 @@ cdl_package CYGPKG_HAL_CORTEXM {
              Select the Cortex-M system tick timer clock source."
     }
 
+    cdl_interface CYGINT_HAL_CORTEXM_FPU {
+        display "The platform and architecture contains floating point unit."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_FPU {
+        display          "Floating Point Unit"
+        active_if        { CYGINT_HAL_CORTEXM_FPU != 0 }
+        default_value    CYGINT_HAL_CORTEXM_FPU
+        description      "
+            Use the Floating Point Unit."
+    }
+
     cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_MAX {
          display         "Maximum usable priority"
          flavor          data
diff --git a/packages/hal/cortexm/arch/current/include/hal_io.h b/packages/hal/cortexm/arch/current/include/hal_io.h
--- a/packages/hal/cortexm/arch/current/include/hal_io.h
+++ b/packages/hal/cortexm/arch/current/include/hal_io.h
@@ -92,7 +92,7 @@
 
 #define CYGARC_REG_NVIC_BASE                    0xE000E000
 
-#if defined(CYGHWR_HAL_CORTEXM_M3)
+#if defined(CYGHWR_HAL_CORTEXM_M3) || defined(CYGHWR_HAL_CORTEXM_M4)
 #define CYGARC_REG_NVIC_TYPE                    0x004
 #endif
 
@@ -117,7 +117,7 @@
 #define CYGARC_REG_NVIC_PR(__intr)              (CYGARC_REG_NVIC_PR0+(__intr))
 
 
-#if defined(CYGHWR_HAL_CORTEXM_M3)
+#if defined(CYGHWR_HAL_CORTEXM_M3) || defined(CYGHWR_HAL_CORTEXM_M4)
 
 #define CYGARC_REG_NVIC_CPUID                   0xD00
 #define CYGARC_REG_NVIC_ICSR                    0xD04
@@ -220,7 +220,7 @@
 //==========================================================================
 // Debug registers
 
-#if defined(CYGHWR_HAL_CORTEXM_M3)
+#if defined(CYGHWR_HAL_CORTEXM_M3) || defined(CYGHWR_HAL_CORTEXM_M4)
 
 #define CYGARC_REG_DEBUG_BASE                   0xE000EDF0
 
diff --git a/packages/hal/cortexm/arch/current/src/hal_misc.c b/packages/hal/cortexm/arch/current/src/hal_misc.c
--- a/packages/hal/cortexm/arch/current/src/hal_misc.c
+++ b/packages/hal/cortexm/arch/current/src/hal_misc.c
@@ -163,11 +163,10 @@ void hal_reset_vsr( void )
     // Ensure that the CPU will use the vector table we have just set
     // up.
 
-# if defined(CYGHWR_HAL_CORTEXM_M3)
+# if defined(CYGHWR_HAL_CORTEXM_M3) || defined(CYGHWR_HAL_CORTEXM_M4)
 
-    // On M3 parts, the NVIC contains a vector table base register. We
-    // program this to relocate the vector table base to the base of
-    // SRAM.
+    // On M3 and M4 parts, the NVIC contains a vector table base register.
+    // We program this to relocate the vector table base to the base of SRAM.
     
     HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_VTOR,
                       CYGARC_REG_NVIC_VTOR_TBLOFF(0)|