# HG changeset patch
# User jlarmour
# Date 1334339775 0
# Node ID 9cff5928a4e2380633b68c5574c32ca4e0cff7db
# Parent  0161bba6d2a7d42c9fd66586e041939c588b10ea
* src/usb_stm32.c (cyg_usbs_cortexm_stm32_init):
Peripheral clocks are enable / disable using new
CYGHWR_HAL_STM32_CLOCK_DISABLE / CYGHWR_HAL_STM32_CLOCK_ENABLE
macro supplied from the variant HAL

diff --git a/packages/devs/usb/cortexm/stm32/current/ChangeLog b/packages/devs/usb/cortexm/stm32/current/ChangeLog
--- a/packages/devs/usb/cortexm/stm32/current/ChangeLog
+++ b/packages/devs/usb/cortexm/stm32/current/ChangeLog
@@ -1,3 +1,10 @@
+2012-04-13  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* src/usb_stm32.c (cyg_usbs_cortexm_stm32_init):
+	Peripheral clocks are enable / disable using new 
+	CYGHWR_HAL_STM32_CLOCK_DISABLE / CYGHWR_HAL_STM32_CLOCK_ENABLE
+	macro supplied from the variant HAL
+
 2012-04-03  Jonathan Larmour  <jifl@eCosCentric.com>
 
 	* src/usb_stm32.c (cyg_usbs_cortexm_stm32_init):
diff --git a/packages/devs/usb/cortexm/stm32/current/src/usb_stm32.c b/packages/devs/usb/cortexm/stm32/current/src/usb_stm32.c
--- a/packages/devs/usb/cortexm/stm32/current/src/usb_stm32.c
+++ b/packages/devs/usb/cortexm/stm32/current/src/usb_stm32.c
@@ -2229,10 +2229,8 @@ static void CYGBLD_ATTRIB_C_INIT_PRI(CYG
   // Make sure that the CAN controller is disabled and held in reset.
   // TODO: If a CAN driver is to be added to the standard distribution, this
   // should check for USB/CAN configuration clashes.
-  HAL_READ_UINT32 (CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_APB1ENR, reg_data);
-  reg_data &= ~((cyg_uint32) CYGHWR_HAL_STM32_RCC_APB1ENR_CAN1);
-  HAL_WRITE_UINT32 (CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_APB1ENR, reg_data);
-  
+  CYGHWR_HAL_STM32_CLOCK_DISABLE( CYGHWR_HAL_STM32_CAN1_CLOCK );
+
   // Configure the IO pins for USB operation.
   CYGHWR_HAL_STM32_GPIO_SET (USB_DISC_PIN);
   CYGHWR_HAL_STM32_GPIO_SET (USB_DP_PIN);
@@ -2244,10 +2242,8 @@ static void CYGBLD_ATTRIB_C_INIT_PRI(CYG
 #endif
 
   // Ensure that the USB clock is disabled prior to setting prescaler. 
-  HAL_READ_UINT32 (CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_APB1ENR, reg_data);
-  reg_data &= ~((cyg_uint32) CYGHWR_HAL_STM32_RCC_APB1ENR_USB);
-  HAL_WRITE_UINT32 (CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_APB1ENR, reg_data);
-  
+  CYGHWR_HAL_STM32_CLOCK_DISABLE( CYGHWR_HAL_STM32_USB_CLOCK );
+
   // Set up the USB 48MHz serial clock.  There are only 2 valid prescaler
   // settings which correspond to 72MHz and 48MHz PLL clock outputs.
   HAL_READ_UINT32 (CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_CFGR, reg_data);
@@ -2261,9 +2257,7 @@ static void CYGBLD_ATTRIB_C_INIT_PRI(CYG
   HAL_WRITE_UINT32 (CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_CFGR, reg_data);
 
   // Activate the USB clock after setting prescaler. 
-  HAL_READ_UINT32 (CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_APB1ENR, reg_data);
-  reg_data |= CYGHWR_HAL_STM32_RCC_APB1ENR_USB;
-  HAL_WRITE_UINT32 (CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_APB1ENR, reg_data);
+  CYGHWR_HAL_STM32_CLOCK_ENABLE( CYGHWR_HAL_STM32_USB_CLOCK );
 
   // Take USB transceiver out of powerdown state, but leave it in reset until we
   // are ready to start.  Leave interrupts disabled at source.