# HG changeset patch # User vae # Date 1337376706 0 # Node ID a56d5166ddf6b4928fee64f580816b2cf4b830f3 # Parent 58eda6fed5a511bb7eda7892da1bce3dc6181e2d New file -- Kinetis variant documentation. [Bug 1001580] diff --git a/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog b/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog --- a/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog +++ b/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog @@ -1,3 +1,8 @@ +2012-05-18 Ilija Kocho + + * doc/twr_k40x512.sgml: + New file -- TWR-K40X512 platform documentation. [Bug 1001580] + 2012-01-06 Ilija Kocho * cdl/hal_cortexm_kinetis_twr_k40x256.cdl: diff --git a/packages/hal/cortexm/kinetis/twr_k40x256/current/doc/twr_k40x256.sgml b/packages/hal/cortexm/kinetis/twr_k40x256/current/doc/twr_k40x256.sgml new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/twr_k40x256/current/doc/twr_k40x256.sgml @@ -0,0 +1,75 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + TWR-K40X256-KIT Development kit + + + CYGPKG_HAL_CORTEXM_KINETIS_TWR_K40X256 + eCos Support for the Freescale TWR-K40X256 development kit + + + Description + + The Freescale TWR-K40X256-KIT is a development kit for + Freescale Kinetis Cortex-M4 based micro-controllers. It covers K40 and K30 microcontroller + subfamilies. K40X256 is a high end member comprising 256 KiB FLASH, 256 KiB FlexMemory and 64 KiB SRAM, + as well as rich set of communication interfaces including USB, UARTs CAN, SPI and I2C. + K40 controllers also feature a Segment LCD controller, a DMA controller and a FlexBus + external memory interface. They are mixed signal devices featuring 16 bit ADC and 12 bit DAC. + + + Configuration + Hardware Setup + + No changes to the factory default setup are necessary. + + Clocking + + The TWR-K40X256 uses an 8MHz crystal as a clock reference which is stated as a requirement in the platform package. + + + Memory + K40X245 has two 32KiB SRAM banks giving a total of 64KiB on chip SRAM. + + + + + + diff --git a/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog b/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog --- a/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog +++ b/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog @@ -1,3 +1,8 @@ +2012-05-18 Ilija Kocho + + * doc/twr_k60n512.sgml: + New file -- TWR-K60N512 platform documentation. [Bug 1001580] + 2012-01-06 Ilija Kocho * cdl/hal_cortexm_kinetis_twr_k60n512.cdl: diff --git a/packages/hal/cortexm/kinetis/twr_k60n512/current/doc/twr_k60n512.sgml b/packages/hal/cortexm/kinetis/twr_k60n512/current/doc/twr_k60n512.sgml new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/twr_k60n512/current/doc/twr_k60n512.sgml @@ -0,0 +1,134 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + TWR-K60N512-KIT Development kit + + + CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60N512 + eCos Support for the Freescale TWR-K60N512 development kit + + + Description + + The Freescale TWR-K60N512-KIT is a development kit for + Freescale Kinetis Cortex-M4 based microcontrollers. + It covers K60, K10 and K20 microcontroller families. + K60N512 is a high end member comprising 512 KiB FLASH and 128 KiB SRAM, + as well as rich set of communication interfaces inclduing Ethernet USB, UARTs CAN, SPI and I2C. + K60 micro-controllres also have a DMA controller and a FlexBus external memory interface. + They are mixed signal devices featuring a 16 bit ADC and a 12 bit DAC. + + + + Configuration + Hardware Setup + + Factory jumper settings on the TWR-K60N512 are fitted for standalone operation of the TWR-K60N512. + In order to use it with the Ethernet PHY on TWR-SER, some jumpers have to be changed from their factory + settings on both TWR-K60N512 and TWR-SER: + + TWR-K60N512 Jumper setting differences from factory settings + + + + + + + Jumper + Setting + Description + + + + + J6 + 2-3 + Select TWR-SER oscillator as clock source. + + + +
+ + TWR-SER Jumper settings differences from factory settings + + + + + + + Jumper + Setting + Description + + + + + J2 + 3-4 + Ethernet PHY clock select: 50MHz + + + J3 + 2-3 + Route 50MHz to CLOCKIN0 + + + J12 + 9-10 + Ethernet PHY config: select RMII mode + + + +
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+ eCos Configuration + Clocking + + TWR-K60N512 uses default Kinetis variant clocking. + + + Memory + K60 has two 64KiB SRAM banks giving a total of 128KiB on chip SRAM. + + +
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