# HG changeset patch # User asl # Date 1173121772 0 # Node ID a874158b6a4e33fadf98613655594a9e90d16325 # Parent edb7cc3a99680faf7b85dad1e0aaf540009c545e * Added hal_plf_eth_init() in order to initialise the Davicom 9161A PHY properly on the Evaluation board diff --git a/packages/hal/arm/at91/at91sam7xek/current/ChangeLog b/packages/hal/arm/at91/at91sam7xek/current/ChangeLog --- a/packages/hal/arm/at91/at91sam7xek/current/ChangeLog +++ b/packages/hal/arm/at91/at91sam7xek/current/ChangeLog @@ -1,3 +1,8 @@ +2007-01-17 John Eigelaar + + * Added hal_plf_eth_init() in order to initialise the Davicom + 9161A PHY properly on the Evaluation board + 2007-01-02 Uwe Kindler * cdl/hal_arm_at91sam7s.cdl Moved HAL_PLATFORM_XXX defines and diff --git a/packages/hal/arm/at91/at91sam7xek/current/cdl/hal_arm_at91sam7xek.cdl b/packages/hal/arm/at91/at91sam7xek/current/cdl/hal_arm_at91sam7xek.cdl --- a/packages/hal/arm/at91/at91sam7xek/current/cdl/hal_arm_at91sam7xek.cdl +++ b/packages/hal/arm/at91/at91sam7xek/current/cdl/hal_arm_at91sam7xek.cdl @@ -58,7 +58,10 @@ cdl_package CYGPKG_HAL_ARM_AT91SAM7XEK { requires { CYGHWR_HAL_ARM_AT91 == "AT91SAM7S" } requires { CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7x256" || CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7x128" } - + + requires { is_active(CYGPKG_DEVS_ETH_PHY) implies + (1 == CYGHWR_DEVS_ETH_PHY_DM9161A) } + define_proc { puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H " puts $::cdl_header "/***** proc output start *****/" diff --git a/packages/hal/arm/at91/at91sam7xek/current/src/at91sam7xek_misc.c b/packages/hal/arm/at91/at91sam7xek/current/src/at91sam7xek_misc.c --- a/packages/hal/arm/at91/at91sam7xek/current/src/at91sam7xek_misc.c +++ b/packages/hal/arm/at91/at91sam7xek/current/src/at91sam7xek_misc.c @@ -73,5 +73,41 @@ hal_at91_led (int val) HAL_ARM_AT91_GPIO_PUT(AT91_GPIO_PB22, !(val & 8)); } +void hal_plf_eth_init(void) +{ + cyg_uint32 stat; + + /* Enable the PIOB Clock */ + HAL_WRITE_UINT32(AT91_PMC + AT91_PMC_PCER, AT91_PMC_PCER_PIOB); + + /* RXDV / Testmode select */ + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PB15, AT91_PIN_IN); + HAL_ARM_AT91_GPIO_CFG_PULLUP(AT91_GPIO_PB15, AT91_PIN_PULLUP_DISABLE); + + //TODO: The errata reports that the RMII mode for the SAM7X does not work. + // It would probably still be a good idea to use the RMII/MII CDL + // configuration to select the appropriate mode here + /* COL / !MII select */ + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PB16, AT91_PIN_IN); + HAL_ARM_AT91_GPIO_CFG_PULLUP(AT91_GPIO_PB16, AT91_PIN_PULLUP_DISABLE); + + /* TXCLK / ISOLATE */ + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PB0, AT91_PIN_IN); + HAL_ARM_AT91_GPIO_CFG_PULLUP(AT91_GPIO_PB0, AT91_PIN_PULLUP_DISABLE); + + /* Power Down Mode */ + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PB18, AT91_PIN_OUT); + HAL_ARM_AT91_GPIO_PUT(AT91_GPIO_PB19,0); + + /* All the lines setup correctly. Now do a external reset and let the phy + start up in the correct mode */ + HAL_WRITE_UINT32(AT91_RST+AT91_RST_RMR,AT91_RST_RMR_KEY|(1<<0x8)); + HAL_WRITE_UINT32(AT91_RST+AT91_RST_RCR,AT91_RST_RCR_KEY|AT91_RST_RCR_EXTRST); + + do { + HAL_READ_UINT32(AT91_RST+AT91_RST_RSR,stat); + } while (!(stat&AT91_RST_RSR_NRST_SET)); +} + //-------------------------------------------------------------------------- // EOF at91sam7sek_misc.c