# HG changeset patch
# User vae
# Date 1362849754 0
# Node ID ba0e09bf66605b9f3d467e44005387417650a319
# Parent  ea9c78f2cd619d74001e8202018128452a646709
Sync with variant changes due to hardware floating point support. Changed CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM.    [Bugzilla 1001607]

diff --git a/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog b/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog
--- a/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog
@@ -1,3 +1,9 @@
+2012-11-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_kwikstik.cdl:
+	Sync with variant changes due to hardware floating point support.
+	Changed CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM.    [Bugzilla 1001607]
+
 2011-12-15  Tomas Frydrych  <tomas@sleepfive.com>
 
 	* cdl/hal_cortexm_kinetis_kwikstik.cdl:
diff --git a/packages/hal/cortexm/kinetis/kwikstik/current/cdl/hal_cortexm_kinetis_kwikstik.cdl b/packages/hal/cortexm/kinetis/kwikstik/current/cdl/hal_cortexm_kinetis_kwikstik.cdl
--- a/packages/hal/cortexm/kinetis/kwikstik/current/cdl/hal_cortexm_kinetis_kwikstik.cdl
+++ b/packages/hal/cortexm/kinetis/kwikstik/current/cdl/hal_cortexm_kinetis_kwikstik.cdl
@@ -59,12 +59,14 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_K
         (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 16) }
 
     requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM == 40 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FPU == "D" }
     requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
     requires      { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" ||
                     CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC" }
-    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == 1 }
-    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME == 256 }
-    requires      { CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 4096 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_DEFAULT == "X" }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT == 256 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X"
+                    implies CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 4096 }
 
     implements    CYGINT_IO_SERIAL_FREESCALE_UART5
     implements    CYGINT_HAL_FREESCALE_UART5
diff --git a/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog b/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog
--- a/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog
@@ -1,3 +1,9 @@
+2012-11-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k40x256.cdl:
+	Sync with variant changes due to hardware floating point support.
+	Changed CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM.    [Bugzilla 1001607]
+
 2012-10-25  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* src/twr_k40x256_misc.c: Initialization for separate SRAM regions
diff --git a/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl b/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl
--- a/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl
+++ b/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl
@@ -58,12 +58,14 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T
         (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 16) }
 
     requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM == 40 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FPU == "D" }
     requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
     requires      { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" ||
                     CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC" }
-    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == 1 }
-    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME == 256 }
-    requires      { CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 4096 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_DEFAULT == "X" }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT == 256 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X"
+                    implies CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 4096 }
 
     implements    CYGINT_IO_SERIAL_FREESCALE_UART3
     implements    CYGINT_HAL_FREESCALE_UART3