# HG changeset patch
# User jlarmour
# Date 1157631254 0
# Node ID d2e08e32ef0440b56ef07642256b13fce688cdfb
# Parent  e29a68373ae99c1ab72e02a1cbf7a0482a79c73f
        * src/spi_at91.c: Fixed the chip select functions.
        Changed the Mode Register setup as to disable the Mode Failure
        Detaction for variants that support it. The Mode Failure Detection
        breaks because NPCS0 is not connected, we are using GPIO, and is
        thus floating.

diff --git a/packages/devs/spi/arm/at91/current/ChangeLog b/packages/devs/spi/arm/at91/current/ChangeLog
--- a/packages/devs/spi/arm/at91/current/ChangeLog
+++ b/packages/devs/spi/arm/at91/current/ChangeLog
@@ -1,3 +1,11 @@
+2006-09-07  John Eigelaar <jeigelaar@mweb.co.za>
+
+	* src/spi_at91.c: Fixed the chip select functions.
+	Changed the Mode Register setup as to disable the Mode Failure
+	Detaction for variants that support it. The Mode Failure Detection
+	breaks because NPCS0 is not connected, we are using GPIO, and is 
+	thus floating. 
+
 2006-06-01  John Eigelaar <jeigelaar@mweb.co.za>
 
 	* src/spi_at91.c:
diff --git a/packages/devs/spi/arm/at91/current/src/spi_at91.c b/packages/devs/spi/arm/at91/current/src/spi_at91.c
--- a/packages/devs/spi/arm/at91/current/src/spi_at91.c
+++ b/packages/devs/spi/arm/at91/current/src/spi_at91.c
@@ -365,7 +365,7 @@ spi_at91_start_transfer(cyg_spi_at91_dev
 #ifdef CYGHWR_DEVS_SPI_ARM_AT91_PCSDEC
     spi_at91_set_npcs(spi_bus,~dev->dev_num);
 #else
-    spi_at91_set_npcs(spi_bus,1<<dev->dev_num);
+    spi_at91_set_npcs(spi_bus,~(1<<dev->dev_num));
 #endif
     CYGACC_CALL_IF_DELAY_US(dev->cs_up_udly);
    
@@ -539,12 +539,25 @@ spi_at91_transaction_begin(cyg_spi_devic
     // Enable the SPI controller
     HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_CR, AT91_SPI_CR_SPIEN);
     
+    /* As we are using this driver only in master mode with NPCS0 
+       configured as GPIO instead of a peripheral pin, it is neccessary 
+       for the Mode Failure detection to be switched off as this will
+       cause havoc with the driver */ 
+
     // Put SPI bus into master mode
     if (1 == at91_spi_dev->cl_div32)
         HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_MR, AT91_SPI_MR_MSTR | 
-                                               AT91_SPI_MR_DIV32);
+                                               AT91_SPI_MR_DIV32
+#ifdef AT91_SPI_MR_MODFDIS
+                                               | AT91_SPI_MR_MODFDIS
+#endif
+                                               );
     else
-        HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_MR, AT91_SPI_MR_MSTR);
+        HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_MR, AT91_SPI_MR_MSTR 
+#ifdef AT91_SPI_MR_MODFDIS
+                                                    | AT91_SPI_MR_MODFDIS
+#endif
+                                                    );
 }
 
 static void