# HG changeset patch
# User vae
# Date 1352036911 0
# Node ID ea482849d62076b56c3dfca0af00e93917860791
# Parent  12716d36ed7d1e904c5cd6de56a80de588fd78f6
Define register access to FTFL module. Contributed by Nicolas Aujoux at 2012-09-07 [Bugzilla 1001561]

diff --git a/packages/hal/cortexm/kinetis/var/current/ChangeLog b/packages/hal/cortexm/kinetis/var/current/ChangeLog
--- a/packages/hal/cortexm/kinetis/var/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/var/current/ChangeLog
@@ -1,3 +1,8 @@
+2012-11-04  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/var_io.h: Define register access to FTFL module. 
+	Contributed by Nicolas Aujoux at 2012-09-07 [Bugzilla 1001561]
+
 2012-09-28  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* var/current/cdl/hal_cortexm_kinetis.cdl
@@ -7,7 +12,7 @@ 2012-09-28  Ilija Kocho  <ilijak@siva.co
 	* var/current/include/var_io_ddrmc.h
 	* var/current/include/var_io_lmem.h
 	* var/current/src/kinetis_ddram.c
-	* var/current/src/kinetis_misc.c
+	* var/current/src/kinetis_misc.c:
 	Separate data and code caches, as well as text indentation suggested by Jifl.
 	Fixes to cache and SDRAM CDL and functions Improved SDRAM controller
 	support due to better manufacturer documentation: Configurable pad control.
diff --git a/packages/hal/cortexm/kinetis/var/current/include/var_io.h b/packages/hal/cortexm/kinetis/var/current/include/var_io.h
--- a/packages/hal/cortexm/kinetis/var/current/include/var_io.h
+++ b/packages/hal/cortexm/kinetis/var/current/include/var_io.h
@@ -100,6 +100,43 @@ typedef struct cyghwr_hal_kinetis_flash_
 //===========================================================================
 // Kinetis Peripherals
 //---------------------------------------------------------------------------
+// Internal Flash
+
+typedef volatile struct cyghwr_hal_kinetis_flash_s {
+    cyg_uint8 fstat;    // Flash status register
+    cyg_uint8 fcnfg;    // Flash configuration register
+    cyg_uint8 fsec;     // Flash security register
+    cyg_uint8 fopt;     // Flash option register
+    cyg_uint8 fccob3;   // Flash common command object registers
+    cyg_uint8 fccob2;
+    cyg_uint8 fccob1;
+    cyg_uint8 fccob0;
+    cyg_uint8 fccob7;
+    cyg_uint8 fccob6;
+    cyg_uint8 fccob5;
+    cyg_uint8 fccob4;
+    cyg_uint8 fccobB;
+    cyg_uint8 fccobA;
+    cyg_uint8 fccob9;
+    cyg_uint8 fccob8;
+    cyg_uint8 fprot3;   // Program flash protection registers
+    cyg_uint8 fprot2;
+    cyg_uint8 fprot1;
+    cyg_uint8 fprot0;
+    cyg_uint8 reserved[2];
+    cyg_uint8 feprot;   // EEPROM Protection register
+    cyg_uint8 fdprot;   // Data flash protection register
+} cyghwr_hal_kinetis_flash_t;
+
+#define CYGHWR_HAL_KINETIS_FLASH_P ((cyghwr_hal_kinetis_flash_t *) 0x40020000)
+
+#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_CCIF_M           0x80
+#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_RDCOLERR_M       0x40
+#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_ACCERR_M         0x20
+#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_FPVIOL_M         0x10
+#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_MGSTAT0_M        0x01
+
+//---------------------------------------------------------------------------
 // Oscillator
 
 #define CYGHWR_HAL_KINETIS_OSC_CR          (0x40065000)
@@ -1269,7 +1306,7 @@ enum{
 #define CYGHWR_HAL_KINETIS_FMC_PFBCR_BDPE  (0x04)
 #define CYGHWR_HAL_KINETIS_FMC_PFBCR_BIPE  (0x02)
 #define CYGHWR_HAL_KINETIS_FMC_PFBCR_BSEBE (0x01)
-
+                                       
 //---------------------------------------------------------------------------
 // MPU Memory Protection unit