# HG changeset patch # User jld # Date 1295339744 0 # Node ID f04f37d9c26961d48bf5a95de99021a4da5e1876 # Parent b5c2e2c6f34a6088f378220405daf406645e7313 * src/stm32_misc.c: Implement a profiling timer on TIM2. * cdl/hal_cortexm_stm32.cdl: Add CDL option to enable the profiling timer. diff --git a/packages/hal/cortexm/stm32/var/current/ChangeLog b/packages/hal/cortexm/stm32/var/current/ChangeLog --- a/packages/hal/cortexm/stm32/var/current/ChangeLog +++ b/packages/hal/cortexm/stm32/var/current/ChangeLog @@ -1,3 +1,9 @@ +2011-01-13 John Dallaway + + * src/stm32_misc.c: Implement a profiling timer on TIM2. + * cdl/hal_cortexm_stm32.cdl: Add CDL option to enable the profiling + timer. + 2011-01-13 Nick Garnett * src/stm32_misc.c (hal_start_clocks): Correct bit clear operation @@ -108,7 +114,7 @@ 2008-10-06 Nick Garnett // HAL header #include // HAL header +#ifdef CYGFUN_HAL_CORTEXM_STM32_PROFILE_TIMER +#include // CYG_ISR_HANDLED +#include // __profile_hit() +#endif + //========================================================================== // Clock Initialization values @@ -387,4 +393,47 @@ cyg_uint32 hal_stm32_timer_clock( CYG_AD } //========================================================================== +// Profiling timer +// +// Implementation of profiling support using general-purpose timer TIM2. + +#ifdef CYGFUN_HAL_CORTEXM_STM32_PROFILE_TIMER +// Use TIM2 for profiling +#define STM32_TIMER_PROFILE CYGHWR_HAL_STM32_TIM2 +#define HAL_INTERRUPT_PROFILE CYGNUM_HAL_INTERRUPT_TIM2 + +// Profiling timer ISR +static cyg_uint32 profile_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + extern HAL_SavedRegisters *hal_saved_interrupt_state; + + HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_SR, 0); // clear interrupt pending flag + HAL_INTERRUPT_ACKNOWLEDGE(HAL_INTERRUPT_PROFILE); + __profile_hit(hal_saved_interrupt_state->u.interrupt.pc); + return CYG_ISR_HANDLED; +} + +// Profiling timer setup +int hal_enable_profile_timer(int resolution) +{ + CYG_ASSERT(resolution < 0x10000, "Invalid profile timer resolution"); // 16 bits only + + // Attach ISR + HAL_INTERRUPT_ATTACH(HAL_INTERRUPT_PROFILE, &profile_isr, 0x1111, 0); + HAL_INTERRUPT_UNMASK(HAL_INTERRUPT_PROFILE); + + // Setup timer + HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_PSC, + (hal_stm32_timer_clock(STM32_TIMER_PROFILE) / 1000000) - 1); // prescale to microseconds + HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_CR2, 0); + HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_DIER, CYGHWR_HAL_STM32_TIM_DIER_UIE); + HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_ARR, resolution); + HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_CR1, CYGHWR_HAL_STM32_TIM_CR1_CEN); + + return resolution; +} + +#endif // CYGFUN_HAL_CORTEXM_STM32_PROFILE_TIMER + +//========================================================================== // EOF stm32_misc.c