# HG changeset patch
# User jld
# Date 1304578297 0
# Node ID fac7912b644953796d1dc6e52f8f2378f822e388
# Parent  32c8a1b0fef908032632dfa25c000b5b97e81491
* cdl/adc_stm32.cdl, src/adc_stm32.c: Make sure DMA clock is enabled. Fix
  ADC clock divider not set in stm32_adc_init_clock. [ Bugzilla 1001215 ]

diff --git a/packages/devs/adc/cortexm/stm32/current/ChangeLog b/packages/devs/adc/cortexm/stm32/current/ChangeLog
--- a/packages/devs/adc/cortexm/stm32/current/ChangeLog
+++ b/packages/devs/adc/cortexm/stm32/current/ChangeLog
@@ -1,3 +1,10 @@
+2011-05-02  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* cdl/adc_stm32.cdl:
+	* src/adc_stm32.c:
+	Make sure DMA clock is enabled. Fix ADC clock divider not set in
+	stm32_adc_init_clock.
+
 2009-03-05  Simon Kallweit  <simon.kallweit@intefo.ch>
 
 	* src/adc_stm32.c:
@@ -15,7 +22,7 @@ 2009-02-24  Simon Kallweit  <simon.kallw
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2009 Free Software Foundation, Inc.                        
+// Copyright (C) 2009, 2011 Free Software Foundation, Inc.                  
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/devs/adc/cortexm/stm32/current/cdl/adc_stm32.cdl b/packages/devs/adc/cortexm/stm32/current/cdl/adc_stm32.cdl
--- a/packages/devs/adc/cortexm/stm32/current/cdl/adc_stm32.cdl
+++ b/packages/devs/adc/cortexm/stm32/current/cdl/adc_stm32.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 2009 Free Software Foundation, Inc.                        
+## Copyright (C) 2009, 2011 Free Software Foundation, Inc                   
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -63,18 +63,23 @@ cdl_package CYGPKG_DEVS_ADC_CORTEXM_STM3
            
     include_dir cyg/io
     compile     -library=libextras.a adc_stm32.c
-    
+
+    cdl_option CYGPKG_DEVS_ADC_CORTEXM_STM32_TRACE {
+        display       "ADC driver tracing"
+        flavor        bool
+        default_value 0
+        description   "
+            Enable tracing of the ADC driver. Select to debug the driver."
+    }
+
     cdl_option CYGNUM_DEVS_ADC_CORTEXM_STM32_CLOCK_DIV {
          display        "ADC clock divider"
          flavor         data
          legal_values   { 2 4 6 8 }
          default_value  8
          description    "
-             This option specifies the level of debug data output by
-             the STM32 ADC device driver. A value of 0 signifies
-             no debug data output; 1 signifies normal debug data
-             output. If an overrun occurred then this can only be
-             detected by debug output messages."         
+             This option specifies the ADC clock divider value. The 
+             ADC clock frequency is defined as PCLK2 / ADC divider. "
     }
     
     cdl_component CYGHWR_DEVS_ADC_CORTEXM_STM32_ADC1 {
diff --git a/packages/devs/adc/cortexm/stm32/current/src/adc_stm32.c b/packages/devs/adc/cortexm/stm32/current/src/adc_stm32.c
--- a/packages/devs/adc/cortexm/stm32/current/src/adc_stm32.c
+++ b/packages/devs/adc/cortexm/stm32/current/src/adc_stm32.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2009 Free Software Foundation, Inc.                        
+// Copyright (C) 2009, 2011 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -64,11 +64,11 @@
 // Diagnostic support
 // Switch the #if to 1 to generate some diagnostic messages.
 
-#if 0
-#include <cyg/infra/diag.h>
-#define adc_diag( __fmt, ... ) diag_printf("ADC: %30s[%4d]: " __fmt, __FUNCTION__, __LINE__, ## __VA_ARGS__ );
+#ifdef CYGPKG_DEVS_ADC_CORTEXM_STM32_TRACE
+# include <cyg/infra/diag.h>
+# define adc_diag( __fmt, ... ) diag_printf("ADC: %30s[%4d]: " __fmt, __FUNCTION__, __LINE__, ## __VA_ARGS__ );
 #else
-#define adc_diag( __fmt, ... ) 
+# define adc_diag( __fmt, ... ) 
 #endif
 
 
@@ -432,7 +432,7 @@ stm32_adc_init_clock(void)
     adc_clock = hal_stm32_pclk2 / 8;
 #endif
 
-    HAL_READ_UINT32(rcc + CYGHWR_HAL_STM32_RCC_CFGR, cfgr);
+    HAL_WRITE_UINT32(rcc + CYGHWR_HAL_STM32_RCC_CFGR, cfgr);
 }
 
 //-----------------------------------------------------------------------------
@@ -446,6 +446,8 @@ stm32_adc_init_device(cyg_adc_device *de
     cyg_uint64 tmp;
     cyg_uint32 cycles;
     cyg_uint32 smpr;
+    cyg_uint32 rcc_base = CYGHWR_HAL_STM32_RCC;
+    cyg_uint32 reg_data;
     int i;
     
     static const cyg_uint32 cycles_table[] = 
@@ -470,7 +472,7 @@ stm32_adc_init_device(cyg_adc_device *de
     } while (cr & CYGHWR_HAL_STM32_ADC_CR2_CAL);
     
     // Power off ADC 
-    cr &= CYGHWR_HAL_STM32_ADC_CR2_ADON;
+    cr &= ~CYGHWR_HAL_STM32_ADC_CR2_ADON;
     HAL_WRITE_UINT32(info->setup->adc_base + CYGHWR_HAL_STM32_ADC_CR2, cr);
     
     // Enable external triggering and DMA
@@ -494,6 +496,14 @@ stm32_adc_init_device(cyg_adc_device *de
     
 
     // Setup DMA channel
+    // Ensure that the DMA clocks are enabled.
+    HAL_READ_UINT32 (rcc_base + CYGHWR_HAL_STM32_RCC_AHBENR, reg_data);
+    if (info->setup->dma_base == CYGHWR_HAL_STM32_DMA1)
+      reg_data |= CYGHWR_HAL_STM32_RCC_AHBENR_DMA1;
+    else
+      reg_data |= CYGHWR_HAL_STM32_RCC_AHBENR_DMA2;
+    HAL_WRITE_UINT32 (rcc_base + CYGHWR_HAL_STM32_RCC_AHBENR, reg_data);
+
     HAL_WRITE_UINT32(info->setup->dma_base + 
                      CYGHWR_HAL_STM32_DMA_CPAR(info->setup->dma_channel),
                      info->setup->adc_base + CYGHWR_HAL_STM32_ADC_DR);
@@ -557,7 +567,7 @@ stm32_adc_update_sequence(cyg_adc_device
     cyg_uint32 sqr2 = 0;
     cyg_uint32 sqr3 = 0;
     
-    adc_diag("Updateing regular group\n");
+    adc_diag("Updating regular group\n");
     
     // Disable ADC
     HAL_READ_UINT32(info->setup->adc_base + CYGHWR_HAL_STM32_ADC_CR2, cr);