# HG changeset patch
# User jlarmour
# Date 962741841 0
# Node ID ff3f181b64bd1f3393d19e0894da510187c07252
# Parent  7f461c3a372cc8316c5270f367108684f0aedacd
Merge from eCos master repository on 2000-07-04-20:42:44-BST

diff --git a/host/libcdl/ChangeLog b/host/libcdl/ChangeLog
--- a/host/libcdl/ChangeLog
+++ b/host/libcdl/ChangeLog
@@ -1,3 +1,16 @@
+2000-07-04  Bart Veer  <bartv@redhat.com>
+
+	* value.cxx (save):
+	The comment "# This value cannot be modified here." was being
+	added even for modifiable options, courtesy of some earlier
+	code rearrangement.
+
+	* config.cxx (change_package_version):
+	Prevent assertion failure/crash when changing the version of a
+	package that has not been loaded (not uncommon when using
+	ecosconfig and confusing the order of the version and the
+	package(s)).
+
 2000-06-28  Bart Veer  <bartv@redhat.com>
 
 	* transact.cxx, cdlcore.hxx:
diff --git a/host/libcdl/config.cxx b/host/libcdl/config.cxx
--- a/host/libcdl/config.cxx
+++ b/host/libcdl/config.cxx
@@ -395,6 +395,9 @@ CdlConfigurationBody::change_package_ver
     }
     // For now it is illegal to change the version of package that has
     // not been loaded yet
+    if (0 == package) {
+        throw CdlInputOutputException(std::string("Cannot change version of \"") + name + "\" , this package is not loaded");
+    }
     CYG_ASSERT_CLASSC(package);
     
     this->change_package_version(transaction, package, new_version, error_fn, warn_fn, limbo);
diff --git a/host/libcdl/value.cxx b/host/libcdl/value.cxx
--- a/host/libcdl/value.cxx
+++ b/host/libcdl/value.cxx
@@ -3790,10 +3790,10 @@ CdlValuableBody::save(CdlInterpreter int
             data += indent_string + "# Calculated value: " +
                 CdlInterpreterBody::extend_comment(expr->get_original_string(), indentation, 4) + '\n';
             data += CdlInterpreterBody::multiline_comment(follow_expr_references(expr, expr), indentation, 4);
-        } else {
+        } else if (!modifiable) {
             data += indent_string + "# This value cannot be modified here.\n";
         }
-        
+         
         // Output the flavor. This clutters up the savefile a bit.
         // However it is necessary so that the user can distinguish
         // between bool, booldata and data items
diff --git a/packages/devs/serial/arm/sa11x0/current/ChangeLog b/packages/devs/serial/arm/sa11x0/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/serial/arm/sa11x0/current/ChangeLog
@@ -0,0 +1,43 @@
+2000-06-29  Jesper Skov  <jskov@redhat.com>
+
+	* src/sa11x0_serial.h: 
+	* src/sa11x0_serial.c:
+	Registers renamed.
+
+2000-06-22  Hugo Tyson  <hmt@cygnus.co.uk>
+
+	* cdl/<yournamehere>.cdl: Remove the comment on the empty
+	include_files directive; the tools now support this correctly.
+	This keeps internal include files internal.
+
+2000-05-10  Gary Thomas  <gthomas@redhat.com>
+
+	* cdl/ser_arm_sa11x0.cdl: 
+	* src/sa11x0_serial.h: 
+	* src/sa11x0_serial.c: New file(s).
+
+//===========================================================================
+//####COPYRIGHTBEGIN####
+//                                                                          
+// -------------------------------------------                              
+// The contents of this file are subject to the Red Hat eCos Public License 
+// Version 1.1 (the "License"); you may not use this file except in         
+// compliance with the License.  You may obtain a copy of the License at    
+// http://www.redhat.com/                                                   
+//                                                                          
+// Software distributed under the License is distributed on an "AS IS"      
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+// License for the specific language governing rights and limitations under 
+// the License.                                                             
+//                                                                          
+// The Original Code is eCos - Embedded Configurable Operating System,      
+// released September 30, 1998.                                             
+//                                                                          
+// The Initial Developer of the Original Code is Red Hat.                   
+// Portions created by Red Hat are                                          
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+// All Rights Reserved.                                                     
+// -------------------------------------------                              
+//                                                                          
+//####COPYRIGHTEND####
+//===========================================================================
diff --git a/packages/devs/serial/arm/sa11x0/current/cdl/ser_arm_sa11x0.cdl b/packages/devs/serial/arm/sa11x0/current/cdl/ser_arm_sa11x0.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/serial/arm/sa11x0/current/cdl/ser_arm_sa11x0.cdl
@@ -0,0 +1,179 @@
+# ====================================================================
+#
+#      ser_arm_sa11x0.cdl
+#
+#      eCos serial ARM/SA11x0 configuration data
+#
+# ====================================================================
+#####COPYRIGHTBEGIN####
+#                                                                          
+# -------------------------------------------                              
+# The contents of this file are subject to the Red Hat eCos Public License 
+# Version 1.1 (the "License"); you may not use this file except in         
+# compliance with the License.  You may obtain a copy of the License at    
+# http://www.redhat.com/                                                   
+#                                                                          
+# Software distributed under the License is distributed on an "AS IS"      
+# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+# License for the specific language governing rights and limitations under 
+# the License.                                                             
+#                                                                          
+# The Original Code is eCos - Embedded Configurable Operating System,      
+# released September 30, 1998.                                             
+#                                                                          
+# The Initial Developer of the Original Code is Red Hat.                   
+# Portions created by Red Hat are                                          
+# Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+# All Rights Reserved.                                                     
+# -------------------------------------------                              
+#                                                                          
+#####COPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      gthomas
+# Contributors:
+# Date:           2000-05-08
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+
+cdl_package CYGPKG_IO_SERIAL_ARM_SA11X0 {
+    display       "ARM SA11X0 serial device drivers"
+
+    parent        CYGPKG_IO_SERIAL_DEVICES
+    active_if     CYGPKG_IO_SERIAL
+    active_if     CYGPKG_HAL_ARM_SA11X0
+
+    requires      CYGPKG_ERROR
+    include_dir   cyg/io
+    include_files ; # none _exported_ whatsoever
+    description   "
+           This option enables the serial device drivers for the
+           StrongARM SA11X0."
+    doc           redirect/ecos-device-drivers.html
+
+    compile       -library=libextras.a   sa11x0_serial.c
+
+    define_proc {
+        puts $::cdl_system_header "/***** serial driver proc output start *****/"
+        puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_arm_sa11x0.h>"
+        puts $::cdl_system_header "/*****  serial driver proc output end  *****/"
+    }
+
+cdl_component CYGPKG_IO_SERIAL_ARM_SA11X0_SERIAL0 {
+    display       "ARM SA11X0 serial port 0 driver"
+    flavor        bool
+    default_value 0
+    description   "
+        This option includes the serial device driver for the ARM SA11X0 
+        port 0 (UART 3)."
+
+    cdl_option CYGDAT_IO_SERIAL_ARM_SA11X0_SERIAL0_NAME {
+        display       "Device name for ARM SA11X0 serial port 0 driver"
+        flavor        data
+        default_value {"\"/dev/ser0\""}
+        description   "
+            This option specifies the name of the serial device for the 
+            ARM SA11X0 port 0."
+    }
+
+    cdl_option CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL0_BAUD {
+        display       "Baud rate for the ARM SA11X0 serial port 0 driver"
+        flavor        data
+        legal_values  { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600
+                      4800 7200 9600 14400 19200 38400 57600 115200 234000
+        }
+        default_value 38400
+        description   "
+            This option specifies the default baud rate (speed) for the 
+            ARM SA11X0 port 0."
+    }
+
+    cdl_option CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL0_BUFSIZE {
+        display       "Buffer size for the ARM SA11X0 serial port 0 driver"
+        flavor        data
+        legal_values  0 to 8192
+        default_value 128
+        description   "
+            This option specifies the size of the internal buffers used 
+            for the ARM SA11X0 port 0."
+    }
+}
+
+cdl_component CYGPKG_IO_SERIAL_ARM_SA11X0_SERIAL1 {
+    display       "ARM SA11X0 serial port 1 driver"
+    flavor        bool
+    default_value 1
+    description   "
+        This option includes the serial device driver for the ARM SA11X0 
+        port 1 (UART 1)."
+
+    cdl_option CYGDAT_IO_SERIAL_ARM_SA11X0_SERIAL1_NAME {
+        display       "Device name for ARM SA11X0 serial port 1 driver"
+        flavor        data
+        default_value {"\"/dev/ser1\""}
+        description   "
+            This option specifies the name of the serial device for the 
+            ARM SA11X0 port 1."
+    }
+
+    cdl_option CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL1_BAUD {
+        display       "Baud rate for the ARM SA11X0 serial port 1 driver"
+        flavor        data
+        legal_values  { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600
+                      4800 7200 9600 14400 19200 38400 57600 115200 234000
+        }
+        default_value 38400
+        description   "
+            This option specifies the default baud rate (speed) for the
+            ARM SA11X0 port 1."
+    }
+
+    cdl_option CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL1_BUFSIZE {
+        display       "Buffer size for the ARM SA11X0 serial port 1 driver"
+        flavor        data
+        legal_values  0 to 8192
+        default_value 128
+        description   "
+            This option specifies the size of the internal buffers used 
+            for the ARM SA11X0 port 1."
+    }
+}
+
+    cdl_component CYGPKG_IO_SERIAL_ARM_SA11X0_OPTIONS {
+        display "Serial device driver build options"
+        flavor  none
+        description   "
+	    Package specific build options including control over
+	    compiler flags used only in building this package,
+	    and details of which tests are built."
+
+
+        cdl_option CYGPKG_IO_SERIAL_ARM_SA11X0_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building these serial device drivers. These flags are used in addition
+                to the set of global flags."
+        }
+
+        cdl_option CYGPKG_IO_SERIAL_ARM_SA11X0_CFLAGS_REMOVE {
+            display "Suppressed compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building these serial device drivers. These flags are removed from
+                the set of global flags if present."
+        }
+    }
+}
+
+# EOF ser_arm_sa11x0.cdl
diff --git a/packages/devs/serial/arm/sa11x0/current/src/sa11x0_serial.c b/packages/devs/serial/arm/sa11x0/current/src/sa11x0_serial.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/serial/arm/sa11x0/current/src/sa11x0_serial.c
@@ -0,0 +1,322 @@
+//==========================================================================
+//
+//      io/serial/arm/sa11x0/sa11x0_serial.c
+//
+//      StrongARM SA11x0 Serial I/O Interface Module (interrupt driven)
+//
+//==========================================================================
+//####COPYRIGHTBEGIN####
+//                                                                          
+// -------------------------------------------                              
+// The contents of this file are subject to the Red Hat eCos Public License 
+// Version 1.1 (the "License"); you may not use this file except in         
+// compliance with the License.  You may obtain a copy of the License at    
+// http://www.redhat.com/                                                   
+//                                                                          
+// Software distributed under the License is distributed on an "AS IS"      
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+// License for the specific language governing rights and limitations under 
+// the License.                                                             
+//                                                                          
+// The Original Code is eCos - Embedded Configurable Operating System,      
+// released September 30, 1998.                                             
+//                                                                          
+// The Initial Developer of the Original Code is Red Hat.                   
+// Portions created by Red Hat are                                          
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+// All Rights Reserved.                                                     
+// -------------------------------------------                              
+//                                                                          
+//####COPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     gthomas
+// Contributors:  gthomas
+// Date:          2000-05-08
+// Purpose:       StrongARM SA11x0 Serial I/O module (interrupt driven version)
+// Description: 
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/io_serial.h>
+#include <pkgconf/io.h>
+#include <pkgconf/kernel.h>
+
+#include <cyg/io/io.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/io/devtab.h>
+#include <cyg/io/serial.h>
+#include <cyg/infra/diag.h>
+
+#ifdef CYGPKG_IO_SERIAL_ARM_SA11X0
+
+#include "sa11x0_serial.h"
+
+typedef struct sa11x0_serial_info {
+    CYG_ADDRWORD   base;
+    CYG_WORD       int_num;
+    cyg_interrupt  serial_interrupt;
+    cyg_handle_t   serial_interrupt_handle;
+} sa11x0_serial_info;
+
+static bool sa11x0_serial_init(struct cyg_devtab_entry *tab);
+static bool sa11x0_serial_putc(serial_channel *chan, unsigned char c);
+static Cyg_ErrNo sa11x0_serial_lookup(struct cyg_devtab_entry **tab, 
+                                   struct cyg_devtab_entry *sub_tab,
+                                   const char *name);
+static unsigned char sa11x0_serial_getc(serial_channel *chan);
+static bool sa11x0_serial_set_config(serial_channel *chan, cyg_serial_info_t *config);
+static void sa11x0_serial_start_xmit(serial_channel *chan);
+static void sa11x0_serial_stop_xmit(serial_channel *chan);
+
+static cyg_uint32 sa11x0_serial_ISR(cyg_vector_t vector, cyg_addrword_t data);
+static void       sa11x0_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data);
+
+static SERIAL_FUNS(sa11x0_serial_funs, 
+                   sa11x0_serial_putc, 
+                   sa11x0_serial_getc,
+                   sa11x0_serial_set_config,
+                   sa11x0_serial_start_xmit,
+                   sa11x0_serial_stop_xmit
+    );
+
+#ifdef CYGPKG_IO_SERIAL_ARM_SA11X0_SERIAL0
+static sa11x0_serial_info sa11x0_serial_info0 = {(CYG_ADDRWORD)SA11X0_UART3_CONTROL0,
+                                                 CYGNUM_HAL_INTERRUPT_UART3};
+#if CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL0_BUFSIZE > 0
+static unsigned char sa11x0_serial_out_buf0[CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL0_BUFSIZE];
+static unsigned char sa11x0_serial_in_buf0[CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL0_BUFSIZE];
+
+static SERIAL_CHANNEL_USING_INTERRUPTS(sa11x0_serial_channel0,
+                                       sa11x0_serial_funs, 
+                                       sa11x0_serial_info0,
+                                       CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL0_BAUD),
+                                       CYG_SERIAL_STOP_DEFAULT,
+                                       CYG_SERIAL_PARITY_DEFAULT,
+                                       CYG_SERIAL_WORD_LENGTH_DEFAULT,
+                                       CYG_SERIAL_FLAGS_DEFAULT,
+                                       &sa11x0_serial_out_buf0[0], sizeof(sa11x0_serial_out_buf0),
+                                       &sa11x0_serial_in_buf0[0], sizeof(sa11x0_serial_in_buf0)
+    );
+#else
+static SERIAL_CHANNEL(sa11x0_serial_channel0,
+                      sa11x0_serial_funs, 
+                      sa11x0_serial_info0,
+                      CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL0_BAUD),
+                      CYG_SERIAL_STOP_DEFAULT,
+                      CYG_SERIAL_PARITY_DEFAULT,
+                      CYG_SERIAL_WORD_LENGTH_DEFAULT,
+                      CYG_SERIAL_FLAGS_DEFAULT
+    );
+#endif
+
+DEVTAB_ENTRY(sa11x0_serial_io0, 
+             CYGDAT_IO_SERIAL_ARM_SA11X0_SERIAL0_NAME,
+             0,                     // Does not depend on a lower level interface
+             &cyg_io_serial_devio, 
+             sa11x0_serial_init, 
+             sa11x0_serial_lookup,     // Serial driver may need initializing
+             &sa11x0_serial_channel0
+    );
+#endif //  CYGPKG_IO_SERIAL_ARM_SA11X0_SERIAL1
+
+#ifdef CYGPKG_IO_SERIAL_ARM_SA11X0_SERIAL1
+static sa11x0_serial_info sa11x0_serial_info1 = {(CYG_ADDRWORD)SA11X0_UART1_CONTROL0,
+                                                 CYGNUM_HAL_INTERRUPT_UART1};
+#if CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL1_BUFSIZE > 0
+static unsigned char sa11x0_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL1_BUFSIZE];
+static unsigned char sa11x0_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL1_BUFSIZE];
+
+static SERIAL_CHANNEL_USING_INTERRUPTS(sa11x0_serial_channel1,
+                                       sa11x0_serial_funs, 
+                                       sa11x0_serial_info1,
+                                       CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL1_BAUD),
+                                       CYG_SERIAL_STOP_DEFAULT,
+                                       CYG_SERIAL_PARITY_DEFAULT,
+                                       CYG_SERIAL_WORD_LENGTH_DEFAULT,
+                                       CYG_SERIAL_FLAGS_DEFAULT,
+                                       &sa11x0_serial_out_buf1[0], sizeof(sa11x0_serial_out_buf1),
+                                       &sa11x0_serial_in_buf1[0], sizeof(sa11x0_serial_in_buf1)
+    );
+#else
+static SERIAL_CHANNEL(sa11x0_serial_channel1,
+                      sa11x0_serial_funs, 
+                      sa11x0_serial_info1,
+                      CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_SA11X0_SERIAL1_BAUD),
+                      CYG_SERIAL_STOP_DEFAULT,
+                      CYG_SERIAL_PARITY_DEFAULT,
+                      CYG_SERIAL_WORD_LENGTH_DEFAULT,
+                      CYG_SERIAL_FLAGS_DEFAULT
+    );
+#endif
+
+DEVTAB_ENTRY(sa11x0_serial_io1, 
+             CYGDAT_IO_SERIAL_ARM_SA11X0_SERIAL1_NAME,
+             0,                     // Does not depend on a lower level interface
+             &cyg_io_serial_devio, 
+             sa11x0_serial_init, 
+             sa11x0_serial_lookup,     // Serial driver may need initializing
+             &sa11x0_serial_channel1
+    );
+#endif //  CYGPKG_IO_SERIAL_ARM_SA11X0_SERIAL1
+
+// Internal function to actually configure the hardware to desired baud rate, etc.
+static bool
+sa11x0_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init)
+{
+    sa11x0_serial_info *sa11x0_chan = (sa11x0_serial_info *)chan->dev_priv;
+    volatile struct serial_port *port = (volatile struct serial_port *)sa11x0_chan->base;
+    unsigned char parity = select_parity[new_config->parity];
+    unsigned char word_length = select_word_length[new_config->word_length-CYGNUM_SERIAL_WORD_LENGTH_5];
+    unsigned char stop_bits = select_stop_bits[new_config->stop];
+    int baud = SA11X0_UART_BAUD_RATE_DIVISOR(select_baud[new_config->baud]);
+    if ((word_length == 0xFF) ||
+        (parity == 0xFF) ||
+        (stop_bits == 0xFF)) {
+        return false;  // Unsupported configuration
+    }
+    // Disable Receiver and Transmitter (clears FIFOs)
+    port->ctl3 = SA11X0_UART_RX_DISABLED |
+                 SA11X0_UART_TX_DISABLED;
+
+    // Clear sticky (writable) status bits.
+    port->stat0 = SA11X0_UART_RX_IDLE |
+                  SA11X0_UART_RX_BEGIN_OF_BREAK |
+                  SA11X0_UART_RX_END_OF_BREAK;
+
+    // Set parity, word length, stop bits
+    port->ctl0 = parity |
+                 word_length |
+                 stop_bits;
+
+    // Set the desired baud rate.
+    port->ctl1 = (baud >> 8) & SA11X0_UART_H_BAUD_RATE_DIVISOR_MASK;
+    port->ctl2 = baud & SA11X0_UART_L_BAUD_RATE_DIVISOR_MASK;
+
+    // Enable the receiver (with interrupts) and the transmitter.
+    port->ctl3 = SA11X0_UART_RX_ENABLED |
+                 SA11X0_UART_TX_ENABLED |
+                 SA11X0_UART_RX_FIFO_INT_ENABLED;
+    return true;
+}
+
+// Function to initialize the device.  Called at bootstrap time.
+static bool 
+sa11x0_serial_init(struct cyg_devtab_entry *tab)
+{
+    serial_channel *chan = (serial_channel *)tab->priv;
+    sa11x0_serial_info *sa11x0_chan = (sa11x0_serial_info *)chan->dev_priv;
+    int res;
+#ifdef CYGDBG_IO_INIT
+    diag_printf("SA11X0 SERIAL init - dev: %x.%d\n", sa11x0_chan->base, sa11x0_chan->int_num);
+#endif
+    (chan->callbacks->serial_init)(chan);  // Really only required for interrupt driven devices
+    if (chan->out_cbuf.len != 0) {
+        cyg_drv_interrupt_create(sa11x0_chan->int_num,
+                                 99,                     // Priority - unused
+                                 (cyg_addrword_t)chan,   // Data item passed to interrupt handler
+                                 sa11x0_serial_ISR,
+                                 sa11x0_serial_DSR,
+                                 &sa11x0_chan->serial_interrupt_handle,
+                                 &sa11x0_chan->serial_interrupt);
+        cyg_drv_interrupt_attach(sa11x0_chan->serial_interrupt_handle);
+        cyg_drv_interrupt_unmask(sa11x0_chan->int_num);
+    }
+    res = sa11x0_serial_config_port(chan, &chan->config, true);
+    return res;
+}
+
+// This routine is called when the device is "looked" up (i.e. attached)
+static Cyg_ErrNo 
+sa11x0_serial_lookup(struct cyg_devtab_entry **tab, 
+                  struct cyg_devtab_entry *sub_tab,
+                  const char *name)
+{
+    serial_channel *chan = (serial_channel *)(*tab)->priv;
+    (chan->callbacks->serial_init)(chan);  // Really only required for interrupt driven devices
+    return ENOERR;
+}
+
+// Send a character to the device output buffer.
+// Return 'true' if character is sent to device
+static bool
+sa11x0_serial_putc(serial_channel *chan, unsigned char c)
+{
+    sa11x0_serial_info *sa11x0_chan = (sa11x0_serial_info *)chan->dev_priv;
+    volatile struct serial_port *port = (volatile struct serial_port *)sa11x0_chan->base;
+    if (port->stat1 & SA11X0_UART_TX_FIFO_NOT_FULL) {
+        port->data = c;
+        return true;
+    } else {
+        return false;  // Couldn't send, tx was busy
+    }
+}
+
+// Fetch a character from the device input buffer, waiting if necessary
+static unsigned char 
+sa11x0_serial_getc(serial_channel *chan)
+{
+    sa11x0_serial_info *sa11x0_chan = (sa11x0_serial_info *)chan->dev_priv;
+    volatile struct serial_port *port = (volatile struct serial_port *)sa11x0_chan->base;
+    return port->data;
+}
+
+// Set up the device characteristics; baud rate, etc.
+static bool 
+sa11x0_serial_set_config(serial_channel *chan, cyg_serial_info_t *config)
+{
+    return sa11x0_serial_config_port(chan, config, false);
+}
+
+// Enable the transmitter on the device
+static void
+sa11x0_serial_start_xmit(serial_channel *chan)
+{
+    sa11x0_serial_info *sa11x0_chan = (sa11x0_serial_info *)chan->dev_priv;
+    volatile struct serial_port *port = (volatile struct serial_port *)sa11x0_chan->base;
+    (chan->callbacks->xmt_char)(chan);  // Kick transmitter (if necessary)
+    port->ctl3 |= SA11X0_UART_TX_FIFO_INT_ENABLED;
+}
+
+// Disable the transmitter on the device
+static void 
+sa11x0_serial_stop_xmit(serial_channel *chan)
+{
+    sa11x0_serial_info *sa11x0_chan = (sa11x0_serial_info *)chan->dev_priv;
+    volatile struct serial_port *port = (volatile struct serial_port *)sa11x0_chan->base;
+    port->ctl3 &= ~SA11X0_UART_TX_FIFO_INT_ENABLED;
+}
+
+// Serial I/O - low level interrupt handler (ISR)
+static cyg_uint32 
+sa11x0_serial_ISR(cyg_vector_t vector, cyg_addrword_t data)
+{
+    cyg_drv_interrupt_mask(vector);
+    cyg_drv_interrupt_acknowledge(vector);
+    return CYG_ISR_CALL_DSR;  // Cause DSR to be run
+}
+
+// Serial I/O - high level interrupt handler (DSR)
+static void       
+sa11x0_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
+{
+    serial_channel *chan = (serial_channel *)data;
+    sa11x0_serial_info *sa11x0_chan = (sa11x0_serial_info *)chan->dev_priv;
+    volatile struct serial_port *port = (volatile struct serial_port *)sa11x0_chan->base;
+    unsigned int stat0 = port->stat0;
+    if (stat0 & SA11X0_UART_TX_SERVICE_REQUEST) {
+        (chan->callbacks->xmt_char)(chan);
+    }
+    if (stat0 & SA11X0_UART_RX_INTS) {
+        while (port->stat1 & SA11X0_UART_RX_FIFO_NOT_EMPTY) {
+            (chan->callbacks->rcv_char)(chan, port->data);
+        }
+        port->stat0 = SA11X0_UART_RX_IDLE;  // Need to clear this manually
+    }
+    cyg_drv_interrupt_unmask(vector);
+}
+#endif
diff --git a/packages/devs/serial/arm/sa11x0/current/src/sa11x0_serial.h b/packages/devs/serial/arm/sa11x0/current/src/sa11x0_serial.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/serial/arm/sa11x0/current/src/sa11x0_serial.h
@@ -0,0 +1,114 @@
+#ifndef CYGONCE_ARM_SA11X0_SERIAL_H
+#define CYGONCE_ARM_SA11X0_SERIAL_H
+
+// ====================================================================
+//
+//      sa11x0_serial.h
+//
+//      Device I/O - Description of StrongARM SA11x0 serial hardware
+//
+// ====================================================================
+//####COPYRIGHTBEGIN####
+//                                                                          
+// -------------------------------------------                              
+// The contents of this file are subject to the Red Hat eCos Public License 
+// Version 1.1 (the "License"); you may not use this file except in         
+// compliance with the License.  You may obtain a copy of the License at    
+// http://www.redhat.com/                                                   
+//                                                                          
+// Software distributed under the License is distributed on an "AS IS"      
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+// License for the specific language governing rights and limitations under 
+// the License.                                                             
+//                                                                          
+// The Original Code is eCos - Embedded Configurable Operating System,      
+// released September 30, 1998.                                             
+//                                                                          
+// The Initial Developer of the Original Code is Red Hat.                   
+// Portions created by Red Hat are                                          
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+// All Rights Reserved.                                                     
+// -------------------------------------------                              
+//                                                                          
+//####COPYRIGHTEND####
+// ====================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+// Date:         2000-05-08
+// Purpose:      Internal interfaces for serial I/O drivers
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+// ====================================================================
+
+// Description of serial ports on StrongARM SA11x0
+
+#include <cyg/hal/hal_sa11x0.h>  // Register definitions
+
+struct serial_port {
+    unsigned long ctl0;   // 0x00
+    unsigned long ctl1;   // 0x04
+    unsigned long ctl2;   // 0x08
+    unsigned long ctl3;   // 0x0C
+    unsigned long _unused0;
+    unsigned long data;   // 0x14
+    unsigned long _unused1;
+    unsigned long stat0;  // 0x1C
+    unsigned long stat1;  // 0x20
+};
+
+#define SA11X0_UART_RX_INTS (SA11X0_UART_RX_SERVICE_REQUEST|SA11X0_UART_RX_IDLE)
+
+static unsigned char select_word_length[] = {
+    0xFF,                         // 5 bits / word (char)
+    0xFF,
+    SA11X0_UART_DATA_BITS_7,
+    SA11X0_UART_DATA_BITS_8
+};
+
+static unsigned char select_stop_bits[] = {
+    0,
+    SA11X0_UART_STOP_BITS_1,      // 1 stop bit
+    0xFF,                         // 1.5 stop bit
+    SA11X0_UART_STOP_BITS_2       // 2 stop bits
+};
+
+static unsigned char select_parity[] = {
+    SA11X0_UART_PARITY_DISABLED,  // No parity
+    SA11X0_UART_PARITY_ENABLED|   // Even parity
+    SA11X0_UART_PARITY_EVEN,
+    SA11X0_UART_PARITY_ENABLED|   // Odd parity
+    SA11X0_UART_PARITY_ODD,
+    0xFF,                         // Mark parity
+    0xFF,                         // Space parity
+};
+
+static cyg_int32 select_baud[] = {
+    0,      // Unused
+    50,     // 50
+    75,     // 75
+    110,    // 110
+    0,      // 134.5
+    150,    // 150
+    200,    // 200
+    300,    // 300
+    600,    // 600
+    1200,   // 1200
+    1800,   // 1800
+    2400,   // 2400
+    3600,   // 3600
+    4800,   // 4800
+    7200,   // 7200
+    9600,   // 9600
+    14400,  // 14400
+    19200,  // 19200
+    38400,  // 38400
+    57600,  // 57600
+    115200, // 115200
+    230400, // 230400
+};
+
+#endif // CYGONCE_ARM_SA11X0_SERIAL_H
diff --git a/packages/ecos.db b/packages/ecos.db
--- a/packages/ecos.db
+++ b/packages/ecos.db
@@ -95,6 +95,15 @@ package CYGPKG_IO_SERIAL_ARM_EBSA285 {
     description       "Intel StrongARM/EBSA285 serial device drivers"
 }
 
+package CYGPKG_IO_SERIAL_ARM_SA11X0 {
+    alias 	      { "Intel StrongARM SA11x0 serial driver"
+                        devs_serial_arm_sa11x0 sa11x0_serial_driver }
+    hardware
+    directory	      devs/serial/arm/sa11x0
+    script	      ser_arm_sa11x0.cdl	
+    description       "Intel StrongARM/SA11x0 serial device drivers"
+}
+
 package CYGPKG_IO_SERIAL_ARM_PID {
     alias             { "ARM PID serial device drivers"
                         devs_serial_arm_pid pid_serial_driver }
@@ -475,6 +484,34 @@ package CYGPKG_HAL_ARM_EBSA285 {
         eCos on a Intel EBSA285 StrongARM eval board."
 }
 
+package CYGPKG_HAL_ARM_SA11X0 {
+	alias		{ "Intel SA11X0 Chipset" hal_arm_sa11x0 }
+	directory	hal/arm/sa11x0/var
+	script		hal_arm_sa11x0.cdl
+	hardware
+        description "
+        The SA11X0 HAL package provides the support needed to run
+        eCos on a Intel StrongARM SA11X0 based systems."
+}
+package CYGPKG_HAL_ARM_SA11X0_ASSABET {
+	alias		{ "Intel SA1110 Assabet eval board" hal_arm_sa11x0_assabet }
+	directory	hal/arm/sa11x0/assabet
+	script		hal_arm_sa11x0_assabet.cdl
+	hardware
+        description "
+        The ASSABET HAL package provides the support needed to run
+        eCos on a Intel StrongARM SA1110 evaulation board (assabet)."
+}
+package CYGPKG_HAL_ARM_SA11X0_BRUTUS {
+	alias		{ "Intel SA1100 Brutus eval board" hal_arm_sa11x0_brutus }
+	directory	hal/arm/sa11x0/brutus
+	script		hal_arm_sa11x0_brutus.cdl
+	hardware
+        description "
+        The BRUTUS HAL package provides the support needed to run
+        eCos on a Intel StrongARM SA1110 evaulation board (brutus)."
+}
+
 package CYGPKG_HAL_ARM_EDB7XXX {
 	alias		{ "Cirrus Logic development board" hal_arm_edb7xxx arm_edb7xxx_hal }
 	directory	hal/arm/edb7xxx
@@ -907,6 +944,29 @@ target ebsa285 {
         eCos on an Intel EBSA285 StrongARM board."
 }
 
+target assabet {
+	alias { "Intel StrongARM SA1110 board" assabet }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_SA11X0
+                   CYGPKG_HAL_ARM_SA11X0_ASSABET
+		   CYGPKG_IO_SERIAL_ARM_SA11X0
+        }
+        description "
+        The assabet target provides the packages needed to run
+        eCos on an Intel StrongARM SA1110 evaluation board."
+}
+target brutus {
+	alias { "Intel StrongARM SA1100 board" brutus }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_SA11X0
+                   CYGPKG_HAL_ARM_SA11X0_BRUTUS
+		   CYGPKG_IO_SERIAL_ARM_SA11X0
+        }
+        description "
+        The brutus target provides the packages needed to run
+        eCos on an Intel StrongARM SA1100 evaluation board."
+}
+
 target edb7xxx {
         alias		{ "Cirrus Logic development board" edb7211 eb7xxx eb7211 }
 	packages	{ CYGPKG_HAL_ARM
diff --git a/packages/hal/arm/arch/current/src/vectors.S b/packages/hal/arm/arch/current/src/vectors.S
--- a/packages/hal/arm/arch/current/src/vectors.S
+++ b/packages/hal/arm/arch/current/src/vectors.S
@@ -231,9 +231,11 @@ warm_reset:
         mov     r0,#0           // move vectors
         // We cannot perform a store until after PLATFORM_SETUP1
 #ifndef CYGPKG_HAL_ARM_EBSA285  // EBSA285 sets the DRAM size above
+#ifndef CYGPKG_HAL_ARM_SA11X0   // SA11x0 also uses this
         ldr     r1,=hal_dram_size
         str     r0, [r1]        // DRAM size to zero => unknown
 #endif
+#endif
 
         ldr     r1,=__exception_handlers
 #ifndef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
diff --git a/packages/hal/arm/pid/current/ChangeLog b/packages/hal/arm/pid/current/ChangeLog
--- a/packages/hal/arm/pid/current/ChangeLog
+++ b/packages/hal/arm/pid/current/ChangeLog
@@ -1,3 +1,13 @@
+2000-07-04  Jesper Skov  <jskov@redhat.com>
+
+	* cdl/hal_arm_pid.cdl:
+	* include/hal_diag.h:
+	* include/plf_stub.h:
+	* src/hal_diag.c:
+	* src/pid_misc.c:
+	* src/plf_stub.c: [deleted]
+	Changed to use virtual vector table.
+	
 2000-06-18  Gary Thomas  <gthomas@redhat.com>
 
 	* include/pkgconf/mlt_arm_pid9_ram.ldi: 
diff --git a/packages/hal/arm/pid/current/cdl/hal_arm_pid.cdl b/packages/hal/arm/pid/current/cdl/hal_arm_pid.cdl
--- a/packages/hal/arm/pid/current/cdl/hal_arm_pid.cdl
+++ b/packages/hal/arm/pid/current/cdl/hal_arm_pid.cdl
@@ -50,10 +50,11 @@ cdl_package CYGPKG_HAL_ARM_PID {
         The pid HAL package provides the support needed to run
         eCos on an ARM PID evaluation board."
 
-    compile       hal_diag.c plf_stub.c pid_misc.c
+    compile       hal_diag.c pid_misc.c
 
     implements    CYGINT_HAL_DEBUG_GDB_STUBS
     implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
 
     define_proc {
         puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_arm.h>"
@@ -141,6 +142,34 @@ cdl_package CYGPKG_HAL_ARM_PID {
             point."
    }
 
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        calculated   2
+    }
+ 
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    CYGHWR_HAL_ARM_PID_GDB_PORT
+        description      "
+            The PID board has only one serial port. This option
+            chooses which port will be used to connect to a host
+            running GDB."
+     }
+ 
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display          "Diagnostic serial port"
+         flavor data
+         legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+         default_value    CYGHWR_HAL_ARM_PID_DIAG_PORT
+         description      "
+            The PID board has only one serial port.  This option
+            chooses which port will be used for diagnostic output."
+     }
+
     # Real-time clock/counter specifics
     cdl_component CYGNUM_HAL_RTC_CONSTANTS {
         display       "Real-time clock constants"
@@ -220,8 +249,8 @@ cdl_package CYGPKG_HAL_ARM_PID {
             requires { CYG_HAL_STARTUP == "ROM" }
             requires CYGSEM_HAL_ROM_MONITOR
             requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
-            requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
-            requires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+            requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+            requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
             requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
             requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
             no_define
@@ -373,4 +402,26 @@ cdl_package CYGPKG_HAL_ARM_PID {
             }
         }
     }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+         display       "Work with a ROM monitor"
+         flavor        booldata
+         legal_values  { "Generic" "GDB_stubs" }
+         default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+         parent        CYGPKG_HAL_ROM_MONITOR
+         requires      { CYG_HAL_STARTUP == "RAM" }
+         description   "
+             Support can be enabled for different varieties of ROM monitor.
+             This support changes various eCos semantics such as the encoding
+             of diagnostic output, or the overriding of hardware interrupt
+             vectors.
+             Firstly there is \"Generic\" support which prevents the HAL
+             from overriding the hardware vectors that it does not use, to
+             instead allow an installed ROM monitor to handle them. This is
+             the most basic support which is likely to be common to most
+             implementations of ROM monitor.
+             \"GDB_stubs\" provides support when GDB stubs are included in
+             the ROM monitor or boot ROM."
+     }
+
 }
diff --git a/packages/hal/arm/pid/current/include/hal_diag.h b/packages/hal/arm/pid/current/include/hal_diag.h
--- a/packages/hal/arm/pid/current/include/hal_diag.h
+++ b/packages/hal/arm/pid/current/include/hal_diag.h
@@ -49,6 +49,16 @@
 
 #include <cyg/infra/cyg_type.h>
 
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+#include <cyg/hal/hal_if.h>
+
+#define HAL_DIAG_INIT() hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
+
+#else // everything by steam
+
 /*---------------------------------------------------------------------------*/
 /* functions implemented in hal_diag.c                                       */
 
@@ -56,8 +66,6 @@ externC void hal_diag_init(void);
 externC void hal_diag_write_char(char c);
 externC void hal_diag_read_char(char *c);
 
-externC void hal_diag_led(int n);
-
 /*---------------------------------------------------------------------------*/
 
 #define HAL_DIAG_INIT() hal_diag_init()
@@ -66,6 +74,13 @@ externC void hal_diag_led(int n);
 
 #define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_)
 
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
+// LED
+
+externC void hal_diag_led(int n);
+
 /*---------------------------------------------------------------------------*/
 /* end of hal_diag.h                                                         */
 #endif /* CYGONCE_HAL_DIAG_H */
diff --git a/packages/hal/arm/pid/current/include/plf_stub.h b/packages/hal/arm/pid/current/include/plf_stub.h
--- a/packages/hal/arm/pid/current/include/plf_stub.h
+++ b/packages/hal/arm/pid/current/include/plf_stub.h
@@ -54,36 +54,30 @@
 #include <cyg/hal/arm_stub.h>           // architecture stub support
 
 //----------------------------------------------------------------------------
-// Define serial stuff.
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
 
-extern void hal_pid_init_serial(void);
-extern int  hal_pid_get_char(void);
-extern void hal_pid_put_char(int c);
-extern int  hal_pid_interruptible(int);
+externC void cyg_hal_plf_comms_init(void);
 
-#define HAL_STUB_PLATFORM_INIT_SERIAL()       hal_pid_init_serial()
-#define HAL_STUB_PLATFORM_GET_CHAR()          hal_pid_get_char()
-#define HAL_STUB_PLATFORM_PUT_CHAR(c)         hal_pid_put_char((c))
+#define HAL_STUB_PLATFORM_INIT_SERIAL()       cyg_hal_plf_comms_init()
+
 #define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
-#define HAL_STUB_PLATFORM_INTERRUPTIBLE       (&hal_pid_interruptible)
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE       0
 #define HAL_STUB_PLATFORM_INIT_BREAK_IRQ()    CYG_EMPTY_STATEMENT
 
 //----------------------------------------------------------------------------
 // Stub initializer.
 #define HAL_STUB_PLATFORM_INIT()              CYG_EMPTY_STATEMENT
 
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
 //----------------------------------------------------------------------------
 // Reset.
-#ifdef CYGSEM_HAL_ROM_MONITOR
-// Just call the ROM's entry point. Not as safe as a reset, but the PID
-// doesn't have a watchdog, so this'll have to do.
-externC void reset_vector(void);
-#define HAL_STUB_PLATFORM_RESET() reset_vector()
-#else
+
 #define HAL_STUB_PLATFORM_RESET() CYG_EMPTY_STATEMENT
-#endif
 
-#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#define HAL_STUB_PLATFORM_RESET_ENTRY 0x4000000
 
 //-----------------------------------------------------------------------------
 #endif // CYGONCE_HAL_PLF_STUB_H
diff --git a/packages/hal/arm/pid/current/src/Notes_GDB_stub b/packages/hal/arm/pid/current/src/Notes_GDB_stub
--- a/packages/hal/arm/pid/current/src/Notes_GDB_stub
+++ b/packages/hal/arm/pid/current/src/Notes_GDB_stub
@@ -50,8 +50,6 @@ This will install some files in ./instal
 
 Make FLASH tool
 ~~~~~~~~~~~~~~~
-Make FLASH tool
-~~~~~~~~~~~~~~~
 
 Again, these are the necessary CLI instructions. It can also be done
 from the Configtool by selecting the appropriate templates, and
diff --git a/packages/hal/arm/pid/current/src/hal_diag.c b/packages/hal/arm/pid/current/src/hal_diag.c
--- a/packages/hal/arm/pid/current/src/hal_diag.c
+++ b/packages/hal/arm/pid/current/src/hal_diag.c
@@ -32,7 +32,7 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):   nickg, gthomas
-// Contributors:        nickg, gthomas
+// Contributors:nickg, gthomas
 // Date:        1998-03-02
 // Purpose:     HAL diagnostic output
 // Description: Implementations of HAL diagnostic output support.
@@ -52,91 +52,51 @@
 #include <cyg/hal/hal_intr.h>           // interrupt macros
 #include <cyg/hal/hal_io.h>             // IO macros
 #include <cyg/hal/hal_diag.h>
-#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 #include <cyg/hal/drv_api.h>
-#include <cyg/hal/hal_stub.h>           // cyg_hal_gdb_interrupt
-#endif
-
-// Assumption: all diagnostic output must be GDB packetized unless this is a ROM (i.e.
-// totally stand-alone) system.
-
-#if defined(CYG_HAL_STARTUP_ROM) || defined(CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL)
-#define HAL_DIAG_USES_HARDWARE
-#endif
-
-#ifndef HAL_DIAG_USES_HARDWARE
-#if (CYGHWR_HAL_ARM_PID_DIAG_PORT != CYGHWR_HAL_ARM_PID_GDB_PORT)
-#define HAL_DIAG_USES_HARDWARE
-#endif
-#endif
+#include <cyg/hal/hal_if.h>             // interface API
+#include <cyg/hal/hal_misc.h>           // Helper functions
 
 /*---------------------------------------------------------------------------*/
 /* From serial_16550.h */
-#if CYGHWR_HAL_ARM_PID_DIAG_PORT==0
-// This is the base address of the A-channel
-#define CYG_DEVICE_SERIAL_RS232_16550_BASE      0x0D800000
-#define CYG_DEVICE_SERIAL_INT                   CYGNUM_HAL_INTERRUPT_SERIALA
-#else
-// This is the base address of the B-channel
-#define CYG_DEVICE_SERIAL_RS232_16550_BASE      0x0D800020
-#define CYG_DEVICE_SERIAL_INT                   CYGNUM_HAL_INTERRUPT_SERIALB
+#if CYGHWR_HAL_ARM_PID_DIAG_BAUD==9600
+#define CYG_DEVICE_SERIAL_BAUD_MSB        0x00
+#define CYG_DEVICE_SERIAL_BAUD_LSB        0x0C
+#endif
+#if CYGHWR_HAL_ARM_PID_DIAG_BAUD==19200
+#define CYG_DEVICE_SERIAL_BAUD_MSB        0x00
+#define CYG_DEVICE_SERIAL_BAUD_LSB        0x06
+#endif
+#if CYGHWR_HAL_ARM_PID_DIAG_BAUD==38400
+#define CYG_DEVICE_SERIAL_BAUD_MSB        0x00
+#define CYG_DEVICE_SERIAL_BAUD_LSB        0x03
+#endif
+#if CYGHWR_HAL_ARM_PID_DIAG_BAUD==115200
+#define CYG_DEVICE_SERIAL_BAUD_MSB        0x00
+#define CYG_DEVICE_SERIAL_BAUD_LSB        0x01
 #endif
 
-#if CYGHWR_HAL_ARM_PID_DIAG_BAUD==9600
-#define CYG_DEVICE_SERIAL_RS232_BAUD_MSB        0x00
-#define CYG_DEVICE_SERIAL_RS232_BAUD_LSB        0x0C
-#endif
-#if CYGHWR_HAL_ARM_PID_DIAG_BAUD==19200
-#define CYG_DEVICE_SERIAL_RS232_BAUD_MSB        0x00
-#define CYG_DEVICE_SERIAL_RS232_BAUD_LSB        0x06
-#endif
-#if CYGHWR_HAL_ARM_PID_DIAG_BAUD==38400
-#define CYG_DEVICE_SERIAL_RS232_BAUD_MSB        0x00
-#define CYG_DEVICE_SERIAL_RS232_BAUD_LSB        0x03
-#endif
-#if CYGHWR_HAL_ARM_PID_DIAG_BAUD==115200
-#define CYG_DEVICE_SERIAL_RS232_BAUD_MSB        0x00
-#define CYG_DEVICE_SERIAL_RS232_BAUD_LSB        0x01
-#endif
-
-#ifndef CYG_DEVICE_SERIAL_RS232_BAUD_MSB
+#ifndef CYG_DEVICE_SERIAL_BAUD_MSB
 #error Missing/incorrect serial baud rate defined - CDL error?
 #endif
 
 // Define the serial registers.
-#define CYG_DEVICE_SERIAL_RS232_16550_RBR \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x00)
-    // receiver buffer register, read, dlab = 0
-#define CYG_DEVICE_SERIAL_RS232_16550_THR \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x00)
-    // transmitter holding register, write, dlab = 0
-#define CYG_DEVICE_SERIAL_RS232_16550_DLL \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x00)
-    // divisor latch (LS), read/write, dlab = 1
-#define CYG_DEVICE_SERIAL_RS232_16550_IER \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x04)
-    // interrupt enable register, read/write, dlab = 0
-#define CYG_DEVICE_SERIAL_RS232_16550_DLM \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x04)
-    // divisor latch (MS), read/write, dlab = 1
-#define CYG_DEVICE_SERIAL_RS232_16550_IIR \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x08)
-    // interrupt identification register, read, dlab = 0
-#define CYG_DEVICE_SERIAL_RS232_16550_FCR \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x08)
-    // fifo control register, write, dlab = 0
-#define CYG_DEVICE_SERIAL_RS232_16550_LCR \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x0C)
-    // line control register, read/write
-#define CYG_DEVICE_SERIAL_RS232_16550_MCR \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x10)
-    // modem control register, read/write
-#define CYG_DEVICE_SERIAL_RS232_16550_LSR \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x14)
-    // line status register, read
-#define CYG_DEVICE_SERIAL_RS232_16550_MSR \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x18)
-    // modem status register, read
+#define CYG_DEV_RBR 0x00   // receiver buffer register, read, dlab = 0
+#define CYG_DEV_THR 0x00   // transmitter holding register, write, dlab = 0
+#define CYG_DEV_DLL 0x00   // divisor latch (LS), read/write, dlab = 1
+#define CYG_DEV_IER 0x04   // interrupt enable register, read/write, dlab = 0
+#define CYG_DEV_DLM 0x04   // divisor latch (MS), read/write, dlab = 1
+#define CYG_DEV_IIR 0x08   // interrupt identification register, read, dlab = 0
+#define CYG_DEV_FCR 0x08   // fifo control register, write, dlab = 0
+#define CYG_DEV_LCR 0x0C   // line control register, read/write
+#define CYG_DEV_MCR 0x10   // modem control register, read/write
+#define CYG_DEV_LSR 0x14   // line status register, read
+#define CYG_DEV_MSR 0x18   // modem status register, read
+
+// Interrupt Enable Register
+#define SIO_IER_RCV 0x01
+#define SIO_IER_XMT 0x02
+#define SIO_IER_LS  0x04
+#define SIO_IER_MS  0x08
 
 // The line status register bits.
 #define SIO_LSR_DR      0x01            // data ready
@@ -168,6 +128,318 @@
 #define SIO_LCR_SB     0x40             // set break
 #define SIO_LCR_DLAB   0x80             // divisor latch access bit
 
+// Modem Control Register
+#define SIO_MCR_DTR 0x01
+#define SIO_MCR_RTS 0x02
+#define SIO_MCR_INT 0x08   // Enable interrupts
+
+//-----------------------------------------------------------------------------
+typedef struct {
+    cyg_uint8* base;
+    cyg_int32 msec_timeout;
+    int isr_vector;
+} channel_data_t;
+
+//-----------------------------------------------------------------------------
+
+static void
+cyg_hal_plf_serial_init_channel(void* __ch_data)
+{
+    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
+    cyg_uint8 lcr;
+
+    // 8-1-no parity.
+    HAL_WRITE_UINT8(base+CYG_DEV_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1);
+
+    HAL_READ_UINT8(base+CYG_DEV_LCR, lcr);
+    lcr |= SIO_LCR_DLAB;
+    HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr);
+    HAL_WRITE_UINT8(base+CYG_DEV_DLL, CYG_DEVICE_SERIAL_BAUD_LSB);
+    HAL_WRITE_UINT8(base+CYG_DEV_DLM, CYG_DEVICE_SERIAL_BAUD_MSB);
+    lcr &= ~SIO_LCR_DLAB;
+    HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr);
+    HAL_WRITE_UINT8(base+CYG_DEV_FCR, 0x07);  // Enable & clear FIFO
+}
+
+void
+cyg_hal_plf_serial_putc(void *__ch_data, char c)
+{
+    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
+    cyg_uint8 lsr;
+    CYGARC_HAL_SAVE_GP();
+
+    do {
+        HAL_READ_UINT8(base+CYG_DEV_LSR, lsr);
+    } while ((lsr & SIO_LSR_THRE) == 0);
+
+    HAL_WRITE_UINT8(base+CYG_DEV_THR, c);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool
+cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
+    cyg_uint8 lsr;
+
+    HAL_READ_UINT8(base+CYG_DEV_LSR, lsr);
+    if ((lsr & SIO_LSR_DR) == 0)
+        return false;
+
+    HAL_READ_UINT8(base+CYG_DEV_RBR, *ch);
+
+    return true;
+}
+
+cyg_uint8
+cyg_hal_plf_serial_getc(void* __ch_data)
+{
+    cyg_uint8 ch;
+    CYGARC_HAL_SAVE_GP();
+
+    while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+    CYGARC_HAL_RESTORE_GP();
+    return ch;
+}
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) \
+    || defined(CYGPRI_HAL_IMPLEMENTS_IF_SERVICES)
+
+static channel_data_t pid_ser_channels[2] = {
+    { (cyg_uint8*)0x0D800000, 1000, CYGNUM_HAL_INTERRUPT_SERIALA },
+    { (cyg_uint8*)0x0D800020, 1000, CYGNUM_HAL_INTERRUPT_SERIALB }
+};
+
+static void
+cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, 
+                         cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void
+cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool
+cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+    int delay_count;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_bool res;
+    CYGARC_HAL_SAVE_GP();
+
+    delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+
+    for(;;) {
+        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
+        if (res || 0 == delay_count--)
+            break;
+        
+        CYGACC_CALL_IF_DELAY_US(100);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static int
+cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+    static int irq_state = 0;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    int ret = 0;
+    CYGARC_HAL_SAVE_GP();
+
+    switch (__func) {
+    case __COMMCTL_IRQ_ENABLE:
+        irq_state = 1;
+
+        HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, SIO_IER_RCV);
+        HAL_WRITE_UINT8(chan->base+CYG_DEV_MCR, SIO_MCR_INT|SIO_MCR_DTR|SIO_MCR_RTS);
+
+        HAL_INTERRUPT_UNMASK(chan->isr_vector);
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = irq_state;
+        irq_state = 0;
+
+        HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, 0);
+
+        HAL_INTERRUPT_MASK(chan->isr_vector);
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = chan->isr_vector;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+    {
+        va_list ap;
+
+        va_start(ap, __func);
+
+        ret = chan->msec_timeout;
+        chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+        va_end(ap);
+    }        
+    default:
+        break;
+    }
+    CYGARC_HAL_RESTORE_GP();
+    return ret;
+}
+
+static int
+cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, 
+                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+    int res = 0;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    char c;
+    cyg_uint8 lsr;
+    CYGARC_HAL_SAVE_GP();
+
+    cyg_drv_interrupt_acknowledge(chan->isr_vector);
+
+    *__ctrlc = 0;
+    HAL_READ_UINT8(chan->base+CYG_DEV_LSR, lsr);
+    if ( (lsr & SIO_LSR_DR) != 0 ) {
+
+        HAL_READ_UINT8(chan->base+CYG_DEV_RBR, c);
+        if( cyg_hal_is_break( &c , 1 ) )
+            *__ctrlc = 1;
+
+        res = CYG_ISR_HANDLED;
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static void
+cyg_hal_plf_serial_init(void)
+{
+    hal_virtual_comm_table_t* comm;
+    int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+    // Disable interrupts.
+    HAL_INTERRUPT_MASK(pid_ser_channels[0].isr_vector);
+    HAL_INTERRUPT_MASK(pid_ser_channels[1].isr_vector);
+
+    // Init channels
+    cyg_hal_plf_serial_init_channel(&pid_ser_channels[0]);
+    cyg_hal_plf_serial_init_channel(&pid_ser_channels[1]);
+
+    // Setup procs in the vector table
+
+    // Set channel 0
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
+    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+    CYGACC_COMM_IF_CH_DATA_SET(*comm, &pid_ser_channels[0]);
+    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+
+    // Set channel 1
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
+    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+    CYGACC_COMM_IF_CH_DATA_SET(*comm, &pid_ser_channels[1]);
+    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+void
+cyg_hal_plf_comms_init(void)
+{
+    static int initialized = 0;
+
+    if (initialized)
+        return;
+
+    initialized = 1;
+
+    cyg_hal_plf_serial_init();
+}
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGPRI_HAL_IMPLEMENTS_IF_SERVICES
+
+/*---------------------------------------------------------------------------*/
+
+#ifdef CYGHWR_HAL_ARM_PID_DIAG_LEDS
+// Control the LEDs PP0-PP3. This requires the jumpers on pins 9-16 to
+// be set on LK11, thus preventing the use of the parallel port.
+
+#define CYG_DEVICE_PARALLEL_DATA 0x0d800040
+
+void
+hal_diag_led(int n)
+{
+    HAL_WRITE_UINT8(CYG_DEVICE_PARALLEL_DATA, (n & 0xf) << 4);
+}
+#endif // CYGHWR_HAL_ARM_PID_DIAG_LEDS
+
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#include <cyg/hal/hal_stub.h>           // cyg_hal_gdb_interrupt
+#endif
+
+#if CYGHWR_HAL_ARM_PID_DIAG_PORT==0
+// This is the base address of the A-channel
+#define CYG_DEV_SERIAL_BASE      0x0D800000
+#define CYG_DEVICE_SERIAL_INT    CYGNUM_HAL_INTERRUPT_SERIALA
+#else
+// This is the base address of the B-channel
+#define CYG_DEV_SERIAL_BASE      0x0D800020
+#define CYG_DEVICE_SERIAL_INT    CYGNUM_HAL_INTERRUPT_SERIALB
+#endif
+
+static channel_data_t pid_ser_channel = {
+    (cyg_uint8*)CYG_DEV_SERIAL_BASE, 0, 0 
+};
+
+// Assumption: all diagnostic output must be GDB packetized unless this is a ROM (i.e.
+// totally stand-alone) system.
+
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL)
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+#ifndef HAL_DIAG_USES_HARDWARE
+#if (CYGHWR_HAL_ARM_PID_DIAG_PORT != CYGHWR_HAL_ARM_PID_GDB_PORT)
+#define HAL_DIAG_USES_HARDWARE
+#endif
+#endif
 
 #ifdef HAL_DIAG_USES_HARDWARE
 
@@ -175,24 +447,12 @@ void hal_diag_init(void)
 {
     static int init = 0;
     char *msg = "\n\rARM eCos\n\r";
-    cyg_uint8 lcr;
 
     if (init++) return;
-    // 8-1-no parity.
-    HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR,
-                     SIO_LCR_WLS0 | SIO_LCR_WLS1);
 
-    HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR, lcr);
-    lcr |= SIO_LCR_DLAB;
-    HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR, lcr);
-    HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_DLL,
-                     CYG_DEVICE_SERIAL_RS232_BAUD_LSB);
-    HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_DLM,
-                     CYG_DEVICE_SERIAL_RS232_BAUD_MSB);
-    lcr &= ~SIO_LCR_DLAB;
-    HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR, lcr);
-    HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_FCR, 0x07);  // Enable & clear FIFO
-    while (*msg) hal_diag_write_char(*msg++);
+    cyg_hal_plf_serial_init_channel(&pid_ser_channel);
+
+    while (*msg) cyg_hal_plf_serial_putc(&pid_ser_channel, *msg++);
 }
 
 #ifdef DEBUG_DIAG
@@ -207,14 +467,10 @@ static int diag_bp = 0;
 
 void hal_diag_write_char(char c)
 {
-    cyg_uint8 lsr;
+    hal_diag_init();
 
-    hal_diag_init();
-    do {
-        HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LSR, lsr);
-    } while ((lsr & SIO_LSR_THRE) == 0);
+    cyg_hal_plf_serial_putc(&pid_ser_channel, c);
 
-    HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_THR, c);
 #ifdef DEBUG_DIAG
     diag_buffer[diag_bp++] = c;
     if (diag_bp == DIAG_BUFSIZE) diag_bp = 0;
@@ -223,13 +479,7 @@ void hal_diag_write_char(char c)
 
 void hal_diag_read_char(char *c)
 {
-    cyg_uint8 lsr;
-
-    do {
-        HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LSR, lsr);
-    } while ((lsr & SIO_LSR_DR) == 0);
-
-    HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_RBR, *c);
+    *c = cyg_hal_plf_serial_getc(&pid_ser_channel);
 }
 
 #else // HAL_DIAG relies on GDB
@@ -237,37 +487,25 @@ void hal_diag_read_char(char *c)
 // Initialize diag port - assume GDB channel is already set up
 void hal_diag_init(void)
 {
+    if (0) cyg_hal_plf_serial_init_channel(&pid_ser_channel); // avoid warning
 }
 
 // Actually send character down the wire
 static void
 hal_diag_write_char_serial(char c)
 {
-    cyg_uint8 lsr;
+    hal_diag_init();
 
-    hal_diag_init();
-    do {
-        HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LSR, lsr);
-    } while ((lsr & SIO_LSR_THRE) == 0);
-
-    HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_THR, c);
-    HAL_IO_BARRIER ();
+    cyg_hal_plf_serial_putc(&pid_ser_channel, c);
 }
 
 static bool
 hal_diag_read_serial(char *c)
 {
     long timeout = 1000000000;  // A long time...
-    cyg_uint8 lsr;
+    while (!cyg_hal_plf_serial_getc_nonblock(&pid_ser_channel, c))
+        if (0 == --timeout) return false;
 
-    do {
-        HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LSR, lsr);
-        if (--timeout == 0) return false;
-    } while ((lsr & SIO_LSR_DR) == 0);
-    HAL_IO_BARRIER ();                  // Prevent RBR preload.
-
-    HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_RBR, *c);
-    HAL_IO_BARRIER ();
     return true;
 }
 
@@ -360,19 +598,7 @@ hal_diag_write_char(char c)
 }
 #endif
 
-/*---------------------------------------------------------------------------*/
-
-#ifdef CYGHWR_HAL_ARM_PID_DIAG_LEDS
-// Control the LEDs PP0-PP3. This requires the jumpers on pins 9-16 to
-// be set on LK11, thus preventing the use of the parallel port.
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
-#define CYG_DEVICE_PARALLEL_DATA 0x0d800040
-
-void
-hal_diag_led(int n)
-{
-    HAL_WRITE_UINT8(CYG_DEVICE_PARALLEL_DATA, (n & 0xf) << 4);
-}
-#endif // CYGHWR_HAL_ARM_PID_DIAG_LEDS
 /*---------------------------------------------------------------------------*/
 /* End of hal_diag.c */
diff --git a/packages/hal/arm/pid/current/src/pid_misc.c b/packages/hal/arm/pid/current/src/pid_misc.c
--- a/packages/hal/arm/pid/current/src/pid_misc.c
+++ b/packages/hal/arm/pid/current/src/pid_misc.c
@@ -51,6 +51,7 @@
 #include <cyg/hal/hal_arch.h>           // Register state info
 #include <cyg/hal/hal_diag.h>
 #include <cyg/hal/hal_intr.h>           // necessary?
+#include <cyg/hal/hal_if.h>             // calling interface
 
 /*------------------------------------------------------------------------*/
 // On-board timer
@@ -131,6 +132,9 @@ void hal_hardware_init(void)
     // Any hardware/platform initialization that needs to be done.
     HAL_WRITE_UINT32(CYG_DEVICE_IRQ_EnableClear, 0xFFFF); // Clear all
                                                          // interrupt sources
+
+    // Set up eCos/ROM interfaces
+    hal_if_init();
 }
 
 //
diff --git a/packages/hal/arm/sa11x0/assabet/current/ChangeLog b/packages/hal/arm/sa11x0/assabet/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/assabet/current/ChangeLog
@@ -0,0 +1,115 @@
+2000-06-27  Jesper Skov  <jskov@redhat.com>
+
+	* cdl/hal_arm_sa11x0_assabet.cdl: Changed PORT values.
+
+2000-06-26  Jesper Skov  <jskov@redhat.com>
+
+	* include/hal_platform_ints.h: Removed Ctrl-c handling.
+
+	* cdl/hal_arm_sa11x0_assabet.cdl: Removed ROM_DEBUG_CHANNEL option.
+
+2000-06-19  Gary Thomas  <gthomas@redhat.com>
+
+	* cdl/hal_arm_sa11x0_assabet.cdl: Adding virtual vector support.
+
+	* include/assabet.h: Adding LCD registers.  Update BCR register.
+
+	* include/hal_platform_ints.h: Changes for virtual vector support.
+
+	* include/hal_platform_setup.h: Updated vectors - fixed stuff
+	now handled elsewhere.
+
+	* misc/cf_test.c: New program to experiment with Compact Flash
+	interface(s).
+
+	* src/assabet_misc.c (plf_hardware_init): Added new function
+	to perform platform specific initializations.
+
+2000-06-18  Gary Thomas  <gthomas@redhat.com>
+
+	* include/pkgconf/mlt_arm_sa11x0_assabet_ram.mlt: 
+	* include/pkgconf/mlt_arm_sa11x0_assabet_rom.ldi: 
+	* include/pkgconf/mlt_arm_sa11x0_assabet_ram.ldi: 
+	* include/pkgconf/mlt_arm_sa11x0_assabet_rom.mlt: 
+	Incorporate new fixed vectors (used on all ARM platforms).
+
+2000-06-05  Gary Thomas  <gthomas@redhat.com>
+
+	* src/assabet_misc.c (assabet_BCR): New function used to 
+	safely manipulate the board control register (write only).
+
+	* include/assabet.h: Flush out board control register.
+
+	* include/hal_platform_ints.h: Add missing GPIO interrupts.
+
+2000-06-04  Gary Thomas  <gthomas@redhat.com>
+
+	* include/hal_platform_setup.h: 
+	* src/assabet_misc.c: 'sa1100' stuff renamed to 'sa11x0'.
+
+	* include/hal_platform_setup.h: Set power supply to full on.  Move
+	board control stuff to <hal/assabet.h>.  Also define "fixed" vectors
+	which will contain board control shadow and other items potentially
+	shared by stubs, CygMon, etc.
+
+	* cdl/hal_arm_sa11x0_assabet.cdl: Update build options for GDB stubs.
+	Necessary when 'fixed_vectors' are present.
+
+	* include/pkgconf/mlt_arm_sa11x0_assabet_rom.mlt: 
+	* include/pkgconf/mlt_arm_sa11x0_assabet_rom.h: 
+	* include/pkgconf/mlt_arm_sa11x0_assabet_rom.ldi: 
+	* include/pkgconf/mlt_arm_sa11x0_assabet_ram.mlt: 
+	* include/pkgconf/mlt_arm_sa11x0_assabet_ram.h: 
+	* include/pkgconf/mlt_arm_sa11x0_assabet_ram.ldi: Improve layout to
+	match real hardware.  Add 'fixed_vectors' at 0x40.
+
+2000-06-01  Gary Thomas  <gthomas@redhat.com>
+
+	* cdl/hal_arm_sa11x0_assabet.cdl: 
+	* include/hal_platform_setup.h: Add ROM startup code.
+
+	* src/assabet_misc.c: New file.
+
+2000-05-12  John Dallaway  <jld@redhat.com>
+
+	* cdl/hal_arm_sa11x0_assabet.cdl:
+
+	Fix calculation of CYGHWR_MEMORY_LAYOUT.
+
+2000-05-10  Gary Thomas  <gthomas@redhat.com>
+
+	* current/include/pkgconf/mlt_arm_sa11x0_assabet_ram.mlt: 
+	* current/include/pkgconf/mlt_arm_sa11x0_assabet_rom.h: 
+	* current/include/pkgconf/mlt_arm_sa11x0_assabet_rom.ldi: 
+	* current/include/pkgconf/mlt_arm_sa11x0_assabet_ram.h: 
+	* current/include/pkgconf/mlt_arm_sa11x0_assabet_ram.ldi: 
+	* current/include/pkgconf/mlt_arm_sa11x0_assabet_rom.mlt: 
+	* current/include/hal_platform_ints.h: 
+	* current/include/hal_platform_setup.h: 
+	* current/cdl/hal_arm_sa11x0_assabet.cdl: New file(s).
+
+//===========================================================================
+//####COPYRIGHTBEGIN####
+//                                                                          
+// -------------------------------------------                              
+// The contents of this file are subject to the Red Hat eCos Public License 
+// Version 1.1 (the "License"); you may not use this file except in         
+// compliance with the License.  You may obtain a copy of the License at    
+// http://www.redhat.com/                                                   
+//                                                                          
+// Software distributed under the License is distributed on an "AS IS"      
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+// License for the specific language governing rights and limitations under 
+// the License.                                                             
+//                                                                          
+// The Original Code is eCos - Embedded Configurable Operating System,      
+// released September 30, 1998.                                             
+//                                                                          
+// The Initial Developer of the Original Code is Red Hat.                   
+// Portions created by Red Hat are                                          
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+// All Rights Reserved.                                                     
+// -------------------------------------------                              
+//                                                                          
+//####COPYRIGHTEND####
+//===========================================================================
diff --git a/packages/hal/arm/sa11x0/assabet/current/cdl/hal_arm_sa11x0_assabet.cdl b/packages/hal/arm/sa11x0/assabet/current/cdl/hal_arm_sa11x0_assabet.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/assabet/current/cdl/hal_arm_sa11x0_assabet.cdl
@@ -0,0 +1,324 @@
+# ====================================================================
+#
+#      hal_arm_sa11x0_assabet.cdl
+#
+#      ARM SA1110/Assabet platform HAL package configuration data
+#
+# ====================================================================
+#####COPYRIGHTBEGIN####
+#                                                                          
+# -------------------------------------------                              
+# The contents of this file are subject to the Red Hat eCos Public License 
+# Version 1.1 (the "License"); you may not use this file except in         
+# compliance with the License.  You may obtain a copy of the License at    
+# http://www.redhat.com/                                                   
+#                                                                          
+# Software distributed under the License is distributed on an "AS IS"      
+# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+# License for the specific language governing rights and limitations under 
+# the License.                                                             
+#                                                                          
+# The Original Code is eCos - Embedded Configurable Operating System,      
+# released September 30, 1998.                                             
+#                                                                          
+# The Initial Developer of the Original Code is Red Hat.                   
+# Portions created by Red Hat are                                          
+# Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+# All Rights Reserved.                                                     
+# -------------------------------------------                              
+#                                                                          
+#####COPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      gthomas
+# Original data:  gthomas
+# Contributors:
+# Date:           2000-05-08
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+cdl_package CYGPKG_HAL_ARM_SA11X0_ASSABET {
+    display       "ARM SA1110/Assabet evaluation board"
+    parent        CYGPKG_HAL_ARM_SA11X0
+    hardware
+    include_dir   cyg/hal
+    define_header hal_arm_sa11x0_assabet.h
+    description   "
+        This HAL platform package provides generic
+        support for the Intel StrongARM SA1110 based evalation board, 
+	known as 'assabet'."
+
+    compile       assabet_misc.c
+
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_GUARANTEED
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_arm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_arm_sa11x0.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_sa11x0_assabet.h>"
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value {"RAM"}
+        legal_values  {"RAM" "ROM"}
+	no_define
+	define -file system.h CYG_HAL_STARTUP
+        description   "
+           When targetting the Assabet eval board it is possible to build
+           the system for either RAM bootstrap or ROM bootstrap(s). Select
+           'ram' when building programs to load into RAM using eCos GDB
+           stubs.  Select 'rom' when building a stand-alone application
+           which will be put into ROM, or for the special case of
+           building the eCos GDB stubs themselves."
+    }
+
+    # Assabet board has only 1 serial port useable for diagnostic/GDB
+##    define CYGHWR_HAL_ARM_SA11X0_DIAG_PORT 1
+# FIXME - make this fixed.
+    cdl_option CYGHWR_HAL_ARM_SA11X0_DIAG_PORT {
+        display       "Diagnostic serial port"
+        flavor        data
+        legal_values  0 0
+        default_value 0
+        description   "
+            The Assabet evaluation boards has only one serial port."
+    }
+
+    cdl_option CYGHWR_HAL_ARM_SA11X0_DIAG_BAUD {
+        display       "Diagnostic serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 115200
+        default_value 38400
+        description   "
+            This option selects the baud rate used for the diagnostic port.
+            Note: this should match the value chosen for the GDB port if the
+            diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGHWR_HAL_ARM_SA11X0_GDB_PORT {
+        display       "GDB serial port"
+        flavor        data
+        legal_values  0 0
+        default_value 0
+        description   "
+            The Assabet evaluation boards has only one serial port."
+    }
+
+    cdl_option CYGHWR_HAL_ARM_SA11X0_GDB_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 115200
+        default_value 38400
+        description   "
+            This option selects the baud rate used for the diagnostic port.
+            Note: this should match the value chosen for the GDB port if the
+            diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        calculated   1
+    }
+ 
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The assabet board has only one serial port. This option
+            chooses which port will be used to connect to a host
+            running GDB."
+     }
+ 
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display          "Diagnostic serial port"
+         flavor data
+         legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+         default_value    0
+         description      "
+            The assabet board has only one serial port.  This option
+            chooses which port will be used for diagnostic output."
+     }
+ 
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        no_define
+        description   "
+	    Global build options including control over
+	    compiler flags, linker flags and choice of toolchain."
+
+
+        parent  CYGPKG_NONE
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-elf" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=strongarm1100 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-Wl,--gc-sections -Wl,-static -Wl,-N -g -O2 -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+
+        cdl_option CYGBLD_BUILD_GDB_STUBS {
+            display "Build GDB stub ROM image"
+            default_value 0
+            requires { CYG_HAL_STARTUP == "ROM" }
+            requires CYGSEM_HAL_ROM_MONITOR
+            requires CYGBLD_BUILD_COMMON_GDB_STUBS
+            requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+            requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+            requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+            requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+            requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+            no_define
+            description "
+                This option enables the building of the GDB stubs for the
+                board. The common HAL controls takes care of most of the
+                build process, but the final conversion from ELF image to
+                binary data is handled by the platform CDL, allowing
+                relocation of the data if necessary."
+
+            make -priority 320 {
+                <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
+                $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@
+            }
+        }
+    }
+
+    cdl_component CYGPKG_HAL_ARM_SA11X0_ASSABET_OPTIONS {
+        display "StrongARM SA1110/ASSABET build options"
+        flavor  none
+        no_define
+        description   "
+	    Package specific build options including control over
+	    compiler flags used only in building this package,
+	    and details of which tests are built."
+
+
+        cdl_option CYGPKG_HAL_ARM_SA11X0_ASSABET_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the StrongARM Assabet HAL. These flags are used in addition
+                to the set of global flags."
+        }
+
+        cdl_option CYGPKG_HAL_ARM_SA11X0_ASSABET_CFLAGS_REMOVE {
+            display "Supressed compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the StrongARM Assabet HAL. These flags are removed from
+                the set of global flags if present."
+        }
+
+        cdl_option CYGPKG_HAL_ARM_SA11X0_ASSABET_TESTS {
+            display "StrongARM SA1110/Assabet tests"
+            flavor  data
+            no_define
+#            calculated { "tests/dram-test" }
+            calculated { "" }
+            description   "
+                This option specifies the set of tests for the StrongARM Assabet HAL."
+        }
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        calculated { CYG_HAL_STARTUP == "RAM" ? "arm_sa11x0_assabet_ram" : \
+	                                        "arm_sa11x0_assabet_rom" }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display "Memory layout linker script fragment"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+            calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_sa11x0_assabet_ram.ldi>" : \
+                                                    "<pkgconf/mlt_arm_sa11x0_assabet_rom.ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display "Memory layout header file"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+            calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_sa11x0_assabet_ram.h>" : \
+                                                    "<pkgconf/mlt_arm_sa11x0_assabet_rom.h>" }
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+         display       "Work with a ROM monitor"
+         flavor        booldata
+         legal_values  { "Generic" "GDB_stubs" }
+         default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+         parent        CYGPKG_HAL_ROM_MONITOR
+         requires      { CYG_HAL_STARTUP == "RAM" }
+         description   "
+             Support can be enabled for different varieties of ROM monitor.
+             This support changes various eCos semantics such as the encoding
+             of diagnostic output, or the overriding of hardware interrupt
+             vectors.
+             Firstly there is \"Generic\" support which prevents the HAL
+             from overriding the hardware vectors that it does not use, to
+             instead allow an installed ROM monitor to handle them. This is
+             the most basic support which is likely to be common to most
+             implementations of ROM monitor.
+             \"GDB_stubs\" provides support when GDB stubs are included in
+             the ROM monitor or boot ROM."
+     }
+
+}
diff --git a/packages/hal/arm/sa11x0/assabet/current/include/assabet.h b/packages/hal/arm/sa11x0/assabet/current/include/assabet.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/assabet/current/include/assabet.h
@@ -0,0 +1,143 @@
+#ifndef CYGONCE_ASSABET_H
+#define CYGONCE_ASSABET_H
+
+/*=============================================================================
+//
+//      assabet.h
+//
+//      Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####COPYRIGHTBEGIN####
+//                                                                          
+// -------------------------------------------                              
+// The contents of this file are subject to the Red Hat eCos Public License 
+// Version 1.1 (the "License"); you may not use this file except in         
+// compliance with the License.  You may obtain a copy of the License at    
+// http://www.redhat.com/                                                   
+//                                                                          
+// Software distributed under the License is distributed on an "AS IS"      
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+// License for the specific language governing rights and limitations under 
+// the License.                                                             
+//                                                                          
+// The Original Code is eCos - Embedded Configurable Operating System,      
+// released September 30, 1998.                                             
+//                                                                          
+// The Initial Developer of the Original Code is Red Hat.                   
+// Portions created by Red Hat are                                          
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+// All Rights Reserved.                                                     
+// -------------------------------------------                              
+//                                                                          
+//####COPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+// Date:         2000-05-08
+// Purpose:      Intel SA1110/Assabet platform specific support routines
+// Description: 
+// Usage:        #include <cyg/hal/assabet.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+
+#ifndef __ASSEMBLER__
+//
+// Board Control Register
+// Note: This register is write-only.  Thus a shadow copy is provided so that
+// it may be safely updated/shared by multiple threads.
+//
+extern unsigned long _assabet_BCR;  // Shadow copy
+
+extern void assabet_BCR(unsigned long mask, unsigned long value);
+
+//
+// Board Configuration data - read at RESET
+//
+extern unsigned long _assabet_CFG;
+#endif
+
+// 
+// Signal assertion levels
+//
+#define SA1110_LOGIC_ONE(m)  (m & 0xFFFFFFFF)
+#define SA1110_LOGIC_ZERO(m) (m & 0x00000000)
+
+//
+// SA1110/Assabet Board Control Register
+//
+#define SA1110_BOARD_CONTROL        REG32_PTR(0x12000000)
+#define SA1110_BCR_MIN              0x00A014E4     // Reset state
+
+#define SA1110_BCR_CF_POWER         0x00000001     // 1 = CompactFlash power on
+#define SA1110_BCR_CF_POWER_ON      SA1110_LOGIC_ONE(SA1110_BCR_CF_POWER)
+#define SA1110_BCR_CF_POWER_OFF     SA1110_LOGIC_ZERO(SA1110_BCR_CF_POWER)
+#define SA1110_BCR_CF_RESET         0x00000002     // 1 = CompactFlash reset
+#define SA1110_BCR_CF_RESET_ENABLE  SA1110_LOGIC_ONE(SA1110_BCR_CF_RESET)
+#define SA1110_BCR_CF_RESET_DISABLE SA1110_LOGIC_ZERO(SA1110_BCR_CF_RESET)
+#define SA1110_BCR_SOFT_RESET       0x00000004     // 0 = resets UCB1300, ADI7171, UDA1341
+#define SA1110_BCR_IRDA_FREQ        0x00000008     // 0 = SIR, 1 = MIR/FIR
+#define SA1110_BCR_IRDA_MD          0x00000030     // IrDA Mode & range
+#define SA1110_BCR_IRDA_MD_MAX      0x00000000     // Max range and power
+#define SA1110_BCR_IRDA_MD_OFF      0x00000010     // Shutdown
+#define SA1110_BCR_IRDA_MD_23       0x00000020     // 2/3 power
+#define SA1110_BCR_IRDA_MD_13       0x00000030     // 1/3 power
+#define SA1110_BCR_STEREO_LB        0x00000040     // 1 = Stereo loopback on
+#define SA1110_BCR_CF_BUS           0x00000080     // 0 = CompactFlash bus on
+#define SA1110_BCR_CF_BUS_ON        SA1110_LOGIC_ZERO(SA1110_BCR_CF_BUS)
+#define SA1110_BCR_CF_BUS_OFF       SA1110_LOGIC_ONE(SA1110_BCR_CF_BUS)
+#define SA1110_BCR_AUDIO_ON         0x00000100     // 1 = UDA1341, MIC, DAA power on
+#define SA1110_BCR_BACKLIGHT        0x00000200     // 1 = LCD backlight on
+#define SA1110_BCR_LCD_BPP          0x00000400     // 0 = 16 RGB, 1 = 12 RGB
+#define SA1110_BCR_LCD_16BPP        SA1110_LOGIC_ZERO(SA1110_BCR_LCD_BPP)
+#define SA1110_BCR_LCD_12BPP        SA1110_LOGIC_ONE(SA1110_BCR_LCD_BPP)
+#define SA1110_BCR_LCD              0x00000800     // 1 = LCD panel and controller on
+#define SA1110_BCR_LCD_ON           SA1110_LOGIC_ONE(SA1110_BCR_LCD)
+#define SA1110_BCR_LCD_OFF          SA1110_LOGIC_ZERO(SA1110_BCR_LCD)
+#define SA1110_BCR_RS232_ENABLE     0x00001000     // 1 = Enable RD232 signals
+#define SA1110_BCR_RED_LED          0x00002000     // 0 = Red LED on
+#define SA1110_BCR_RED_LED_ON       SA1110_LOGIC_ZERO(SA1110_BCR_RED_LED)
+#define SA1110_BCR_RED_LED_OFF      SA1110_LOGIC_ONE(SA1110_BCR_RED_LED)
+#define SA1110_BCR_GREEN_LED        0x00004000     // 0 = Green LED on
+#define SA1110_BCR_GREEN_LED_ON     SA1110_LOGIC_ZERO(SA1110_BCR_GREEN_LED)
+#define SA1110_BCR_GREEN_LED_OFF    SA1110_LOGIC_ONE(SA1110_BCR_GREEN_LED)
+#define SA1110_BCR_MOTOR            0x00008000     // 1 = Vibrator motor on
+#define SA1110_BCR_COM_DTR          0x00010000     // COM port Data Terminal Ready
+#define SA1110_BCR_COM_RTS          0x00020000     // COM port Request To Send
+#define SA1110_BCR_RADIO_WAKE       0x00040000     // 1 = Wake up CPU with radio
+#define SA1110_BCR_MUTE             0x00200000     // 1 = Audio muted
+
+//
+// Special purpose GPIO interrupt mappings
+//
+#define SA1110_CF_IRQ               CYGNUM_HAL_INTERRUPT_GPIO21
+#define SA1110_CF_DETECT            CYGNUM_HAL_INTERRUPT_GPIO22
+
+//
+// GPIO layout
+//
+#define SA1110_GPIO_CF_DETECT       0x00400000     // 0 = Compact Flash detect
+#define SA1110_GPIO_CF_PRESENT      SA1110_LOGIC_ZERO(SA1110_GPIO_CF_DETECT)
+#define SA1110_GPIO_CF_ABSENT       SA1110_LOGIC_ONE(SA1110_GPIO_CF_DETECT)
+
+//
+// LCD Controller
+//
+#define SA1110_LCCR0                SA11X0_REGISTER(0x30100000)
+#define SA1110_LCSR                 SA11X0_REGISTER(0x30100004)
+#define SA1110_DBAR1                SA11X0_REGISTER(0x30100010)
+#define SA1110_DCAR1                SA11X0_REGISTER(0x30100014)
+#define SA1110_DBAR2                SA11X0_REGISTER(0x30100018)
+#define SA1110_DCAR2                SA11X0_REGISTER(0x3010001C)
+#define SA1110_LCCR1                SA11X0_REGISTER(0x30100020)
+#define SA1110_LCCR2                SA11X0_REGISTER(0x30100024)
+#define SA1110_LCCR3                SA11X0_REGISTER(0x30100028)
+
+/*---------------------------------------------------------------------------*/
+/* end of assabet.h                                                          */
+#endif /* CYGONCE_ASSABET_H */
diff --git a/packages/hal/arm/sa11x0/assabet/current/include/hal_platform_ints.h b/packages/hal/arm/sa11x0/assabet/current/include/hal_platform_ints.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/assabet/current/include/hal_platform_ints.h
@@ -0,0 +1,108 @@
+#ifndef CYGONCE_HAL_PLATFORM_INTS_H
+#define CYGONCE_HAL_PLATFORM_INTS_H
+//==========================================================================
+//
+//      hal_platform_ints.h
+//
+//      HAL Interrupt and clock support
+//
+//==========================================================================
+//####COPYRIGHTBEGIN####
+//                                                                          
+// -------------------------------------------                              
+// The contents of this file are subject to the Red Hat eCos Public License 
+// Version 1.1 (the "License"); you may not use this file except in         
+// compliance with the License.  You may obtain a copy of the License at    
+// http://www.redhat.com/                                                   
+//                                                                          
+// Software distributed under the License is distributed on an "AS IS"      
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+// License for the specific language governing rights and limitations under 
+// the License.                                                             
+//                                                                          
+// The Original Code is eCos - Embedded Configurable Operating System,      
+// released September 30, 1998.                                             
+//                                                                          
+// The Initial Developer of the Original Code is Red Hat.                   
+// Portions created by Red Hat are                                          
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+// All Rights Reserved.                                                     
+// -------------------------------------------                              
+//                                                                          
+//####COPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+// Date:         2000-05-08
+// Purpose:      Define Interrupt support
+// Description:  The interrupt details for the SA1110/Assabet are defined here.
+// Usage:
+//               #include <cyg/hal/hal_platform_ints.h>
+//               ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#define CYGNUM_HAL_INTERRUPT_GPIO0   0
+#define CYGNUM_HAL_INTERRUPT_GPIO1   1
+#define CYGNUM_HAL_INTERRUPT_GPIO2   2
+#define CYGNUM_HAL_INTERRUPT_GPIO3   3
+#define CYGNUM_HAL_INTERRUPT_GPIO4   4
+#define CYGNUM_HAL_INTERRUPT_GPIO5   5
+#define CYGNUM_HAL_INTERRUPT_GPIO6   6
+#define CYGNUM_HAL_INTERRUPT_GPIO7   7
+#define CYGNUM_HAL_INTERRUPT_GPIO8   8
+#define CYGNUM_HAL_INTERRUPT_GPIO9   9
+#define CYGNUM_HAL_INTERRUPT_GPIO10  10
+#define CYGNUM_HAL_INTERRUPT_GPIO    11  // Don't use directly!
+#define CYGNUM_HAL_INTERRUPT_LCD     12
+#define CYGNUM_HAL_INTERRUPT_UDC     13
+#define CYGNUM_HAL_INTERRUPT_UART1   15
+#define CYGNUM_HAL_INTERRUPT_UART2   16
+#define CYGNUM_HAL_INTERRUPT_UART3   17
+#define CYGNUM_HAL_INTERRUPT_MCP     18
+#define CYGNUM_HAL_INTERRUPT_SSP     19
+#define CYGNUM_HAL_INTERRUPT_TIMER0  26
+#define CYGNUM_HAL_INTERRUPT_TIMER1  27
+#define CYGNUM_HAL_INTERRUPT_TIMER2  28
+#define CYGNUM_HAL_INTERRUPT_TIMER3  29
+#define CYGNUM_HAL_INTERRUPT_HZ      30
+#define CYGNUM_HAL_INTERRUPT_ALARM   31
+
+// GPIO bits 31..11 can generate interrupts as well, but they all
+// end up clumped into interrupt signal #11.  Using the symbols
+// below allow for detection of these separately.
+
+#define CYGNUM_HAL_INTERRUPT_GPIO11  (32+11)
+#define CYGNUM_HAL_INTERRUPT_GPIO12  (32+12)
+#define CYGNUM_HAL_INTERRUPT_GPIO13  (32+13)
+#define CYGNUM_HAL_INTERRUPT_GPIO14  (32+14)
+#define CYGNUM_HAL_INTERRUPT_GPIO15  (32+15)
+#define CYGNUM_HAL_INTERRUPT_GPIO16  (32+16)
+#define CYGNUM_HAL_INTERRUPT_GPIO17  (32+17)
+#define CYGNUM_HAL_INTERRUPT_GPIO18  (32+18)
+#define CYGNUM_HAL_INTERRUPT_GPIO19  (32+19)
+#define CYGNUM_HAL_INTERRUPT_GPIO20  (32+20)
+#define CYGNUM_HAL_INTERRUPT_GPIO21  (32+21)
+#define CYGNUM_HAL_INTERRUPT_GPIO22  (32+22)
+#define CYGNUM_HAL_INTERRUPT_GPIO23  (32+23)
+#define CYGNUM_HAL_INTERRUPT_GPIO24  (32+24)
+#define CYGNUM_HAL_INTERRUPT_GPIO25  (32+25)
+#define CYGNUM_HAL_INTERRUPT_GPIO26  (32+26)
+#define CYGNUM_HAL_INTERRUPT_GPIO27  (32+27)
+
+#define CYGNUM_HAL_INTERRUPT_NONE    -1
+
+#define CYGNUM_HAL_ISR_MIN            0
+#define CYGNUM_HAL_ISR_MAX           (27+32)
+
+#define CYGNUM_HAL_ISR_COUNT            (CYGNUM_HAL_ISR_MAX+1)
+
+// The vector used by the Real time clock
+#define CYGNUM_HAL_INTERRUPT_RTC        CYGNUM_HAL_INTERRUPT_TIMER0
+
+#endif // CYGONCE_HAL_PLATFORM_INTS_H
diff --git a/packages/hal/arm/sa11x0/assabet/current/include/hal_platform_setup.h b/packages/hal/arm/sa11x0/assabet/current/include/hal_platform_setup.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/assabet/current/include/hal_platform_setup.h
@@ -0,0 +1,271 @@
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+
+/*=============================================================================
+//
+//      hal_platform_setup.h
+//
+//      Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+//####COPYRIGHTBEGIN####
+//                                                                          
+// -------------------------------------------                              
+// The contents of this file are subject to the Red Hat eCos Public License 
+// Version 1.1 (the "License"); you may not use this file except in         
+// compliance with the License.  You may obtain a copy of the License at    
+// http://www.redhat.com/                                                   
+//                                                                          
+// Software distributed under the License is distributed on an "AS IS"      
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+// License for the specific language governing rights and limitations under 
+// the License.                                                             
+//                                                                          
+// The Original Code is eCos - Embedded Configurable Operating System,      
+// released September 30, 1998.                                             
+//                                                                          
+// The Initial Developer of the Original Code is Red Hat.                   
+// Portions created by Red Hat are                                          
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+// All Rights Reserved.                                                     
+// -------------------------------------------                              
+//                                                                          
+//####COPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+// Date:         2000-05-08
+// Purpose:      Intel SA1110/Assabet platform specific support routines
+// Description: 
+// Usage:        #include <cyg/hal/hal_platform_setup.h>
+//     Only used by "vectors.S"         
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/system.h>             // System-wide configuration info
+#include CYGBLD_HAL_VARIANT_H           // Variant (SA11x0) specific configuration
+#include CYGBLD_HAL_PLATFORM_H          // Platform specific configuration
+#include <cyg/hal/hal_sa11x0.h>         // Variant specific hardware definitions
+#include <cyg/hal/hal_mmu.h>            // MMU definitions
+#include <cyg/hal/assabet.h>            // Platform specific hardware definitions
+
+#if defined(CYG_HAL_STARTUP_ROM)
+#define PLATFORM_SETUP1 _platform_setup1
+#define CYGHWR_HAL_ARM_HAS_MMU
+
+#if (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 59000)
+#define SA11X0_PLL_CLOCK 0x0        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 73700)
+#define SA11X0_PLL_CLOCK 0x1
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 88500)
+#define SA11X0_PLL_CLOCK 0x2        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 103200) 
+#define SA11X0_PLL_CLOCK 0x3        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 118000)
+#define SA11X0_PLL_CLOCK 0x4        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 132700)
+#define SA11X0_PLL_CLOCK 0x5        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 147500)
+#define SA11X0_PLL_CLOCK 0x6        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 162200)
+#define SA11X0_PLL_CLOCK 0x7        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 176900)
+#define SA11X0_PLL_CLOCK 0x8        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 191700)
+#define SA11X0_PLL_CLOCK 0x9        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 206400)
+#define SA11X0_PLL_CLOCK 0xA        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 221200)
+#define SA11X0_PLL_CLOCK 0xB        
+#else
+#error Invalid processor clock speed
+#endif                
+        
+        
+// This macro represents the initial startup code for the platform        
+        .macro  _platform_setup1
+
+        // Turn off LEDs
+        ldr     r1,=SA1110_BOARD_CONTROL
+        ldr     r2,=SA1110_BCR_MIN
+        orr     r2,r2,#SA1110_BCR_RED_LED
+        orr     r2,r2,#SA1110_BCR_GREEN_LED
+        str     r2,[r1]
+
+        // Set up GPIO to read hardware configuration
+        ldr     r1,=SA11X0_GPIO_PIN_DIRECTION
+        ldr     r2,=0x0807A7FC
+        str     r2,[r1]
+        ldr     r3,=SA11X0_GPIO_PIN_OUTPUT_SET
+        ldr     r2,=0x2FC               // Bits 2..9
+        str     r2,[r3]                 // Requests hardware configuration
+        ldr     r2,=0x0807A400          // Reconfigure 2..9 as inputs
+        str     r2,[r1]
+        ldr     r3,=SA11X0_GPIO_PIN_LEVEL
+        mov     r2,#100
+10:     ldr     r9,[r3]                 // Read multiple times to settle
+        subs    r2,r2,#1
+        bne     10b        
+        ldr     r2,=0x0807A7FC          // Restore proper pin configuration
+        str     r2,[r1]
+        ldr     r3,=SA11X0_GPIO_PIN_OUTPUT_SET
+        ldr     r2,=0x10000             // Enable high power mode
+        str     r2,[r3]
+
+        // Disable clock switching
+        mcr     p15,0,r0,\
+                SA11X0_TEST_CLOCK_AND_IDLE_REGISTER,\
+                SA11X0_DISABLE_CLOCK_SWITCHING_RM,\
+                SA11X0_DISABLE_CLOCK_SWITCHING_OPCODE
+
+        // Set up processor clock
+        ldr     r1,=SA11X0_PWR_MGR_PLL_CONFIG
+        ldr     r2,=SA11X0_PLL_CLOCK
+        str     r2,[r1]
+
+        // Turn clock switching back on
+        mcr     p15,0,r0,\
+                SA11X0_TEST_CLOCK_AND_IDLE_REGISTER,\
+                SA11X0_ENABLE_CLOCK_SWITCHING_RM,\
+                SA11X0_ENABLE_CLOCK_SWITCHING_OPCODE
+        nop
+        nop
+
+        // Turn on Red LED
+        ldr     r1,=SA1110_BOARD_CONTROL
+        ldr     r2,=SA1110_BCR_MIN
+        bic     r2,r2,#SA1110_BCR_RED_LED
+        orr     r2,r2,#SA1110_BCR_GREEN_LED
+        str     r2,[r1]
+
+        // Pause
+        ldr     r1,=100000
+10:     sub     r1,r1,#1
+        cmp     r1,#0
+        bne     10b        
+
+        // Initialize DRAM controller
+        ldr     r1,=dram_table
+        ldr     r2,=__exception_handlers
+        sub     r1,r1,r2
+        ldr     r2,[r1],#4                      // First control register
+10:     ldr     r3,[r1],#4
+        str     r3,[r2]
+        ldr     r2,[r1],#4                      // Next control register
+        cmp     r2,#0
+        bne     10b
+
+        ldr     r1,=SA1110_BOARD_CONTROL
+        ldr     r2,=SA1110_BCR_MIN
+        orr     r2,r2,#SA1110_BCR_RED_LED
+        bic     r2,r2,#SA1110_BCR_GREEN_LED
+        str     r2,[r1]
+
+        // Enable UART
+        ldr     r1,=SA1110_GPCLK_CONTROL_0
+        ldr     r2,=SA1110_GPCLK_SUS_UART
+        str     r2,[r1]
+
+        // Release DRAM hold (set by RESET)
+        ldr     r1,=SA11X0_PWR_MGR_SLEEP_STATUS
+        ldr     r2,=SA11X0_DRAM_CONTROL_HOLD
+        str     r2,[r1]
+
+        // Perform 8 reads from unmapped/unenabled DRAM
+        ldr     r1,=SA11X0_RAM_BANK0_BASE
+        ldr     r2,[r1]
+        ldr     r2,[r1]
+        ldr     r2,[r1]
+        ldr     r2,[r1]
+        ldr     r2,[r1]
+        ldr     r2,[r1]
+        ldr     r2,[r1]
+        ldr     r2,[r1]
+
+        // Enable DRAM controller
+        ldr     r1,=SA11X0_DRAM_CONFIGURATION
+        ldr     r2,=0x72547255
+        str     r2,[r1]
+
+        b       19f
+        
+// DRAM controller initialization        
+dram_table:
+        .word   SA11X0_DRAM0_CAS_0,           0xAAAAAA7F
+        .word   SA11X0_DRAM0_CAS_1,           0xAAAAAAAA
+        .word   SA11X0_DRAM0_CAS_2,           0xAAAAAAAA
+        .word   SA11X0_STATIC_CONTROL_0,      0x4B384B38
+        .word   SA11X0_STATIC_CONTROL_1,      0x22212419
+        .word   SA11X0_EXP_BUS_CONFIGURATION, 0x994A994A
+        .word   SA11X0_REFRESH_CONFIGURATION, 0x49FC0327
+        .word   SA11X0_DRAM2_CAS_0,           0xAAAAAA7F
+        .word   SA11X0_DRAM2_CAS_1,           0xAAAAAAAA
+        .word   SA11X0_DRAM2_CAS_2,           0xAAAAAAAA
+        .word   SA11X0_STATIC_CONTROL_2,      0x42194449
+        .word   SA11X0_SMROM_CONFIGURATION,   0xAFCCAFCC
+        .word   SA11X0_DRAM_CONFIGURATION,    0x72547254        // Disabled
+        .word   0, 0
+19:
+
+        // Release peripheral hold (set by RESET)
+        ldr     r1,=SA11X0_PWR_MGR_SLEEP_STATUS
+        ldr     r2,=SA11X0_PERIPHERAL_CONTROL_HOLD
+        str     r2,[r1]
+
+        // Set up a stack [for calling C code]
+        ldr     r1,=__startup_stack
+        ldr     r2,=SA11X0_RAM_BANK0_BASE
+        orr     sp,r1,r2
+
+        // Create MMU tables
+        bl      hal_mmu_init
+       
+        // Turn on green LED
+        ldr     r1,=SA1110_BOARD_CONTROL
+        ldr     r2,=SA1110_BCR_MIN
+        orr     r2,r2,#SA1110_BCR_RED_LED
+        bic     r2,r2,#SA1110_BCR_GREEN_LED
+        str     r2,[r1]
+
+        // Enable MMU
+        ldr     r2,=10f
+       	ldr	r1,=MMU_Control_Init|MMU_Control_M
+	mcr	MMU_CP,0,r1,MMU_Control,c0
+	mov	pc,r2    /* Change address spaces */
+	nop
+ 	nop
+	nop
+10:
+       
+        // Turn on both LEDs
+        ldr     r1,=SA1110_BOARD_CONTROL
+        ldr     r2,=SA1110_BCR_MIN
+        bic     r2,r2,#SA1110_BCR_RED_LED
+        bic     r2,r2,#SA1110_BCR_GREEN_LED
+        str     r2,[r1]
+
+        // Save shadow copy of BCR, also hardware configuration
+        ldr     r1,=_assabet_BCR
+        str     r2,[r1]
+        ldr     r1,=_assabet_CFG
+        str     r9,[r1]                // Saved far above...
+        .endm
+        
+#else // defined(CYG_HAL_STARTUP_ROM)
+#define PLATFORM_SETUP1
+#endif
+
+#define PLATFORM_VECTORS         _platform_vectors
+        .macro  _platform_vectors
+        .globl  _assabet_BCR, _assabet_CFG
+_assabet_BCR:   .long   0       // Board Control register shadow
+_assabet_CFG:   .long   0       // Board Configuration (read at RESET)
+        .endm                                        
+
+/*---------------------------------------------------------------------------*/
+/* end of hal_platform_setup.h                                               */
+#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
diff --git a/packages/hal/arm/sa11x0/assabet/current/include/pkgconf/mlt_arm_sa11x0_assabet_ram.h b/packages/hal/arm/sa11x0/assabet/current/include/pkgconf/mlt_arm_sa11x0_assabet_ram.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/assabet/current/include/pkgconf/mlt_arm_sa11x0_assabet_ram.h
@@ -0,0 +1,10 @@
+// eCos memory layout - Sun Jun 04 12:17:47 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#define CYGMEM_REGION_ram (0)
+#define CYGMEM_REGION_ram_SIZE (0x2000000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
diff --git a/packages/hal/arm/sa11x0/assabet/current/include/pkgconf/mlt_arm_sa11x0_assabet_ram.ldi b/packages/hal/arm/sa11x0/assabet/current/include/pkgconf/mlt_arm_sa11x0_assabet_ram.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/assabet/current/include/pkgconf/mlt_arm_sa11x0_assabet_ram.ldi
@@ -0,0 +1,24 @@
+// eCos memory layout - Sun Jun 04 12:17:47 2000
+
+// This is a generated file - do not edit
+
+MEMORY
+{
+    ram : ORIGIN = 0, LENGTH = 0x2000000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
+    SECTION_rom_vectors (ram, 0x10000, LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTIONS_END
+}
diff --git a/packages/hal/arm/sa11x0/assabet/current/include/pkgconf/mlt_arm_sa11x0_assabet_ram.mlt b/packages/hal/arm/sa11x0/assabet/current/include/pkgconf/mlt_arm_sa11x0_assabet_ram.mlt
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/assabet/current/include/pkgconf/mlt_arm_sa11x0_assabet_ram.mlt
@@ -0,0 +1,12 @@
+version 0
+region ram 0 2000000 0 !
+section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
+section rom_vectors 0 1 0 1 1 1 1 1 10000 10000 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata rodata !
+section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 4 0 1 0 1 0 1 data data !
+section data 0 4 0 1 0 1 0 1 bss bss !
+section bss 0 4 0 1 0 0 0 0 !
diff --git a/packages/hal/arm/sa11x0/assabet/current/include/pkgconf/mlt_arm_sa11x0_assabet_rom.h b/packages/hal/arm/sa11x0/assabet/current/include/pkgconf/mlt_arm_sa11x0_assabet_rom.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/assabet/current/include/pkgconf/mlt_arm_sa11x0_assabet_rom.h
@@ -0,0 +1,13 @@
+// eCos memory layout - Sun Jun 04 12:19:07 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#define CYGMEM_REGION_ram (0)
+#define CYGMEM_REGION_ram_SIZE (0x2000000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0x50000000)
+#define CYGMEM_REGION_rom_SIZE (0x40000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
diff --git a/packages/hal/arm/sa11x0/assabet/current/include/pkgconf/mlt_arm_sa11x0_assabet_rom.ldi b/packages/hal/arm/sa11x0/assabet/current/include/pkgconf/mlt_arm_sa11x0_assabet_rom.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/assabet/current/include/pkgconf/mlt_arm_sa11x0_assabet_rom.ldi
@@ -0,0 +1,25 @@
+// eCos memory layout - Sun Jun 04 12:19:07 2000
+
+// This is a generated file - do not edit
+
+MEMORY
+{
+    ram : ORIGIN = 0, LENGTH = 0x2000000
+    rom : ORIGIN = 0x50000000, LENGTH = 0x40000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (rom, 0x50000000, LMA_EQ_VMA)
+    SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
+    SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table))
+    SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTIONS_END
+}
diff --git a/packages/hal/arm/sa11x0/assabet/current/include/pkgconf/mlt_arm_sa11x0_assabet_rom.mlt b/packages/hal/arm/sa11x0/assabet/current/include/pkgconf/mlt_arm_sa11x0_assabet_rom.mlt
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/assabet/current/include/pkgconf/mlt_arm_sa11x0_assabet_rom.mlt
@@ -0,0 +1,13 @@
+version 0
+region ram 0 2000000 0 !
+region rom 50000000 40000 1 !
+section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
+section data 0 1 1 1 1 1 0 0 8000 bss !
+section bss 0 4 0 1 0 0 0 0 !
+section rom_vectors 0 1 0 1 1 1 1 1 50000000 50000000 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata rodata !
+section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 4 0 1 0 0 0 1 data !
diff --git a/packages/hal/arm/sa11x0/assabet/current/misc/cf_test.c b/packages/hal/arm/sa11x0/assabet/current/misc/cf_test.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/assabet/current/misc/cf_test.c
@@ -0,0 +1,140 @@
+//==========================================================================
+//
+//        cf_test.c
+//
+//        SA1110/Assabet - Compact Flash test
+//
+//==========================================================================
+//####COPYRIGHTBEGIN####
+//                                                                          
+// -------------------------------------------                              
+// The contents of this file are subject to the Red Hat eCos Public License 
+// Version 1.1 (the "License"); you may not use this file except in         
+// compliance with the License.  You may obtain a copy of the License at    
+// http://www.redhat.com/                                                   
+//                                                                          
+// Software distributed under the License is distributed on an "AS IS"      
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+// License for the specific language governing rights and limitations under 
+// the License.                                                             
+//                                                                          
+// The Original Code is eCos - Embedded Configurable Operating System,      
+// released September 30, 1998.                                             
+//                                                                          
+// The Initial Developer of the Original Code is Red Hat.                   
+// Portions created by Red Hat are                                          
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+// All Rights Reserved.                                                     
+// -------------------------------------------                              
+//                                                                          
+//####COPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     gthomas
+// Contributors:  gthomas
+// Date:          2000-06-05
+// Description:   Tool used to test CF stuff
+//####DESCRIPTIONEND####
+
+#include <pkgconf/kernel.h>   // Configuration header
+#include <cyg/kernel/kapi.h>
+#include <cyg/infra/diag.h>
+
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_arch.h>           // Register state info
+#include <cyg/hal/hal_intr.h>           // HAL interrupt macros
+
+#include <cyg/hal/hal_sa11x0.h>  // Board definitions
+#include <cyg/hal/assabet.h>
+
+#ifndef FALSE
+#define FALSE 0
+#define TRUE  1
+#endif
+
+#define STACK_SIZE 4096
+static char stack[STACK_SIZE];
+static cyg_thread thread_data;
+static cyg_handle_t thread_handle;
+
+static cyg_interrupt cf_interrupt;
+static cyg_handle_t  cf_interrupt_handle;
+
+// FUNCTIONS
+
+static void
+cyg_test_exit(void)
+{
+    while (TRUE) ;
+}
+
+// This ISR is called when a CompactFlash board is inserted
+static int
+cf_detect_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
+{
+    cyg_interrupt_mask(SA1110_CF_DETECT);
+    return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR);  // Run the DSR
+}
+
+// This DSR handles the board insertion
+static void
+cf_detect_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
+{
+    unsigned long new_state = *SA11X0_GPIO_PIN_LEVEL;
+    diag_printf("CF card inserted, state: %x\n", new_state);
+    cyg_interrupt_acknowledge(SA1110_CF_DETECT);
+    cyg_interrupt_unmask(SA1110_CF_DETECT);
+}
+
+static void
+cf_test(cyg_addrword_t p)
+{
+    unsigned long cf_state;
+    diag_printf("CF test here\n");
+    // Disable CF bus & power (idle/off)
+    assabet_BCR(SA1110_BCR_CF_POWER |
+                SA1110_BCR_CF_RESET |
+                SA1110_BCR_CF_BUS,
+                SA1110_BCR_CF_POWER_OFF |
+                SA1110_BCR_CF_RESET_DISABLE |
+                SA1110_BCR_CF_BUS_OFF);
+    while (1) {
+        cf_state = *SA11X0_GPIO_PIN_LEVEL;
+        if ((cf_state & SA1110_GPIO_CF_DETECT) == SA1110_GPIO_CF_PRESENT) {
+            diag_printf("Compact Flash card inserted!\n");
+            diag_dump_buf(0x30000000, 0x100);
+            break;
+        }
+    }
+    cyg_test_exit();
+}
+
+externC void
+cyg_start( void )
+{
+    // Set up interrupts
+    cyg_interrupt_create(SA1110_CF_DETECT,
+                         99,                     // Priority - what goes here?
+                         0,                      //  Data item passed to interrupt handler
+                         (cyg_ISR_t *)cf_detect_isr,
+                         (cyg_DSR_t *)cf_detect_dsr,
+                         &cf_interrupt_handle,
+                         &cf_interrupt);
+    cyg_interrupt_attach(cf_interrupt_handle);
+    cyg_interrupt_configure(SA1110_CF_DETECT, true, true);  // Detect either edge
+    cyg_interrupt_acknowledge(SA1110_CF_DETECT);
+    cyg_interrupt_unmask(SA1110_CF_DETECT);
+    // Create a main thread, so we can run the scheduler and have time 'pass'
+    cyg_thread_create(10,                // Priority - just a number
+                      cf_test,           // entry
+                      0,                 // entry parameter
+                      "CompactFlash test",  // Name
+                      &stack[0],         // Stack
+                      STACK_SIZE,        // Size
+                      &thread_handle,    // Handle
+                      &thread_data       // Thread data structure
+            );
+    cyg_thread_resume(thread_handle);  // Start it
+    cyg_scheduler_start();
+} // cyg_package_start()
diff --git a/packages/hal/arm/sa11x0/assabet/current/src/assabet_misc.c b/packages/hal/arm/sa11x0/assabet/current/src/assabet_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/assabet/current/src/assabet_misc.c
@@ -0,0 +1,246 @@
+//==========================================================================
+//
+//      assabet_misc.c
+//
+//      HAL misc board support code for StrongARM SA1110/Assabet
+//
+//==========================================================================
+//####COPYRIGHTBEGIN####
+//
+// -------------------------------------------
+// The contents of this file are subject to the Red Hat eCos Public License
+// Version 1.1 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://www.redhat.com/
+//
+// Software distributed under the License is distributed on an "AS IS"
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the
+// License for the specific language governing rights and limitations under
+// the License. 
+//
+// The Original Code is eCos - Embedded Configurable Operating System,
+// released September 30, 1998.
+//
+// The Initial Developer of the Original Code is Red Hat.
+// Portions created by Red Hat are
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
+// All Rights Reserved.
+// -------------------------------------------
+//
+//####COPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: hmt
+//               Travis C. Furrer <furrer@mit.edu>
+// Date:         2000-05-21
+// Purpose:      HAL board support
+// Description:  Implementations of HAL board interfaces
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_arch.h>           // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h>           // Interrupt names
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_sa11x0.h>         // Hardware definitions
+#include <cyg/hal/assabet.h>            // Platform specifics
+
+#include <cyg/infra/diag.h>             // diag_printf
+
+// -------------------------------------------------------------------------
+// MMU initialization:
+// 
+// These structures are laid down in memory to define the translation
+// table.
+// 
+
+/*
+ * SA-1100 Translation Table Base Bit Masks */
+#define ARM_TRANSLATION_TABLE_MASK               0xFFFFC000
+
+/*
+ * SA-1100 Domain Access Control Bit Masks
+ */
+#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num)    (0x0 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_CLIENT(domain_num)       (0x1 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_MANAGER(domain_num)      (0x3 << (domain_num)*2)
+
+struct ARM_MMU_FIRST_LEVEL_FAULT {
+    int id : 2;
+    int sbz : 30;
+};
+#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
+
+struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
+    int id : 2;
+    int imp : 2;
+    int domain : 4;
+    int sbz : 1;
+    int base_address : 23;
+};
+#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
+
+struct ARM_MMU_FIRST_LEVEL_SECTION {
+    int id : 2;
+    int b : 1;
+    int c : 1;
+    int imp : 1;
+    int domain : 4;
+    int sbz0 : 1;
+    int ap : 2;
+    int sbz1 : 8;
+    int base_address : 12;
+};
+#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
+
+struct ARM_MMU_FIRST_LEVEL_RESERVED {
+    int id : 2;
+    int sbz : 30;
+};
+#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
+
+#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
+   (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
+
+#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
+
+#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base,              \
+                        cacheable, bufferable, perm)                      \
+    CYG_MACRO_START                                                       \
+        register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc;               \
+                                                                          \
+        desc.word = 0;                                                    \
+        desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID;                 \
+        desc.section.domain = 0;                                          \
+        desc.section.c = (cacheable);                                     \
+        desc.section.b = (bufferable);                                    \
+        desc.section.ap = (perm);                                         \
+        desc.section.base_address = (actual_base);                        \
+        *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
+                            = desc.word;                                  \
+    CYG_MACRO_END
+
+#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access)      \
+    { int i; int j = abase; int k = vbase;                         \
+      for (i = size; i > 0 ; i--,j++,k++)                          \
+      {                                                            \
+        ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access);      \
+      }                                                            \
+    }
+
+union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
+    unsigned long word;
+    struct ARM_MMU_FIRST_LEVEL_FAULT fault;
+    struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
+    struct ARM_MMU_FIRST_LEVEL_SECTION section;
+    struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
+};
+
+#define ARM_UNCACHEABLE                         0
+#define ARM_CACHEABLE                           1
+#define ARM_UNBUFFERABLE                        0
+#define ARM_BUFFERABLE                          1
+
+#define ARM_ACCESS_PERM_NONE_NONE               0
+#define ARM_ACCESS_PERM_RO_NONE                 0
+#define ARM_ACCESS_PERM_RO_RO                   0
+#define ARM_ACCESS_PERM_RW_NONE                 1
+#define ARM_ACCESS_PERM_RW_RO                   2
+#define ARM_ACCESS_PERM_RW_RW                   3
+
+void
+hal_mmu_init(void)
+{
+    unsigned long ttb_base = SA11X0_RAM_BANK0_BASE + 0x4000;
+    unsigned long i;
+
+    /*
+     * Set the TTB register
+     */
+    asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+
+    /*
+     * Set the Domain Access Control Register
+     */
+    i = ARM_ACCESS_TYPE_MANAGER(0)    | 
+        ARM_ACCESS_TYPE_NO_ACCESS(1)  |
+        ARM_ACCESS_TYPE_NO_ACCESS(2)  |
+        ARM_ACCESS_TYPE_NO_ACCESS(3)  |
+        ARM_ACCESS_TYPE_NO_ACCESS(4)  |
+        ARM_ACCESS_TYPE_NO_ACCESS(5)  |
+        ARM_ACCESS_TYPE_NO_ACCESS(6)  |
+        ARM_ACCESS_TYPE_NO_ACCESS(7)  |
+        ARM_ACCESS_TYPE_NO_ACCESS(8)  |
+        ARM_ACCESS_TYPE_NO_ACCESS(9)  |
+        ARM_ACCESS_TYPE_NO_ACCESS(10) |
+        ARM_ACCESS_TYPE_NO_ACCESS(11) |
+        ARM_ACCESS_TYPE_NO_ACCESS(12) |
+        ARM_ACCESS_TYPE_NO_ACCESS(13) |
+        ARM_ACCESS_TYPE_NO_ACCESS(14) |
+        ARM_ACCESS_TYPE_NO_ACCESS(15);
+    asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+    /*
+     * First clear all TT entries - ie Set them to Faulting
+     */
+    memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+
+    /*               Actual  Virtual  Size   Attributes                                                    Function  */
+    /*		     Base     Base     MB      cached?           buffered?        access permissions                 */
+    /*             xxx00000  xxx00000                                                                                */
+    X_ARM_MMU_SECTION(0x000,  0x500,     1,  ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* Boot flash ROMspace */
+    X_ARM_MMU_SECTION(0x080,  0x080,     4,  ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* Application flash ROM */
+    X_ARM_MMU_SECTION(0x100,  0x100,   128,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SA-1101 Development Board Registers */
+    X_ARM_MMU_SECTION(0x180,  0x180,   128,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Ethernet Adaptor */
+    X_ARM_MMU_SECTION(0x184,  0x184,     1,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* XBusReg    */
+    X_ARM_MMU_SECTION(0x188,  0x188,     1,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SysRegA    */
+    X_ARM_MMU_SECTION(0x18C,  0x18C,     1,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SysRegB    */
+    X_ARM_MMU_SECTION(0x190,  0x190,     4,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CPLD A     */
+    X_ARM_MMU_SECTION(0x194,  0x194,     4,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CPLD B     */
+    X_ARM_MMU_SECTION(0x200,  0x200,   512,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA Socket A */
+    X_ARM_MMU_SECTION(0x300,  0x300,   512,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA Sockets B */
+    X_ARM_MMU_SECTION(0x400,  0x400,   128,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SA1111 Daughter card */
+    X_ARM_MMU_SECTION(0x480,  0x480,   128,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Video Controller Daughter card */
+    X_ARM_MMU_SECTION(0x800,  0x800, 0x400,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* StrongARM(R) Registers */
+    X_ARM_MMU_SECTION(0xC00,      0,    32,  ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 0 */
+    X_ARM_MMU_SECTION(0xC00,  0xC00,    32,  ARM_UNCACHEABLE, ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 0 */
+    X_ARM_MMU_SECTION(0xE00,  0xE00,   128,  ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* Zeros (Cache Clean) Bank */
+
+}
+
+//
+// Board control register support
+//   Update the board control register (write only).  Only the bits
+// specified by 'mask' are changed to 'value'.
+//
+
+void
+assabet_BCR(unsigned long mask, unsigned long value)
+{
+    _assabet_BCR = (_assabet_BCR & ~mask) | (mask & value);
+    *SA1110_BOARD_CONTROL = _assabet_BCR;
+}
+
+//
+// Platform specific initialization
+//
+
+void
+plf_hardware_init(void)
+{
+    // Force "alternate" use of GPIO pins used for LCD screen
+//    *SA11X0_GPIO_ALTERNATE_FUNCTION |= 0x000003FC;  // Bits 2..9
+}
diff --git a/packages/hal/arm/sa11x0/assabet/current/support/README b/packages/hal/arm/sa11x0/assabet/current/support/README
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/assabet/current/support/README
@@ -0,0 +1,6 @@
+This directory contains programs/files obtained from the Intel
+developer's website - http://developer.intel.com/
+
+SA1110Jflash.tgz - A set of tools for updating the flash devices
+                   on the Assabet board in place using a parallel
+                   port on either Linux or Windows.
\ No newline at end of file
diff --git a/packages/hal/arm/sa11x0/assabet/current/support/SA1110Jflash.tgz b/packages/hal/arm/sa11x0/assabet/current/support/SA1110Jflash.tgz
new file mode 100644
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diff --git a/packages/hal/arm/sa11x0/brutus/current/ChangeLog b/packages/hal/arm/sa11x0/brutus/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/brutus/current/ChangeLog
@@ -0,0 +1,83 @@
+2000-06-26  Jesper Skov  <jskov@redhat.com>
+
+	* include/hal_platform_ints.h: Removed Ctrl-c handling.
+
+	* cdl/hal_arm_sa11x0_brutus.cdl: Removed ROM_DEBUG_CHANNEL option.
+
+2000-06-19  Gary Thomas  <gthomas@redhat.com>
+
+	* src/brutus_misc.c: Define proper MMU initialization.
+
+	* include/hal_platform_setup.h: Rework MMU initialization to
+	be closer to other SA1xx platforms (Assabet, EBSA285)
+
+2000-06-18  Gary Thomas  <gthomas@redhat.com>
+
+	* include/pkgconf/mlt_arm_sa11x0_brutus_rom.ldi: 
+	* include/pkgconf/mlt_arm_sa11x0_brutus_rom.mlt: 
+	* include/pkgconf/mlt_arm_sa11x0_brutus_ram.mlt: 
+	* include/pkgconf/mlt_arm_sa11x0_brutus_ram.ldi: 
+	Incorporate new fixed vectors (used on all ARM platforms).
+
+2000-06-08  Gary Thomas  <gthomas@redhat.com>
+
+	* include/hal_platform_setup.h: Adding ROM startup support.
+
+2000-06-05  Gary Thomas  <gthomas@redhat.com>
+
+	* cdl/hal_arm_sa11x0_brutus.cdl: Default serial port is 0
+	(maps to UART 3 on J23).
+
+	* include/hal_platform_ints.h: Add missing GPIO interrupts.
+
+2000-06-04  Gary Thomas  <gthomas@redhat.com>
+
+	* include/hal_platform_setup.h: 'sa1100' stuff renamed to 'sa11x0'.
+
+2000-06-01  Gary Thomas  <gthomas@redhat.com>
+
+	* cdl/hal_arm_sa11x0_brutus.cdl: Adding ROM startup support.
+
+2000-05-12  John Dallaway  <jld@redhat.com>
+
+	* cdl/hal_arm_sa11x0_brutus.cdl:
+
+	Fix calculation of CYGHWR_MEMORY_LAYOUT.
+
+2000-05-10  Gary Thomas  <gthomas@redhat.com>
+
+	* current/include/pkgconf/mlt_arm_sa11x0_brutus_rom.h: 
+	* current/include/pkgconf/mlt_arm_sa11x0_brutus_rom.ldi: 
+	* current/include/pkgconf/mlt_arm_sa11x0_brutus_rom.mlt: 
+	* current/include/pkgconf/mlt_arm_sa11x0_brutus_ram.mlt: 
+	* current/include/pkgconf/mlt_arm_sa11x0_brutus_ram.h: 
+	* current/include/pkgconf/mlt_arm_sa11x0_brutus_ram.ldi: 
+	* current/include/hal_platform_ints.h: 
+	* current/include/hal_platform_setup.h: 
+	* current/cdl/hal_arm_sa11x0_brutus.cdl: New file(s).
+
+//===========================================================================
+//####COPYRIGHTBEGIN####
+//                                                                          
+// -------------------------------------------                              
+// The contents of this file are subject to the Red Hat eCos Public License 
+// Version 1.1 (the "License"); you may not use this file except in         
+// compliance with the License.  You may obtain a copy of the License at    
+// http://www.redhat.com/                                                   
+//                                                                          
+// Software distributed under the License is distributed on an "AS IS"      
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+// License for the specific language governing rights and limitations under 
+// the License.                                                             
+//                                                                          
+// The Original Code is eCos - Embedded Configurable Operating System,      
+// released September 30, 1998.                                             
+//                                                                          
+// The Initial Developer of the Original Code is Red Hat.                   
+// Portions created by Red Hat are                                          
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+// All Rights Reserved.                                                     
+// -------------------------------------------                              
+//                                                                          
+//####COPYRIGHTEND####
+//===========================================================================
diff --git a/packages/hal/arm/sa11x0/brutus/current/cdl/hal_arm_sa11x0_brutus.cdl b/packages/hal/arm/sa11x0/brutus/current/cdl/hal_arm_sa11x0_brutus.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/brutus/current/cdl/hal_arm_sa11x0_brutus.cdl
@@ -0,0 +1,324 @@
+# ====================================================================
+#
+#      hal_arm_sa11x0_brutus.cdl
+#
+#      ARM SA1100/Brutus platform HAL package configuration data
+#
+# ====================================================================
+#####COPYRIGHTBEGIN####
+#                                                                          
+# -------------------------------------------                              
+# The contents of this file are subject to the Red Hat eCos Public License 
+# Version 1.1 (the "License"); you may not use this file except in         
+# compliance with the License.  You may obtain a copy of the License at    
+# http://www.redhat.com/                                                   
+#                                                                          
+# Software distributed under the License is distributed on an "AS IS"      
+# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+# License for the specific language governing rights and limitations under 
+# the License.                                                             
+#                                                                          
+# The Original Code is eCos - Embedded Configurable Operating System,      
+# released September 30, 1998.                                             
+#                                                                          
+# The Initial Developer of the Original Code is Red Hat.                   
+# Portions created by Red Hat are                                          
+# Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+# All Rights Reserved.                                                     
+# -------------------------------------------                              
+#                                                                          
+#####COPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      gthomas
+# Original data:  gthomas
+# Contributors:
+# Date:           2000-05-08
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+cdl_package CYGPKG_HAL_ARM_SA11X0_BRUTUS {
+    display       "ARM SA1100/Brutus evaluation board"
+    parent        CYGPKG_HAL_ARM_SA11X0
+    hardware
+    include_dir   cyg/hal
+    define_header hal_arm_sa11x0_brutus.h
+    description   "
+        This HAL platform package provides generic
+        support for the Intel StrongARM SA1100 based evalation board, 
+	known as 'brutus'."
+
+    compile       brutus_misc.c
+
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_GUARANTEED
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_arm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_arm_sa11x0.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_sa11x0_brutus.h>"
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value {"RAM"}
+        legal_values  {"RAM" "ROM"}
+	no_define
+	define -file system.h CYG_HAL_STARTUP
+        description   "
+           When targetting the Brutus eval board it is possible to build
+           the system for either RAM bootstrap or ROM bootstrap(s). Select
+           'ram' when building programs to load into RAM using eCos GDB
+           stubs.  Select 'rom' when building a stand-alone application
+           which will be put into ROM, or for the special case of
+           building the eCos GDB stubs themselves."
+    }
+
+    cdl_option CYGHWR_HAL_ARM_SA11X0_DIAG_PORT {
+        display       "Diagnostic serial port"
+        flavor        data
+        legal_values  0 1
+        default_value 1
+        description   "
+            The Brutus evaluation boards have two separate serial ports.  This option
+            chooses which of these ports will be used."
+    }
+
+    cdl_option CYGHWR_HAL_ARM_SA11X0_DIAG_BAUD {
+        display       "Diagnostic serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 115200
+        default_value 38400
+        description   "
+            This option selects the baud rate used for the diagnostic port.
+            Note: this should match the value chosen for the GDB port if the
+            diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGHWR_HAL_ARM_SA11X0_GDB_PORT {
+        display       "GDB serial port"
+        flavor        data
+        legal_values  0 1
+        default_value 1
+        description   "
+            The Brutus evaluation boards have two separate serial ports.  This option
+            chooses which of these ports will be used."
+    }
+
+    cdl_option CYGHWR_HAL_ARM_SA11X0_GDB_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 115200
+        default_value 38400
+        description   "
+            This option selects the baud rate used for the diagnostic port.
+            Note: this should match the value chosen for the GDB port if the
+            diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        calculated   2
+    }
+ 
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    CYGHWR_HAL_ARM_SA11X0_GDB_PORT
+        description      "
+            The brutus board has two serial ports. This option
+            chooses which port will be used to connect to a host
+            running GDB."
+     }
+ 
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display          "Diagnostic serial port"
+         flavor data
+         legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+         default_value    CYGHWR_HAL_ARM_SA11X0_DIAG_PORT
+         description      "
+            The brutus board has two serial ports.  This option
+            chooses which port will be used for diagnostic output."
+     }
+ 
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        no_define
+        description   "
+	    Global build options including control over
+	    compiler flags, linker flags and choice of toolchain."
+
+
+        parent  CYGPKG_NONE
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-elf" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=strongarm1100 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+
+        cdl_option CYGBLD_BUILD_GDB_STUBS {
+            display "Build GDB stub ROM image"
+            default_value 0
+            requires { CYG_HAL_STARTUP == "ROM" }
+            requires CYGSEM_HAL_ROM_MONITOR
+            requires CYGBLD_BUILD_COMMON_GDB_STUBS
+            requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+            requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+            requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+            requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+            requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+            no_define
+            description "
+                This option enables the building of the GDB stubs for the
+                board. The common HAL controls takes care of most of the
+                build process, but the final conversion from ELF image to
+                binary data is handled by the platform CDL, allowing
+                relocation of the data if necessary."
+
+            make -priority 320 {
+                <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
+                $(OBJCOPY) -O binary $< $@
+            }
+        }
+    }
+
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+         display       "Work with a ROM monitor"
+         flavor        booldata
+         legal_values  { "Generic" "GDB_stubs" }
+         default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+         parent        CYGPKG_HAL_ROM_MONITOR
+         requires      { CYG_HAL_STARTUP == "RAM" }
+         description   "
+             Support can be enabled for different varieties of ROM monitor.
+             This support changes various eCos semantics such as the encoding
+             of diagnostic output, or the overriding of hardware interrupt
+             vectors.
+             Firstly there is \"Generic\" support which prevents the HAL
+             from overriding the hardware vectors that it does not use, to
+             instead allow an installed ROM monitor to handle them. This is
+             the most basic support which is likely to be common to most
+             implementations of ROM monitor.
+             \"GDB_stubs\" provides support when GDB stubs are included in
+             the ROM monitor or boot ROM."
+    }
+
+    cdl_component CYGPKG_HAL_ARM_SA11X0_BRUTUS_OPTIONS {
+        display "StrongARM SA1100/BRUTUS build options"
+        flavor  none
+        no_define
+        description   "
+	    Package specific build options including control over
+	    compiler flags used only in building this package,
+	    and details of which tests are built."
+
+
+        cdl_option CYGPKG_HAL_ARM_SA11X0_BRUTUS_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the StrongARM Brutus HAL. These flags are used in addition
+                to the set of global flags."
+        }
+
+        cdl_option CYGPKG_HAL_ARM_SA11X0_BRUTUS_CFLAGS_REMOVE {
+            display "Supressed compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the StrongARM Brutus HAL. These flags are removed from
+                the set of global flags if present."
+        }
+
+        cdl_option CYGPKG_HAL_ARM_SA11X0_BRUTUS_TESTS {
+            display "StrongARM SA1100/Brutus tests"
+            flavor  data
+            no_define
+#            calculated { "tests/dram-test" }
+            calculated { "" }
+            description   "
+                This option specifies the set of tests for the StrongARM Brutus HAL."
+        }
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        calculated { CYG_HAL_STARTUP == "RAM" ? "arm_sa11x0_brutus_ram" : \
+	                                        "arm_sa11x0_brutus_rom" }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display "Memory layout linker script fragment"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+            calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_sa11x0_brutus_ram.ldi>" : \
+                                                    "<pkgconf/mlt_arm_sa11x0_brutus_rom.ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display "Memory layout header file"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+            calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_sa11x0_brutus_ram.h>" : \
+                                                    "<pkgconf/mlt_arm_sa11x0_brutus_rom.h>" }
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+}
diff --git a/packages/hal/arm/sa11x0/brutus/current/include/brutus.h b/packages/hal/arm/sa11x0/brutus/current/include/brutus.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/brutus/current/include/brutus.h
@@ -0,0 +1,50 @@
+#ifndef CYGONCE_BRUTUS_H
+#define CYGONCE_BRUTUS_H
+
+/*=============================================================================
+//
+//      brutus.h
+//
+//      Platform specific support (registers, etc)
+//
+//=============================================================================
+//####COPYRIGHTBEGIN####
+//                                                                          
+// -------------------------------------------                              
+// The contents of this file are subject to the Red Hat eCos Public License 
+// Version 1.1 (the "License"); you may not use this file except in         
+// compliance with the License.  You may obtain a copy of the License at    
+// http://www.redhat.com/                                                   
+//                                                                          
+// Software distributed under the License is distributed on an "AS IS"      
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+// License for the specific language governing rights and limitations under 
+// the License.                                                             
+//                                                                          
+// The Original Code is eCos - Embedded Configurable Operating System,      
+// released September 30, 1998.                                             
+//                                                                          
+// The Initial Developer of the Original Code is Red Hat.                   
+// Portions created by Red Hat are                                          
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+// All Rights Reserved.                                                     
+// -------------------------------------------                              
+//                                                                          
+//####COPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+// Date:         2000-05-08
+// Purpose:      Intel SA1110/Brutus platform specific support routines
+// Description: 
+// Usage:        #include <cyg/hal/brutus.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+/*---------------------------------------------------------------------------*/
+/* end of brutus.h                                                          */
+#endif /* CYGONCE_BRUTUS_H */
diff --git a/packages/hal/arm/sa11x0/brutus/current/include/hal_platform_ints.h b/packages/hal/arm/sa11x0/brutus/current/include/hal_platform_ints.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/brutus/current/include/hal_platform_ints.h
@@ -0,0 +1,108 @@
+#ifndef CYGONCE_HAL_PLATFORM_INTS_H
+#define CYGONCE_HAL_PLATFORM_INTS_H
+//==========================================================================
+//
+//      hal_platform_ints.h
+//
+//      HAL Interrupt and clock support
+//
+//==========================================================================
+//####COPYRIGHTBEGIN####
+//                                                                          
+// -------------------------------------------                              
+// The contents of this file are subject to the Red Hat eCos Public License 
+// Version 1.1 (the "License"); you may not use this file except in         
+// compliance with the License.  You may obtain a copy of the License at    
+// http://www.redhat.com/                                                   
+//                                                                          
+// Software distributed under the License is distributed on an "AS IS"      
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+// License for the specific language governing rights and limitations under 
+// the License.                                                             
+//                                                                          
+// The Original Code is eCos - Embedded Configurable Operating System,      
+// released September 30, 1998.                                             
+//                                                                          
+// The Initial Developer of the Original Code is Red Hat.                   
+// Portions created by Red Hat are                                          
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+// All Rights Reserved.                                                     
+// -------------------------------------------                              
+//                                                                          
+//####COPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+// Date:         2000-05-08
+// Purpose:      Define Interrupt support
+// Description:  The interrupt details for the SA1100/Brutus are defined here.
+// Usage:
+//               #include <cyg/hal/hal_platform_ints.h>
+//               ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#define CYGNUM_HAL_INTERRUPT_GPIO0   0
+#define CYGNUM_HAL_INTERRUPT_GPIO1   1
+#define CYGNUM_HAL_INTERRUPT_GPIO2   2
+#define CYGNUM_HAL_INTERRUPT_GPIO3   3
+#define CYGNUM_HAL_INTERRUPT_GPIO4   4
+#define CYGNUM_HAL_INTERRUPT_GPIO5   5
+#define CYGNUM_HAL_INTERRUPT_GPIO6   6
+#define CYGNUM_HAL_INTERRUPT_GPIO7   7
+#define CYGNUM_HAL_INTERRUPT_GPIO8   8
+#define CYGNUM_HAL_INTERRUPT_GPIO9   9
+#define CYGNUM_HAL_INTERRUPT_GPIO10  10
+#define CYGNUM_HAL_INTERRUPT_GPIO    11  // Don't use directly
+#define CYGNUM_HAL_INTERRUPT_LCD     12
+#define CYGNUM_HAL_INTERRUPT_UDC     13
+#define CYGNUM_HAL_INTERRUPT_UART1   15
+#define CYGNUM_HAL_INTERRUPT_UART2   16
+#define CYGNUM_HAL_INTERRUPT_UART3   17
+#define CYGNUM_HAL_INTERRUPT_MCP     18
+#define CYGNUM_HAL_INTERRUPT_SSP     19
+#define CYGNUM_HAL_INTERRUPT_TIMER0  26
+#define CYGNUM_HAL_INTERRUPT_TIMER1  27
+#define CYGNUM_HAL_INTERRUPT_TIMER2  28
+#define CYGNUM_HAL_INTERRUPT_TIMER3  29
+#define CYGNUM_HAL_INTERRUPT_HZ      30
+#define CYGNUM_HAL_INTERRUPT_ALARM   31
+
+// GPIO bits 31..11 can generate interrupts as well, but they all
+// end up clumped into interrupt signal #11.  Using the symbols
+// below allow for detection of these separately.
+
+#define CYGNUM_HAL_INTERRUPT_GPIO11  (32+11)
+#define CYGNUM_HAL_INTERRUPT_GPIO12  (32+12)
+#define CYGNUM_HAL_INTERRUPT_GPIO13  (32+13)
+#define CYGNUM_HAL_INTERRUPT_GPIO14  (32+14)
+#define CYGNUM_HAL_INTERRUPT_GPIO15  (32+15)
+#define CYGNUM_HAL_INTERRUPT_GPIO16  (32+16)
+#define CYGNUM_HAL_INTERRUPT_GPIO17  (32+17)
+#define CYGNUM_HAL_INTERRUPT_GPIO18  (32+18)
+#define CYGNUM_HAL_INTERRUPT_GPIO19  (32+19)
+#define CYGNUM_HAL_INTERRUPT_GPIO20  (32+20)
+#define CYGNUM_HAL_INTERRUPT_GPIO21  (32+21)
+#define CYGNUM_HAL_INTERRUPT_GPIO22  (32+22)
+#define CYGNUM_HAL_INTERRUPT_GPIO23  (32+23)
+#define CYGNUM_HAL_INTERRUPT_GPIO24  (32+24)
+#define CYGNUM_HAL_INTERRUPT_GPIO25  (32+25)
+#define CYGNUM_HAL_INTERRUPT_GPIO26  (32+26)
+#define CYGNUM_HAL_INTERRUPT_GPIO27  (32+27)
+
+#define CYGNUM_HAL_INTERRUPT_NONE    -1
+
+#define CYGNUM_HAL_ISR_MIN            0
+#define CYGNUM_HAL_ISR_MAX           (27+32)
+
+#define CYGNUM_HAL_ISR_COUNT            (CYGNUM_HAL_ISR_MAX+1)
+
+// The vector used by the Real time clock
+#define CYGNUM_HAL_INTERRUPT_RTC        CYGNUM_HAL_INTERRUPT_TIMER0
+
+#endif // CYGONCE_HAL_PLATFORM_INTS_H
diff --git a/packages/hal/arm/sa11x0/brutus/current/include/hal_platform_setup.h b/packages/hal/arm/sa11x0/brutus/current/include/hal_platform_setup.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/brutus/current/include/hal_platform_setup.h
@@ -0,0 +1,363 @@
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+
+/*=============================================================================
+//
+//      hal_platform_setup.h
+//
+//      Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+//####COPYRIGHTBEGIN####
+//                                                                          
+// -------------------------------------------                              
+// The contents of this file are subject to the Red Hat eCos Public License 
+// Version 1.1 (the "License"); you may not use this file except in         
+// compliance with the License.  You may obtain a copy of the License at    
+// http://www.redhat.com/                                                   
+//                                                                          
+// Software distributed under the License is distributed on an "AS IS"      
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+// License for the specific language governing rights and limitations under 
+// the License.                                                             
+//                                                                          
+// The Original Code is eCos - Embedded Configurable Operating System,      
+// released September 30, 1998.                                             
+//                                                                          
+// The Initial Developer of the Original Code is Red Hat.                   
+// Portions created by Red Hat are                                          
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+// All Rights Reserved.                                                     
+// -------------------------------------------                              
+//                                                                          
+//####COPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+//               Travis C. Furrer <furrer@mit.edu>
+// Date:         2000-05-08
+// Purpose:      Intel SA1110/Assabet platform specific support routines
+// Description: 
+// Usage:        #include <cyg/hal/hal_platform_setup.h>
+//     This file should only be used by "vectors.S"        
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/system.h>             // System-wide configuration info
+#include CYGBLD_HAL_PLATFORM_H          // Platform specific configuration
+#include <cyg/hal/hal_sa11x0.h>         // Platform specific hardware definitions
+#include <cyg/hal/hal_mmu.h>            // MMU definitions
+
+#if defined(CYG_HAL_STARTUP_ROM)
+#define PLATFORM_SETUP1 _platform_setup1
+#define CYGHWR_HAL_ARM_HAS_MMU
+
+#if (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 59000)
+#define SA11X0_PLL_CLOCK 0x0        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 73700)
+#define SA11X0_PLL_CLOCK 0x1
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 88500)
+#define SA11X0_PLL_CLOCK 0x2        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 103200) 
+#define SA11X0_PLL_CLOCK 0x3        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 118000)
+#define SA11X0_PLL_CLOCK 0x4        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 132700)
+#define SA11X0_PLL_CLOCK 0x5        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 147500)
+#define SA11X0_PLL_CLOCK 0x6        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 162200)
+#define SA11X0_PLL_CLOCK 0x7        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 176900)
+#define SA11X0_PLL_CLOCK 0x8        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 191700)
+#define SA11X0_PLL_CLOCK 0x9        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 206400)
+#define SA11X0_PLL_CLOCK 0xA        
+#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 221200)
+#define SA11X0_PLL_CLOCK 0xB        
+#else
+#error Invalid processor clock speed
+#endif
+
+// This function is called very early on by the boot ROM (or by any ROM
+// based startup).  It's job is to initialize the hardware to a known state
+// so that eCos applications can execute properly.
+
+// This version of the code is patterned after the contribution from
+// Travis Furer (@MIT)                
+
+
+// Define macro used to diddle the LEDs during early initialization.
+// Can use r0+r1.  Argument in \x.
+
+#define CYGHWR_LED_MACRO _set_LEDS(\x)
+        
+// Initialize GPIOs
+#define GPIO_GRER (SA11X0_GPIO_RISING_EDGE_DETECT-SA11X0_GPIO_PIN_LEVEL)
+#define GPIO_GFER (SA11X0_GPIO_FALLING_EDGE_DETECT-SA11X0_GPIO_PIN_LEVEL)
+#define GPIO_GAFR (SA11X0_GPIO_ALTERNATE_FUNCTION-SA11X0_GPIO_PIN_LEVEL)
+#define GPIO_GEDR (SA11X0_GPIO_EDGE_DETECT_STATUS-SA11X0_GPIO_PIN_LEVEL)
+#define GPIO_GPDR (SA11X0_GPIO_PIN_DIRECTION-SA11X0_GPIO_PIN_LEVEL)
+#define GPIO_GPCR (SA11X0_GPIO_PIN_OUTPUT_CLEAR-SA11X0_GPIO_PIN_LEVEL)
+        .macro  _init_GPIO
+        ldr     r1,=SA11X0_GPIO_PIN_LEVEL
+        mov     r0,#0           
+        str     r0,[r1,#GPIO_GRER]      // Disable rising edge detects
+        str     r0,[r1,#GPIO_GFER]      // Disable falling edge detects
+        str     r0,[r1,#GPIO_GAFR]      // No alt. funcs. during init
+        sub     r0,r0,#1        
+        str     r0,[r1,#GPIO_GPCR]      // Force all outputs to low
+        str     r0,[r1,#GPIO_GEDR]      // Clear edge detect status
+        ldr     r0,=0x00100300  
+        str     r0,[r1,#GPIO_GPDR]      // Only LEDs outputs (for now)
+        .endm
+
+// Initialize HEX display.
+#define MCP_STAT  (SA11X0_MCP_STATUS-SA11X0_MCP_CONTROL_0)        
+#define MCP_CTRL0 (SA11X0_MCP_CONTROL_0-SA11X0_MCP_CONTROL_0)        
+#define MCP_DATA2 (SA11X0_MCP_DATA_2-SA11X0_MCP_CONTROL_0)        
+        .macro  _init_HEX_DISPLAY
+        ldr     r1, =SA11X0_MCP_CONTROL_0
+        ldr     r2, =0xFFFFFFFF
+        str     r2, [r1, #MCP_STAT]
+        ldr     r2, =0x801F
+        orr     r2, r2, #(3 << 16)
+        str     r2, [r1, #MCP_DATA2]
+        ldr     r2, =0x50000
+        str     r2, [r1, #MCP_CTRL0]
+        .endm
+
+// Display value on hex LED display
+        .macro  _set_LEDS,val
+        mov     r0,#\val
+        orr     r0,r0,#(1<<16)
+        ldr     r1,=SA11X0_MCP_DATA_2
+        str     r0,[r1]
+        .endm
+
+// Setup pin directions:
+//  inputs: all serial receive pins
+// outputs: all LCD pins, all serial transmit pins
+        .macro  _init_PERIPHERAL_PINS
+        ldr     r0,=0x00355FFF
+        ldr     r1,=SA11X0_PPC_PIN_DIRECTION
+        str     r0,[r1]
+        mov     r0,#0                           // Force initial state
+        ldr     r1,=SA11X0_PPC_PIN_STATE
+        str     r0,[r1]
+        ldr     r1,=SA11X0_PPC_PIN_ASSIGNMENT   // Disable any reassignments
+        str     r0,[r1]
+        .endm
+        
+// Set core frequency (this can take up to 150us)        
+        .macro  _set_CLOCK_FREQUENCY
+        mov     r0,#SA11X0_PLL_CLOCK
+        ldr     r1,=SA11X0_PWR_MGR_PLL_CONFIG
+        str     r0,[r1]
+        .endm
+
+// Enable clock switching (must be done after setting core frequency)
+        .macro  _enable_CLOCK_SWITCHING
+        mcr     p15,0,r1,c15,c1,2
+        .endm
+
+// Initialize memory interfaces. (ROM, SRAM, Flash, DRAM, etc)
+//
+// Note: This code has hardcoded values (taken from the uHAL
+//       code for brutus provided at the Intel StrongARM
+//       website) that are specific to the memory devices
+//       used on the Brutus board.
+//
+// Brutus memory is as follows:
+//   ROM     256K (assuming 32 bit accesses)
+//   Flash   256K (assuming 32 bit accesses)
+//   SRAM    512K
+//   DRAM     16M (4M per bank)
+//
+// From SA11X0 Manual, Section 10.7.1:
+//
+//  The following flow should be followed when coming out of
+//  reset, whether for sleep or power-up:
+//
+//    - Read boot ROM and write to memory configuration
+//      registers, but do not enable DRAM banks.
+//
+//    - If necessary, finish any DRAM power-up wait period
+//      (usually about 100us).
+//
+//    - If coming out of sleep, see Section 9.5, Power
+//      Manager on page 9-26 on how to release the nCAS and
+//      nRAS pins from their self-refresh state.
+//
+//    - If coming out of sleep, wait the DRAM-specific
+//      post-self-refresh precharge period before issuing
+//      a new DRAM transaction.
+//
+//    - If power-on reset, perform the number of
+//      initialization refreshes required by the specific
+//      DRAM part by reading disabled banks. A read from
+//      any disabled bank will refresh all four banks.
+//
+//    - Enable DRAM banks by setting MDCNFG:DE3:0.
+//
+//
+// FIXME: Values for Brutus SRAM (NOT yet supported) are:
+//  MDCAS0 = 0xCCCCCCCF
+//  MDCAS1 = 0xFFFFFFFC
+//  MDCAS2 = 0xFFFFFFFF
+//  MDCNFG = 0 //DRAM not enabled
+//
+//
+// Configure Bank 0 (ROM) and Bank 1 (Flash) in MSC0 as
+// follows:
+//
+// Bank 0:
+//                ROM type = Nonburst ROM or Flash EPROM
+//           ROM bus width = as specified on ROM_SEL pin (s11)
+//  ROM delay first access = 17 MCLK cycles
+//   ROM delay next access = 0 (unused)
+//       ROM recovery time = 2 MCLK cycles
+//
+// Bank 1:
+//                ROM type = Nonburst ROM or SRAM
+//           ROM bus width = 32 bits
+//  ROM delay first access = 17 MCLK cycles
+//   ROM delay next access = 20 MCLK cycles
+//       ROM recovery time = 1 MCLK cycles
+//
+//
+// Configure Bank 2 (SRAM) and Bank 3 (External Register)
+// in MSC1 as follows:
+//
+// Bank 2:
+//                ROM type = Nonburst ROM or SRAM
+//           ROM bus width = 32 bits
+//  ROM delay first access = 4 MCLK cycles
+//   ROM delay next access = 2 MCLK cycles
+//       ROM recovery time = 2 MCLK cycles
+//
+// Bank 3:
+//                ROM type = Nonburst ROM or SRAM
+//           ROM bus width = 32 bits
+//  ROM delay first access = 5 MCLK cycles
+//   ROM delay next access = 3 MCLK cycles
+//       ROM recovery time = 4 MCLK cycles
+//
+//
+// Enable DRAM banks 0-3 and configure for:
+//  12 row address bits (brutus has 12x8 DRAMs)
+//  CAS waveform shifted on DCLK
+//  RAS precharges for 4 MCLK cycles
+//  RAS asserts for 6 MCLK cycles during CBR
+//  Data latched 3 DCLK cycles after CAS
+//  0x400 * 4 = 4096 MCLK cycles between refreshes
+//
+#define MDCFG  (SA11X0_DRAM_CONFIGURATION-SA11X0_DRAM_CONFIGURATION)        
+#define MDCAS0 (SA11X0_DRAM0_CAS_0-SA11X0_DRAM_CONFIGURATION)        
+#define MDCAS1 (SA11X0_DRAM0_CAS_1-SA11X0_DRAM_CONFIGURATION)        
+#define MDCAS2 (SA11X0_DRAM0_CAS_2-SA11X0_DRAM_CONFIGURATION)        
+#define MSCTL0 (SA11X0_STATIC_CONTROL_0-SA11X0_DRAM_CONFIGURATION)        
+#define MSCTL1 (SA11X0_STATIC_CONTROL_1-SA11X0_DRAM_CONFIGURATION)        
+        .macro  _init_MEM_INTERFACES
+        /* Do nothing if DRAM already configured */
+        ldr     r1,=SA11X0_DRAM_CONFIGURATION
+        ldr     r1,[r1]
+        ands    r1,r1,#0xF
+        bne     2003f
+        /* Configure Memory */
+        /* Configure Waveform Registers */
+        ldr     r1,=SA11X0_DRAM_CONFIGURATION
+        ldr     r0,=0x83C1E01F
+        str     r0,[r1,#MDCAS0]
+        ldr     r0,=0x3C1E0F07
+        str     r0,[r1,#MDCAS1]
+        ldr     r0,=0xFFFFF078
+        str     r0,[r1,#MDCAS2]
+        /* Configure Static Memory Regs */
+        /*      FIXME: I think this is right? See note on page 10-11. */
+        /*             Value from uHAL was actually 13812080          */
+        ldr     r0,=0x13802080
+        ldr     r2,[r1,#MSCTL0]
+        and     r2,r2,#4        /* Extract the ROM_SEL (s11) value */
+        orr     r0,r0,r2        /* Merge in the ROM_SEL value */
+        str     r0,[r1,#MSCTL0]
+        /*      FIXME: I think this is right? See note on page 10-11. */
+        /*             Value from uHAL was actually 42210119          */
+        ldr     r0,=0x42200118
+        str     r0,[r1,#MSCTL1]
+        /* FIXME: According to the SA11X0 Manual, we need to force    */
+        /*        a certain number of refreshes here by doing reads   */
+        /*        to the disabled banks.  However, the uHAL code      */
+        /*        doesn't seem to do this, so we skip it here too     */
+        /*        for now.                                            */
+        /* Configure DRAM Registers */
+        ldr     r0,=0x0801A9BF
+        str     r0,[r1,#MDCFG]
+        /* Wait for DRAM to be ready for use (as in uHAL code) */
+        /* FIXME: why do we need to do this? */
+        mov     r0,#0x200
+2002:   subs    r0,r0,#1
+        bne     2002b
+2003:
+        .endm
+        
+        .macro  _platform_setup1
+        nop                                                               
+        nop                                                               
+        nop                                                               
+        nop                                                               
+        nop                                                               
+        nop                                                               
+        nop                                                               
+        nop                                                               
+        nop                                                               
+                                                                           
+        _init_GPIO
+        _init_HEX_DISPLAY               /* this is flaky sometimes */       
+        _init_HEX_DISPLAY               /* so do it twice just in case */   
+        _set_LEDS(15)
+                                                                           
+        _init_PERIPHERAL_PINS                                               
+        _set_LEDS(13)
+                                                                           
+        _set_CLOCK_FREQUENCY                                                
+        _enable_CLOCK_SWITCHING                                             
+        _set_LEDS(12)
+                                                                           
+        _init_MEM_INTERFACES                                                
+        _set_LEDS(11)
+                                                                           
+        // Set up a stack [for calling C code]
+        ldr     r1,=__startup_stack
+        ldr     r2,=SA11X0_RAM_BANK0_BASE
+        orr     sp,r1,r2
+
+        // Create MMU tables
+        bl      hal_mmu_init
+
+        _set_LEDS(9)
+        // Enable MMU
+        ldr     r2,=10f
+       	ldr	r1,=MMU_Control_Init|MMU_Control_M
+	mcr	MMU_CP,0,r1,MMU_Control,c0
+	mov	pc,r2    /* Change address spaces */
+	nop
+ 	nop
+	nop
+10:
+        _set_LEDS(8)
+
+        .endm
+                        
+#else // STARTUP_ROM        
+#define PLATFORM_SETUP1
+#endif
+
+/*---------------------------------------------------------------------------*/
+/* end of hal_platform_setup.h                                               */
+#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
diff --git a/packages/hal/arm/sa11x0/brutus/current/include/pkgconf/mlt_arm_sa11x0_brutus_ram.h b/packages/hal/arm/sa11x0/brutus/current/include/pkgconf/mlt_arm_sa11x0_brutus_ram.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/brutus/current/include/pkgconf/mlt_arm_sa11x0_brutus_ram.h
@@ -0,0 +1,13 @@
+// eCos memory layout - Tue Apr 04 20:19:06 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#define CYGMEM_REGION_ram (0)
+#define CYGMEM_REGION_ram_SIZE (0xBFFFFF)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+extern char CYG_LABEL_NAME (_reserved) [];
+#define CYGMEM_SECTION_reserved (CYG_LABEL_NAME (_reserved))
+#define CYGMEM_SECTION_reserved_SIZE (0x10000)
diff --git a/packages/hal/arm/sa11x0/brutus/current/include/pkgconf/mlt_arm_sa11x0_brutus_ram.ldi b/packages/hal/arm/sa11x0/brutus/current/include/pkgconf/mlt_arm_sa11x0_brutus_ram.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/brutus/current/include/pkgconf/mlt_arm_sa11x0_brutus_ram.ldi
@@ -0,0 +1,24 @@
+// eCos memory layout - Tue Apr 04 20:19:06 2000
+
+// This is a generated file - do not edit
+
+MEMORY
+{
+    ram : ORIGIN = 0, LENGTH = 0xBFFFFF
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
+    SECTION_rom_vectors (ram, 0x10000, LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTIONS_END
+}
diff --git a/packages/hal/arm/sa11x0/brutus/current/include/pkgconf/mlt_arm_sa11x0_brutus_ram.mlt b/packages/hal/arm/sa11x0/brutus/current/include/pkgconf/mlt_arm_sa11x0_brutus_ram.mlt
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/brutus/current/include/pkgconf/mlt_arm_sa11x0_brutus_ram.mlt
@@ -0,0 +1,12 @@
+version 0
+region ram 0 BFFFFF 0 !
+section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
+section rom_vectors 0 1 0 1 1 1 1 1 10000 10000 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata rodata !
+section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 4 0 1 0 1 0 1 data data !
+section data 0 4 0 1 0 1 0 1 bss bss !
+section bss 0 4 0 1 0 0 0 0 !
diff --git a/packages/hal/arm/sa11x0/brutus/current/include/pkgconf/mlt_arm_sa11x0_brutus_rom.h b/packages/hal/arm/sa11x0/brutus/current/include/pkgconf/mlt_arm_sa11x0_brutus_rom.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/brutus/current/include/pkgconf/mlt_arm_sa11x0_brutus_rom.h
@@ -0,0 +1,16 @@
+// eCos memory layout - Tue Apr 04 20:19:06 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#define CYGMEM_REGION_ram (0)
+#define CYGMEM_REGION_ram_SIZE (0xBFFFFF)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0x40000000)
+#define CYGMEM_REGION_rom_SIZE (0x40000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+extern char CYG_LABEL_NAME (_reserved) [];
+#define CYGMEM_SECTION_reserved (CYG_LABEL_NAME (_reserved))
+#define CYGMEM_SECTION_reserved_SIZE (0x8000)
diff --git a/packages/hal/arm/sa11x0/brutus/current/include/pkgconf/mlt_arm_sa11x0_brutus_rom.ldi b/packages/hal/arm/sa11x0/brutus/current/include/pkgconf/mlt_arm_sa11x0_brutus_rom.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/brutus/current/include/pkgconf/mlt_arm_sa11x0_brutus_rom.ldi
@@ -0,0 +1,25 @@
+// eCos memory layout - Tue Apr 04 20:19:06 2000
+
+// This is a generated file - do not edit
+
+MEMORY
+{
+    ram : ORIGIN = 0, LENGTH = 0xBFFFFF
+    rom : ORIGIN = 0x40000000, LENGTH = 0x40000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (rom, 0x40000000, LMA_EQ_VMA)
+    SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
+    SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table))
+    SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTIONS_END
+}
diff --git a/packages/hal/arm/sa11x0/brutus/current/include/pkgconf/mlt_arm_sa11x0_brutus_rom.mlt b/packages/hal/arm/sa11x0/brutus/current/include/pkgconf/mlt_arm_sa11x0_brutus_rom.mlt
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/brutus/current/include/pkgconf/mlt_arm_sa11x0_brutus_rom.mlt
@@ -0,0 +1,13 @@
+version 0
+region ram 0 BFFFFF 0 !
+region rom 40000000 40000 1 !
+section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
+section data 0 1 1 1 1 1 0 0 8000 bss !
+section bss 0 4 0 1 0 0 0 0 !
+section rom_vectors 0 1 0 1 1 1 1 1 40000000 40000000 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata rodata !
+section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 4 0 1 0 0 0 1 data !
diff --git a/packages/hal/arm/sa11x0/brutus/current/src/brutus_misc.c b/packages/hal/arm/sa11x0/brutus/current/src/brutus_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/brutus/current/src/brutus_misc.c
@@ -0,0 +1,227 @@
+//==========================================================================
+//
+//      brutus_misc.c
+//
+//      HAL misc board support code for StrongARM SA1110/Brutus
+//
+//==========================================================================
+//####COPYRIGHTBEGIN####
+//
+// -------------------------------------------
+// The contents of this file are subject to the Red Hat eCos Public License
+// Version 1.1 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://www.redhat.com/
+//
+// Software distributed under the License is distributed on an "AS IS"
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the
+// License for the specific language governing rights and limitations under
+// the License. 
+//
+// The Original Code is eCos - Embedded Configurable Operating System,
+// released September 30, 1998.
+//
+// The Initial Developer of the Original Code is Red Hat.
+// Portions created by Red Hat are
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
+// All Rights Reserved.
+// -------------------------------------------
+//
+//####COPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: hmt
+//               Travis C. Furrer <furrer@mit.edu>
+// Date:         2000-05-21
+// Purpose:      HAL board support
+// Description:  Implementations of HAL board interfaces
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_arch.h>           // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h>           // Interrupt names
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_sa11x0.h>         // Hardware definitions
+#include <cyg/hal/brutus.h>             // Platform specifics
+
+#include <cyg/infra/diag.h>             // diag_printf
+
+// -------------------------------------------------------------------------
+// MMU initialization:
+// 
+// These structures are laid down in memory to define the translation
+// table.
+// 
+
+/*
+ * SA-1100 Translation Table Base Bit Masks */
+#define ARM_TRANSLATION_TABLE_MASK               0xFFFFC000
+
+/*
+ * SA-1100 Domain Access Control Bit Masks
+ */
+#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num)    (0x0 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_CLIENT(domain_num)       (0x1 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_MANAGER(domain_num)      (0x3 << (domain_num)*2)
+
+struct ARM_MMU_FIRST_LEVEL_FAULT {
+    int id : 2;
+    int sbz : 30;
+};
+#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
+
+struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
+    int id : 2;
+    int imp : 2;
+    int domain : 4;
+    int sbz : 1;
+    int base_address : 23;
+};
+#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
+
+struct ARM_MMU_FIRST_LEVEL_SECTION {
+    int id : 2;
+    int b : 1;
+    int c : 1;
+    int imp : 1;
+    int domain : 4;
+    int sbz0 : 1;
+    int ap : 2;
+    int sbz1 : 8;
+    int base_address : 12;
+};
+#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
+
+struct ARM_MMU_FIRST_LEVEL_RESERVED {
+    int id : 2;
+    int sbz : 30;
+};
+#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
+
+#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
+   (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
+
+#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
+
+#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base,              \
+                        cacheable, bufferable, perm)                      \
+    CYG_MACRO_START                                                       \
+        register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc;               \
+                                                                          \
+        desc.word = 0;                                                    \
+        desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID;                 \
+        desc.section.domain = 0;                                          \
+        desc.section.c = (cacheable);                                     \
+        desc.section.b = (bufferable);                                    \
+        desc.section.ap = (perm);                                         \
+        desc.section.base_address = (actual_base);                        \
+        *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
+                            = desc.word;                                  \
+    CYG_MACRO_END
+
+#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access)      \
+    { int i; int j = abase; int k = vbase;                         \
+      for (i = size; i > 0 ; i--,j++,k++)                          \
+      {                                                            \
+        ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access);      \
+      }                                                            \
+    }
+
+union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
+    unsigned long word;
+    struct ARM_MMU_FIRST_LEVEL_FAULT fault;
+    struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
+    struct ARM_MMU_FIRST_LEVEL_SECTION section;
+    struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
+};
+
+#define ARM_UNCACHEABLE                         0
+#define ARM_CACHEABLE                           1
+#define ARM_UNBUFFERABLE                        0
+#define ARM_BUFFERABLE                          1
+
+#define ARM_ACCESS_PERM_NONE_NONE               0
+#define ARM_ACCESS_PERM_RO_NONE                 0
+#define ARM_ACCESS_PERM_RO_RO                   0
+#define ARM_ACCESS_PERM_RW_NONE                 1
+#define ARM_ACCESS_PERM_RW_RO                   2
+#define ARM_ACCESS_PERM_RW_RW                   3
+
+void
+hal_mmu_init(void)
+{
+    unsigned long ttb_base = SA11X0_RAM_BANK0_BASE + 0x4000;
+    unsigned long i;
+
+    /*
+     * Set the TTB register
+     */
+    asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+
+    /*
+     * Set the Domain Access Control Register
+     */
+    i = ARM_ACCESS_TYPE_MANAGER(0)    | 
+        ARM_ACCESS_TYPE_NO_ACCESS(1)  |
+        ARM_ACCESS_TYPE_NO_ACCESS(2)  |
+        ARM_ACCESS_TYPE_NO_ACCESS(3)  |
+        ARM_ACCESS_TYPE_NO_ACCESS(4)  |
+        ARM_ACCESS_TYPE_NO_ACCESS(5)  |
+        ARM_ACCESS_TYPE_NO_ACCESS(6)  |
+        ARM_ACCESS_TYPE_NO_ACCESS(7)  |
+        ARM_ACCESS_TYPE_NO_ACCESS(8)  |
+        ARM_ACCESS_TYPE_NO_ACCESS(9)  |
+        ARM_ACCESS_TYPE_NO_ACCESS(10) |
+        ARM_ACCESS_TYPE_NO_ACCESS(11) |
+        ARM_ACCESS_TYPE_NO_ACCESS(12) |
+        ARM_ACCESS_TYPE_NO_ACCESS(13) |
+        ARM_ACCESS_TYPE_NO_ACCESS(14) |
+        ARM_ACCESS_TYPE_NO_ACCESS(15);
+    asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+    /*
+     * First clear all TT entries - ie Set them to Faulting
+     */
+    memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+
+    /*               Actual  Virtual  Size   Attributes                                                    Function  */
+    /*		     Base     Base     MB      cached?           buffered?        access permissions                 */
+    /*             xxx00000  xxx00000                                                                                */
+    X_ARM_MMU_SECTION(0x000,  0x400,     1,  ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* Boot flash ROMspace */
+    X_ARM_MMU_SECTION(0x080,  0x080,     4,  ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* Application flash ROM */
+    X_ARM_MMU_SECTION(0x100,  0x100,     1,  ARM_CACHEABLE,   ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Static RAM - 512K */
+    X_ARM_MMU_SECTION(0x180,  0x180,     1,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Static select 3 */
+    X_ARM_MMU_SECTION(0x200,  0x200,   256,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA Socket 0 */
+    X_ARM_MMU_SECTION(0x300,  0x300,   256,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA Sockets 1 */
+    X_ARM_MMU_SECTION(0x800,  0x800, 0x400,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* StrongARM(R) Registers */
+    X_ARM_MMU_SECTION(0xC00,  0x000,     4,  ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 0 */
+    X_ARM_MMU_SECTION(0xC80,  0x004,     4,  ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 1 */
+    X_ARM_MMU_SECTION(0xD00,  0x008,     4,  ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 2 */
+    X_ARM_MMU_SECTION(0xD80,  0x00C,     4,  ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 3 */
+    X_ARM_MMU_SECTION(0xC00,  0xC00,   256,  ARM_UNCACHEABLE, ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* DRAM Banks - raw access */
+    X_ARM_MMU_SECTION(0xE00,  0xE00,   128,  ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* Zeros (Cache Clean) Bank */
+
+}
+
+//
+// Platform specific initialization
+//
+
+void
+plf_hardware_init(void)
+{
+}
diff --git a/packages/hal/arm/sa11x0/var/current/ChangeLog b/packages/hal/arm/sa11x0/var/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/var/current/ChangeLog
@@ -0,0 +1,113 @@
+2000-06-30  Jesper Skov  <jskov@redhat.com>
+
+	* src/hal_diag.c: calling i/f macro changes.
+
+2000-06-28  Jesper Skov  <jskov@redhat.com>
+
+	* cdl/hal_arm_sa11x0.cdl: 
+	* include/plf_stub.h:
+	* src/plf_stub.c: [deleted]
+	Stub uses vector table for all IO.
+	
+	* src/sa11x0_misc.c: Fix compiler warning.
+
+2000-06-27  Jesper Skov  <jskov@redhat.com>
+
+	* src/hal_diag.c: Some fixes and code layout changes (Gary
+	Thomas).
+
+	* src/hal_diag.c:
+	* include/hal_diag.h:
+	* include/hal_sa11x0.h:
+	Changed to initialize all procs tables. Added timeout getc, and
+	proper debug channel switch behavior.
+
+2000-06-24  Gary Thomas  <gthomas@redhat.com>
+
+	* src/sa11x0_misc.c (hal_clock_reset): Add code to compensate for
+	clock drift since this hardware does not reset on interrupts.
+	(hal_clock_read): Also adjust the value returned here for same reason.
+
+2000-06-22  Gary Thomas  <gthomas@redhat.com>
+
+	* src/hal_diag.c (hal_diag_write_char): 
+	Fix typo: CYGINT_HAL_GDB_PORT_VECTOR to be CYGHWR_HAL_GDB_PORT_VECTOR
+	
+2000-06-19  Gary Thomas  <gthomas@redhat.com>
+
+	* include/hal_diag.h: 
+	* include/plf_stub.h: 
+	* src/hal_diag.c: 
+	* src/sa11x0_misc.c: Update for virtual vector (debug) support.
+
+2000-06-12  Gary Thomas  <gthomas@redhat.com>
+
+	* src/hal_diag.c: Fix baud rates for 960,19200.  Take out "announce"
+	string in ROM mode.
+
+2000-06-05  Gary Thomas  <gthomas@redhat.com>
+
+	* src/plf_stub.c: 
+	* include/plf_stub.h: 'sa1100' shared items renamed to 'sa11x0'.
+
+	* src/sa11x0_misc.c (hal_IRQ_handler): 
+	(hal_interrupt_mask): 
+	(hal_interrupt_unmask): 
+	(hal_interrupt_acknowledge): 
+	(hal_interrupt_configure): Complete support for GPIO interrupts.  
+	Some of these are direct, others are grouped and the code needs 
+	to handle both.  Also update support for GPIO edge detect interrupt 
+	circuitry.
+
+2000-06-04  Gary Thomas  <gthomas@redhat.com>
+
+	* include/hal_cache.h: 
+	* src/hal_diag.c: 
+	* src/sa11x0_misc.c: Renaming of 'sa1100' shared stuff to be
+	'sa11x0'.
+	
+	* include/hal_sa11x0.h: Renamed from 'hal_sa1100.h'.
+
+2000-06-01  Gary Thomas  <gthomas@redhat.com>
+
+	* src/sa11x0_misc.c: Enable caches.
+
+	* include/hal_sa1100.h: Misc cleanups and additions necessary for
+	ROM startup mode.
+
+2000-05-10  Gary Thomas  <gthomas@redhat.com>
+
+	* current/src/plf_stub.c:
+	* current/src/hal_diag.c:
+	* current/src/sa11x0_misc.c: 
+	* current/include/hal_diag.h: 
+	* current/include/hal_sa1100.h: 
+	* current/include/hal_cache.h: 
+	* current/include/plf_stub.h: 
+	* current/cdl/hal_arm_sa11x0.cdl: New file(s).
+
+//===========================================================================
+//####COPYRIGHTBEGIN####
+//                                                                          
+// -------------------------------------------                              
+// The contents of this file are subject to the Red Hat eCos Public License 
+// Version 1.1 (the "License"); you may not use this file except in         
+// compliance with the License.  You may obtain a copy of the License at    
+// http://www.redhat.com/                                                   
+//                                                                          
+// Software distributed under the License is distributed on an "AS IS"      
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+// License for the specific language governing rights and limitations under 
+// the License.                                                             
+//                                                                          
+// The Original Code is eCos - Embedded Configurable Operating System,      
+// released September 30, 1998.                                             
+//                                                                          
+// The Initial Developer of the Original Code is Red Hat.                   
+// Portions created by Red Hat are                                          
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+// All Rights Reserved.                                                     
+// -------------------------------------------                              
+//                                                                          
+//####COPYRIGHTEND####
+//===========================================================================
diff --git a/packages/hal/arm/sa11x0/var/current/cdl/hal_arm_sa11x0.cdl b/packages/hal/arm/sa11x0/var/current/cdl/hal_arm_sa11x0.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/var/current/cdl/hal_arm_sa11x0.cdl
@@ -0,0 +1,93 @@
+# ====================================================================
+#
+#      hal_arm_sa11x0.cdl
+#
+#      ARM SA11x0 architectural HAL package configuration data
+#
+# ====================================================================
+#####COPYRIGHTBEGIN####
+#                                                                          
+# -------------------------------------------                              
+# The contents of this file are subject to the Red Hat eCos Public License 
+# Version 1.1 (the "License"); you may not use this file except in         
+# compliance with the License.  You may obtain a copy of the License at    
+# http://www.redhat.com/                                                   
+#                                                                          
+# Software distributed under the License is distributed on an "AS IS"      
+# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+# License for the specific language governing rights and limitations under 
+# the License.                                                             
+#                                                                          
+# The Original Code is eCos - Embedded Configurable Operating System,      
+# released September 30, 1998.                                             
+#                                                                          
+# The Initial Developer of the Original Code is Red Hat.                   
+# Portions created by Red Hat are                                          
+# Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+# All Rights Reserved.                                                     
+# -------------------------------------------                              
+#                                                                          
+#####COPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      gthomas
+# Original data:  gthomas
+# Contributors:
+# Date:           2000-05-08
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+cdl_package CYGPKG_HAL_ARM_SA11X0 {
+    display       "ARM SA11X0 architecture"
+    parent        CYGPKG_HAL_ARM
+    hardware
+    include_dir   cyg/hal
+    define_header hal_arm_sa11x0.h
+    description   "
+        This HAL variant package provides generic
+        support for the Intel StrongARM SA11x0 processors. It is also
+        necessary to select a specific target platform HAL
+        package."
+
+
+    compile       hal_diag.c sa11x0_misc.c
+
+    cdl_option CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK {
+        display       "Processor clock rate"
+        flavor        data
+        legal_values  59000 73700 88500 103200 118000 132700 147500 162200 176900 191700 206400 221200
+        default_value 221200
+        description   "
+           The SA-1100 processor can run at various frequencies.
+           These values are expressed in KHz.  Note that there are
+           several steppings of the SA-1100 rated to run at different
+           maximum frequencies.  Check the specs to make sure that your
+           particular processor can run at the rate you select here."
+    }
+
+    # Real-time clock/counter specifics
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants"
+        flavor        none
+        no_define
+    
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            calculated    1000000000
+        }
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            calculated    100
+        }
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            calculated    36864        ;# Clock for OS Timer is 3.6864MHz
+        }
+    }
+
+}
diff --git a/packages/hal/arm/sa11x0/var/current/include/hal_cache.h b/packages/hal/arm/sa11x0/var/current/include/hal_cache.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/var/current/include/hal_cache.h
@@ -0,0 +1,355 @@
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+//      hal_cache.h
+//
+//      HAL cache control API
+//
+//=============================================================================
+//####COPYRIGHTBEGIN####
+//
+// -------------------------------------------
+// The contents of this file are subject to the Red Hat eCos Public License
+// Version 1.1 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://www.redhat.com/
+//
+// Software distributed under the License is distributed on an "AS IS"
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the
+// License for the specific language governing rights and limitations under
+// the License.
+//
+// The Original Code is eCos - Embedded Configurable Operating System,
+// released September 30, 1998.
+//
+// The Initial Developer of the Original Code is Red Hat.
+// Portions created by Red Hat are
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
+// All Rights Reserved.
+// -------------------------------------------
+//
+//####COPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   gthomas
+// Contributors:hmt
+//              Travis C. Furrer <furrer@mit.edu>
+// Date:        2000-05-08
+// Purpose:     Cache control API
+// Description: The macros defined here provide the HAL APIs for handling
+//              cache control operations.
+// Usage:
+//              #include <cyg/hal/hal_cache.h>
+//              ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_sa11x0.h>
+#include <cyg/hal/hal_mmu.h>
+
+//-----------------------------------------------------------------------------
+// Cache dimensions
+
+#define HAL_ICACHE_SIZE                 SA11X0_ICACHE_SIZE
+#define HAL_ICACHE_LINE_SIZE            SA11X0_ICACHE_LINESIZE_BYTES
+#define HAL_ICACHE_WAYS                 SA11X0_ICACHE_WAYS
+#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
+
+#define HAL_DCACHE_SIZE                 SA11X0_DCACHE_SIZE
+#define HAL_DCACHE_LINE_SIZE            SA11X0_DCACHE_LINESIZE_BYTES
+#define HAL_DCACHE_WAYS                 SA11X0_DCACHE_WAYS
+#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
+
+// FIXME: much of the code below should make better use of
+// the definitions from hal_mmu.h
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()                                             \
+CYG_MACRO_START                                                         \
+    asm volatile (                                                      \
+        "mrc  p15,0,r1,c1,c0,0;"                                        \
+        "orr  r1,r1,#0x1000;"                                           \
+        "orr  r1,r1,#0x0003;" /* enable ICache (also ensures   */       \
+                              /* that MMU and alignment faults */       \
+                              /* are enabled)                  */       \
+        "mcr  p15,0,r1,c1,c0,0"                                         \
+        :                                                               \
+        :                                                               \
+        : "r1" /* Clobber list */                                       \
+        );                                                              \
+CYG_MACRO_END
+
+// Disable the instruction cache (and invalidate it, required semanitcs)
+#define HAL_ICACHE_DISABLE()                                            \
+CYG_MACRO_START                                                         \
+    asm volatile (                                                      \
+        "mrc    p15,0,r1,c1,c0,0;"                                      \
+        "bic    r1,r1,#0x1000;" /* disable ICache (but not MMU, etc) */ \
+        "mcr    p15,0,r1,c1,c0,0;"                                      \
+        "mcr    p15,0,r1,c7,c5,0;"  /* flush ICache */                  \
+        "nop;" /* next few instructions may be via cache    */          \
+        "nop;"                                                          \
+        "nop;"                                                          \
+        "nop;"                                                          \
+        "nop;"                                                          \
+        "nop"                                                           \
+        :                                                               \
+        :                                                               \
+        : "r1" /* Clobber list */                                       \
+        );                                                              \
+CYG_MACRO_END
+
+// Query the state of the instruction cache
+#define HAL_ICACHE_IS_ENABLED(_state_)                                   \
+CYG_MACRO_START                                                          \
+    register cyg_uint32 reg;                                             \
+    asm volatile ("mrc  p15,0,%0,c1,c0,0"                                \
+                  : "=r"(reg)                                            \
+                  :                                                      \
+        );                                                               \
+    (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */     \
+CYG_MACRO_END
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL()                                     \
+CYG_MACRO_START                                                         \
+    /* this macro can discard dirty cache lines (N/A for ICache) */     \
+    asm volatile (                                                      \
+        "mcr    p15,0,r1,c7,c5,0;"  /* flush ICache */                  \
+        "mcr    p15,0,r1,c8,c5,0;"  /* flush ITLB only */               \
+        "nop;" /* next few instructions may be via cache    */          \
+        "nop;"                                                          \
+        "nop;"                                                          \
+        "nop;"                                                          \
+        "nop;"                                                          \
+        "nop;"                                                          \
+        :                                                               \
+        :                                                               \
+        );                                                              \
+CYG_MACRO_END
+
+// Synchronize the contents of the cache with memory.
+// (which includes flushing out pending writes)
+#define HAL_ICACHE_SYNC()                                       \
+CYG_MACRO_START                                                 \
+    HAL_DCACHE_SYNC(); /* ensure data gets to RAM */            \
+    HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */       \
+CYG_MACRO_END
+
+// Set the instruction cache refill burst size
+//#define HAL_ICACHE_BURST_SIZE(_size_)
+// This feature is not available on the SA11X0.
+
+// Load the contents of the given address range into the instruction cache
+// and then lock the cache so that it stays there.
+//#define HAL_ICACHE_LOCK(_base_, _size_)
+// This feature is not available on the SA11X0.
+
+// Undo a previous lock operation
+//#define HAL_ICACHE_UNLOCK(_base_, _size_)
+// This feature is not available on the SA11X0.
+
+// Unlock entire cache
+//#define HAL_ICACHE_UNLOCK_ALL()
+// This feature is not available on the SA11X0.
+
+//-----------------------------------------------------------------------------
+// Instruction cache line control
+
+// Invalidate cache lines in the given range without writing to memory.
+//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
+// This feature is not available on the SA11X0.
+
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()                                             \
+CYG_MACRO_START                                                         \
+    asm volatile (                                                      \
+        "mrc  p15,0,r1,c1,c0,0;"                                        \
+        "orr  r1,r1,#0x000F;" /* enable DCache (also ensures    */      \
+                              /* the MMU, alignment faults, and */      \
+                              /* write buffer are enabled)      */      \
+        "mcr  p15,0,r1,c1,c0,0"                                         \
+        :                                                               \
+        :                                                               \
+        : "r1" /* Clobber list */                                       \
+        );                                                              \
+CYG_MACRO_END
+
+// Disable the data cache (and invalidate it, required semanitcs)
+#define HAL_DCACHE_DISABLE()                                            \
+CYG_MACRO_START                                                         \
+    asm volatile (                                                      \
+        "mrc  p15,0,r1,c1,c0,0;"                                        \
+        "bic  r1,r1,#0x000C;" /* disable DCache AND write buffer  */    \
+                              /* but not MMU and alignment faults */    \
+        "mcr  p15,0,r1,c1,c0,0;"                                        \
+        "mcr  p15,0,r1,c7,c6,0" /* clear data cache */                  \
+        :                                                               \
+        :                                                               \
+        : "r1" /* Clobber list */                                       \
+        );                                                              \
+CYG_MACRO_END
+
+// Query the state of the data cache
+#define HAL_DCACHE_IS_ENABLED(_state_)                                   \
+CYG_MACRO_START                                                          \
+    register int reg;                                                    \
+    asm volatile ("mrc  p15,0,%0,c1,c0,0;"                               \
+                  : "=r"(reg)                                            \
+                  :                                                      \
+        );                                                               \
+    (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */           \
+CYG_MACRO_END
+
+// Flush the entire dcache (and then both TLBs, just in case)
+#define HAL_DCACHE_INVALIDATE_ALL()                                     \
+CYG_MACRO_START                                                         \
+    /* this macro can discard dirty cache lines. */                     \
+    asm volatile ("mcr    p15,0,r1,c7,c6,0;"                            \
+                  "mcr    p15,0,r1,c8,c7,0;"                            \
+                  : : );                                                \
+CYG_MACRO_END
+
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC()                                               \
+CYG_MACRO_START                                                         \
+    /* This is slightly naff in that the only way to force a dirty */   \
+    /* line out is by loading other data into its slot, so         */   \
+    /* invalidating that slot.                                     */   \
+    asm volatile (                                                      \
+        "mov    r0, #0xE0000000;" /* SA11X0 zeros bank (128Mb) */       \
+        "add    r1, r0, #0x2000;" /* We read 8kB of it */               \
+ "667: "                                                                \
+        "ldr    r2, [r0], #32;"                                         \
+        "teq    r1, r0;"                                                \
+        "bne    667b;"                                                  \
+        "mcr    p15,0,r0,c7,c6,0;"  /* flush DCache */                  \
+        "mcr    p15,0,r0,c7,c10,4;" /* and drain the write buffer */    \
+        "nop;"  /* wait for the writebacks to occur...     */           \
+        "nop;"                                                          \
+        "nop;"                                                          \
+        "nop;"                                                          \
+        "nop;"                                                          \
+        "nop;"                                                          \
+        :                                                               \
+        :                                                               \
+        : "r0","r1","r2" /* Clobber list */                             \
+        );                                                              \
+CYG_MACRO_END
+
+// Set the data cache refill burst size
+//#define HAL_DCACHE_BURST_SIZE(_size_)
+// This feature is not available on the SA11X0.
+
+// Set the data cache write mode
+//#define HAL_DCACHE_WRITE_MODE( _mode_ )
+// This feature is not available on the SA11X0.
+
+#define HAL_DCACHE_WRITETHRU_MODE       0
+#define HAL_DCACHE_WRITEBACK_MODE       1
+
+// Get the current writeback mode - or only writeback mode if fixed
+#define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START           \
+    _mode_ = HAL_DCACHE_WRITEBACK_MODE;                                 \
+CYG_MACRO_END
+
+// Load the contents of the given address range into the data cache
+// and then lock the cache so that it stays there.
+//#define HAL_DCACHE_LOCK(_base_, _size_)
+// This feature is not available on the SA11X0.
+
+// Undo a previous lock operation
+//#define HAL_DCACHE_UNLOCK(_base_, _size_)
+// This feature is not available on the SA11X0.
+
+// Unlock entire cache
+//#define HAL_DCACHE_UNLOCK_ALL()
+// This feature is not available on the SA11X0.
+
+//-----------------------------------------------------------------------------
+// Data cache line control
+
+// Allocate cache lines for the given address range without reading its
+// contents from memory.
+//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
+// This feature is not available on the SA11X0.
+
+// Write dirty cache lines to memory and invalidate the cache entries
+// for the given address range.
+// ---- this seems not to work despite the documentation ---
+//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
+//CYG_MACRO_START
+//    HAL_DCACHE_STORE( _base_ , _size_ );
+//    HAL_DCACHE_INVALIDATE( _base_ , _size_ );
+//CYG_MACRO_END
+
+// Invalidate cache lines in the given range without writing to memory.
+// ---- this seems not to work despite the documentation ---
+//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
+//CYG_MACRO_START
+//    register int addr, enda;
+//    for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
+//              enda = (int)(_base_) + (_size_);
+//          addr < enda ;
+//          addr += HAL_DCACHE_LINE_SIZE )
+//    {
+//        asm volatile (
+//                      "mcr  p15,0,%0,c7,c6,1;" /* flush entry away */
+//                      :
+//                      : "r"(addr)
+//                      : "memory"
+//            );
+//    }
+//CYG_MACRO_END
+                          
+// Write dirty cache lines to memory for the given address range.
+// ---- this seems not to work despite the documentation ---
+//#define HAL_DCACHE_STORE( _base_ , _size_ )
+//CYG_MACRO_START
+//    register int addr, enda;
+//    for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
+//              enda = (int)(_base_) + (_size_);
+//          addr < enda ;
+//          addr += HAL_DCACHE_LINE_SIZE )
+//    {
+//        asm volatile ("mcr  p15,0,%0,c7,c10,1;" /* push entry to RAM */
+//                      :
+//                      : "r"(addr)
+//                      : "memory"
+//            );
+//    }
+//CYG_MACRO_END
+
+// Preread the given range into the cache with the intention of reading
+// from it later.
+//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
+// This feature is available on the SA11X0, but due to tricky
+// coherency issues with the read buffer (see SA11X0 developer's
+// manual page 6-7) we don't bother to implement it here.
+
+// Preread the given range into the cache with the intention of writing
+// to it later.
+//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
+// This feature is not available on the SA11X0.
+
+// Allocate and zero the cache lines associated with the given range.
+//#define HAL_DCACHE_ZERO( _base_ , _size_ )
+// This feature is not available on the SA11X0.
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
diff --git a/packages/hal/arm/sa11x0/var/current/include/hal_diag.h b/packages/hal/arm/sa11x0/var/current/include/hal_diag.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/var/current/include/hal_diag.h
@@ -0,0 +1,80 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+
+/*=============================================================================
+//
+//      hal_diag.h
+//
+//      HAL Support for Kernel Diagnostic Routines
+//
+//=============================================================================
+//####COPYRIGHTBEGIN####
+//                                                                          
+// -------------------------------------------                              
+// The contents of this file are subject to the Red Hat eCos Public License 
+// Version 1.1 (the "License"); you may not use this file except in         
+// compliance with the License.  You may obtain a copy of the License at    
+// http://www.redhat.com/                                                   
+//                                                                          
+// Software distributed under the License is distributed on an "AS IS"      
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+// License for the specific language governing rights and limitations under 
+// the License.                                                             
+//                                                                          
+// The Original Code is eCos - Embedded Configurable Operating System,      
+// released September 30, 1998.                                             
+//                                                                          
+// The Initial Developer of the Original Code is Red Hat.                   
+// Portions created by Red Hat are                                          
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+// All Rights Reserved.                                                     
+// -------------------------------------------                              
+//                                                                          
+//####COPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, gthomas
+// Contributors: nickg, gthomas
+// Date:         1998-09-11
+// Purpose:      HAL Support for Kernel Diagnostic Routines
+// Description:  Diagnostic routines for use during kernel development.
+// Usage:        #include <cyg/hal/hal_diag.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_if.h>
+
+/*---------------------------------------------------------------------------*/
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+#include <cyg/hal/hal_if.h>
+
+#define HAL_DIAG_INIT()          hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_)  hal_if_diag_read_char(&_c_)
+
+#else
+
+/*---------------------------------------------------------------------------*/
+/* functions implemented in hal_diag.c                                       */
+
+externC void hal_diag_init(void);
+externC void hal_diag_write_char(char c);
+externC void hal_diag_read_char(char *c);
+
+#define HAL_DIAG_INIT()          hal_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_)  hal_diag_read_char(&_c_)
+
+#endif
+
+/*---------------------------------------------------------------------------*/
+/* end of hal_diag.h                                                         */
+#endif /* CYGONCE_HAL_DIAG_H */
diff --git a/packages/hal/arm/sa11x0/var/current/include/hal_sa11x0.h b/packages/hal/arm/sa11x0/var/current/include/hal_sa11x0.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/var/current/include/hal_sa11x0.h
@@ -0,0 +1,705 @@
+//==========================================================================
+//
+//      hal_sa11x0.h
+//
+//      HAL misc board support definitions for StrongARM SA11x0
+//
+//==========================================================================
+//####COPYRIGHTBEGIN####
+//
+// -------------------------------------------
+// The contents of this file are subject to the Red Hat eCos Public License
+// Version 1.1 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://www.redhat.com/
+//
+// Software distributed under the License is distributed on an "AS IS"
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the
+// License for the specific language governing rights and limitations under
+// the License. 
+//
+// The Original Code is eCos - Embedded Configurable Operating System,
+// released September 30, 1998.
+//
+// The Initial Developer of the Original Code is Red Hat.
+// Portions created by Red Hat are
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
+// All Rights Reserved.
+// -------------------------------------------
+//
+//####COPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+// Date:         2000-04-04
+// Purpose:      Platform register definitions
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#ifndef __HAL_SA11X0_H__
+#define __HAL_SA11X0_H__ 1
+
+#ifdef __ASSEMBLER__
+
+#define REG8_VAL(a)  (a)
+#define REG16_VAL(a) (a)
+#define REG32_VAL(a) (a)
+
+#define REG8_PTR(a)  (a)
+#define REG16_PTR(a) (a)
+#define REG32_PTR(a) (a)
+
+#else /* __ASSEMBLER__ */
+
+#define REG8_VAL(a)  ((unsigned char)(a))
+#define REG16_VAL(a) ((unsigned short)(a))
+#define REG32_VAL(a) ((unsigned int)(a))
+
+#define REG8_PTR(a)  ((volatile unsigned char *)(a))
+#define REG16_PTR(a) ((volatile unsigned long *)(a))
+#define REG32_PTR(a) ((volatile unsigned long *)(a))
+
+#endif /* __ASSEMBLER__ */
+
+/*
+ * SA11X0 Default Memory Layout Definitions
+ */
+#define SA11X0_ROM_BANK0_BASE                    (0)
+#define SA11X0_ROM_BANK1_BASE                    (SA11X0_ROM_BANK0_BASE + SZ_128M)
+#define SA11X0_ROM_BANK2_BASE                    (SA11X0_ROM_BANK1_BASE + SZ_128M)
+#define SA11X0_ROM_BANK3_BASE                    (SA11X0_ROM_BANK2_BASE + SZ_128M)
+
+#define SA11X0_RAM_BANK0_BASE                    (0xC0000000)
+#define SA11X0_RAM_BANK1_BASE                    (SA11X0_RAM_BANK0_BASE + SZ_128M)
+#define SA11X0_RAM_BANK2_BASE                    (SA11X0_RAM_BANK1_BASE + SZ_128M)
+#define SA11X0_RAM_BANK3_BASE                    (SA11X0_RAM_BANK2_BASE + SZ_128M)
+
+#define SA11X0_ZEROS_BANK_BASE                   (SA11X0_RAM_BANK3_BASE + SZ_128M)
+
+/*
+ * SA11X0 Register Definitions
+ */
+#define SA11X0_REGISTER_BASE                     0x80000000
+#define SA11X0_REGISTER(x)                       REG32_PTR(SA11X0_REGISTER_BASE + (x))
+
+/*
+ * SA-1100 Cache and MMU Definitions
+ */
+#define SA11X0_ICACHE_SIZE                       0x4000  // 16K
+#define SA11X0_DCACHE_SIZE                       0x2000  // 8K
+#define SA11X0_ICACHE_LINESIZE_BYTES             32
+#define SA11X0_DCACHE_LINESIZE_BYTES             32
+#define SA11X0_ICACHE_LINESIZE_WORDS             8
+#define SA11X0_DCACHE_LINESIZE_WORDS             8
+#define SA11X0_ICACHE_WAYS                       32
+#define SA11X0_DCACHE_WAYS                       32
+#define SA11X0_ICACHE_LINE_BASE(p)               REG32_PTR((unsigned long)(p) & \
+                                                           ~(SA11X0_ICACHE_LINESIZE_BYTES - 1))
+#define SA11X0_DCACHE_LINE_BASE(p)               REG32_PTR((unsigned long)(p) & \
+                                                           ~(SA11X0_DCACHE_LINESIZE_BYTES - 1))
+
+/*
+ * SA-1100 Coprocessor 15 Extensions Register Definitions
+ */
+#ifdef __ASSEMBLER__
+#  define SA11X0_READ_PROCESS_ID_REGISTER        c13
+#  define SA11X0_WRITE_PROCESS_ID_REGISTER       c13
+#  define SA11X0_READ_BREAKPOINT_REGISTER        c14
+#  define SA11X0_WRITE_BREAKPOINT_REGISTER       c14
+#  define SA11X0_TEST_CLOCK_AND_IDLE_REGISTER    c15
+#else /* __ASSEMBLER__ */
+#  define SA11X0_READ_PROCESS_ID_REGISTER        "c13"
+#  define SA11X0_WRITE_PROCESS_ID_REGISTER       "c13"
+#  define SA11X0_READ_BREAKPOINT_REGISTER        "c14"
+#  define SA11X0_WRITE_BREAKPOINT_REGISTER       "c14"
+#  define SA11X0_TEST_CLOCK_AND_IDLE_REGISTER    "c15"
+#endif /* __ASSEMBLER__ */
+
+/*
+ * SA-1100 Process ID Virtual Address Mapping Definitions
+ */
+#ifdef __ASSEMBLER__
+#  define SA11X0_ACCESS_PROC_ID_REGISTER_OPCODE  0x0
+#  define SA11X0_ACCESS_PROC_ID_REGISTER_RM      c0
+#else /* __ASSEMBLER__ */
+#  define SA11X0_ACCESS_PROC_ID_REGISTER_OPCODE  "0x0"
+#  define SA11X0_ACCESS_PROC_ID_REGISTER_RM      "c0"
+#endif /* __ASSEMBLER__ */
+
+#define SA11X0_PROCESS_ID_PID_MASK               0x7E000000
+
+/*
+ * SA-1100 Debug Support Definitions
+ */
+#ifdef __ASSEMBLER__
+#  define SA11X0_ACCESS_DBAR_OPCODE              0x0
+#  define SA11X0_ACCESS_DBAR_RM                  c0
+#  define SA11X0_ACCESS_DBVR_OPCODE              0x0
+#  define SA11X0_ACCESS_DBVR_RM                  c1
+#  define SA11X0_ACCESS_DBMR_OPCODE              0x0
+#  define SA11X0_ACCESS_DBMR_RM                  c2
+#  define SA11X0_LOAD_DBCR_OPCODE                0x0
+#  define SA11X0_LOAD_DBCR_RM                    c3
+#else /* __ASSEMBLER__ */
+#  define SA11X0_ACCESS_DBAR_OPCODE              "0x0"
+#  define SA11X0_ACCESS_DBAR_RM                  "c0"
+#  define SA11X0_ACCESS_DBVR_OPCODE              "0x0"
+#  define SA11X0_ACCESS_DBVR_RM                  "c1"
+#  define SA11X0_ACCESS_DBMR_OPCODE              "0x0"
+#  define SA11X0_ACCESS_DBMR_RM                  "c2"
+#  define SA11X0_LOAD_DBCR_OPCODE                "0x0"
+#  define SA11X0_LOAD_DBCR_RM                    "c3"
+#endif /* __ASSEMBLER__ */
+
+#define SA11X0_DBCR_LOAD_WATCH_DISABLED          0x00000000
+#define SA11X0_DBCR_LOAD_WATCH_ENABLED           0x00000001
+#define SA11X0_DBCR_LOAD_WATCH_MASK              0x00000001
+#define SA11X0_DBCR_STORE_ADDRESS_WATCH_DISABLED 0x00000000
+#define SA11X0_DBCR_STORE_ADDRESS_WATCH_ENABLED  0x00000002
+#define SA11X0_DBCR_STORE_ADDRESS_WATCH_MASK     0x00000002
+#define SA11X0_DBCR_STORE_DATA_WATCH_DISABLED    0x00000000
+#define SA11X0_DBCR_STORE_DATA_WATCH_ENABLED     0x00000004
+#define SA11X0_DBCR_STORE_DATA_WATCH_MASK        0x00000004
+
+#define SA11X0_IBCR_INSTRUCTION_ADDRESS_MASK     0xFFFFFFFC
+#define SA11X0_IBCR_BREAKPOINT_DISABLED          0x00000000
+#define SA11X0_IBCR_BREAKPOINT_ENABLED           0x00000001
+#define SA11X0_IBCR_BREAKPOINT_ENABLE_MASK       0x00000001
+
+/*
+ * SA-1100 Test, Clock and Idle Control Definition
+ */
+#ifdef __ASSEMBLER__
+#  define SA11X0_ICACHE_ODD_WORD_LOADING_OPCODE  0x1
+#  define SA11X0_ICACHE_ODD_WORD_LOADING_RM      c1
+#  define SA11X0_ICACHE_EVEN_WORD_LOADING_OPCODE 0x1
+#  define SA11X0_ICACHE_EVEN_WORD_LOADING_RM     c2
+#  define SA11X0_ICACHE_CLEAR_LFSR_OPCODE        0x1
+#  define SA11X0_ICACHE_CLEAR_LFSR_RM            c4
+#  define SA11X0_MOVE_LFSR_TO_R14_ABORT_OPCODE   0x1
+#  define SA11X0_MOVE_LFSR_TO_R14_ABORT_RM       c8
+#  define SA11X0_ENABLE_CLOCK_SWITCHING_OPCODE   0x2
+#  define SA11X0_ENABLE_CLOCK_SWITCHING_RM       c1
+#  define SA11X0_DISABLE_CLOCK_SWITCHING_OPCODE  0x2
+#  define SA11X0_DISABLE_CLOCK_SWITCHING_RM      c2
+#  define SA11X0_WAIT_FOR_INTERRUPT_OPCODE       0x2
+#  define SA11X0_WAIT_FOR_INTERRUPT_RM           c8
+#else /* __ASSEMBLER__ */
+#  define SA11X0_ICACHE_ODD_WORD_LOADING_OPCODE  "0x1"
+#  define SA11X0_ICACHE_ODD_WORD_LOADING_RM      "c1"
+#  define SA11X0_ICACHE_EVEN_WORD_LOADING_OPCODE "0x1"
+#  define SA11X0_ICACHE_EVEN_WORD_LOADING_RM     "c2"
+#  define SA11X0_ICACHE_CLEAR_LFSR_OPCODE        "0x1"
+#  define SA11X0_ICACHE_CLEAR_LFSR_RM            "c4"
+#  define SA11X0_MOVE_LFSR_TO_R14_ABORT_OPCODE   "0x1"
+#  define SA11X0_MOVE_LFSR_TO_R14_ABORT_RM       "c8"
+#  define SA11X0_ENABLE_CLOCK_SWITCHING_OPCODE   "0x2"
+#  define SA11X0_ENABLE_CLOCK_SWITCHING_RM       "c1"
+#  define SA11X0_DISABLE_CLOCK_SWITCHING_OPCODE  "0x2"
+#  define SA11X0_DISABLE_CLOCK_SWITCHING_RM      "c2"
+#  define SA11X0_WAIT_FOR_INTERRUPT_OPCODE       "0x2"
+#  define SA11X0_WAIT_FOR_INTERRUPT_RM           "c8"
+#endif /* __ASSEMBLER__ */
+
+
+/*
+ * SA11X0 IRQ Controller IRQ Numbers
+ */
+#define SA11X0_IRQ_MIN                           0
+                                                 
+#define SA11X0_IRQ_GPIO_0_EDGE_DETECT            0
+#define SA11X0_IRQ_GPIO_1_EDGE_DETECT            1
+#define SA11X0_IRQ_GPIO_2_EDGE_DETECT            2
+#define SA11X0_IRQ_GPIO_3_EDGE_DETECT            3
+#define SA11X0_IRQ_GPIO_4_EDGE_DETECT            4
+#define SA11X0_IRQ_GPIO_5_EDGE_DETECT            5
+#define SA11X0_IRQ_GPIO_6_EDGE_DETECT            6
+#define SA11X0_IRQ_GPIO_7_EDGE_DETECT            7
+#define SA11X0_IRQ_GPIO_8_EDGE_DETECT            8
+#define SA11X0_IRQ_GPIO_9_EDGE_DETECT            0
+#define SA11X0_IRQ_GPIO_10_EDGE_DETECT           10
+#define SA11X0_IRQ_GPIO_ANY_EDGE_DETECT          11
+#define SA11X0_IRQ_LCD_CONT_SERVICE_REQUEST      12
+#define SA11X0_IRQ_USB_SERVICE_REQUEST           13
+#define SA11X0_IRQ_SDLC_SERVICE_REQUEST          14
+#define SA11X0_IRQ_UART1_SERVICE_REQUEST         15
+#define SA11X0_IRQ_ICP_SERVICE_REQUEST           16
+#define SA11X0_IRQ_UART3_SERVICE_REQUEST         17
+#define SA11X0_IRQ_MCP_SERVICE_REQUEST           18
+#define SA11X0_IRQ_SSP_SERVICE_REQUEST           19
+#define SA11X0_IRQ_CHANNEL_0_SERVICE_REQUEST     20
+#define SA11X0_IRQ_CHANNEL_1_SERVICE_REQUEST     21
+#define SA11X0_IRQ_CHANNEL_2_SERVICE_REQUEST     22
+#define SA11X0_IRQ_CHANNEL_3_SERVICE_REQUEST     23
+#define SA11X0_IRQ_CHANNEL_4_SERVICE_REQUEST     24
+#define SA11X0_IRQ_CHANNEL_5_SERVICE_REQUEST     25
+#define SA11X0_IRQ_OS_TIMER_MATCH_REG_0          26
+#define SA11X0_IRQ_OS_TIMER_MATCH_REG_1          27
+#define SA11X0_IRQ_OS_TIMER_MATCH_REG_2          28
+#define SA11X0_IRQ_OS_TIMER_MATCH_REG_3          29
+#define SA11X0_IRQ_ONE_HZ_CLOCK_TIC              30
+#define SA11X0_IRQ_RTC_EQUALS_ALARM              31
+                                                 
+#define SA11X0_IRQ_MAX                           31
+#define NUM_SA11X0_INTERRUPTS                    SA11X0_IRQ_MAX - SA11X0_IRQ_MIN + 1
+#define SA11X0_IRQ_INTSRC_MASK(irq_nr)           (1 << (irq_nr))
+
+/*
+ * SA11X0 UART 1 Registers
+ */
+#define SA11X0_UART1_BASE                       SA11X0_REGISTER(0x10000)
+#define SA11X0_UART1_CONTROL0                   SA11X0_REGISTER(0x10000)
+#define SA11X0_UART1_CONTROL1                   SA11X0_REGISTER(0x10004)
+#define SA11X0_UART1_CONTROL2                   SA11X0_REGISTER(0x10008)
+#define SA11X0_UART1_CONTROL3                   SA11X0_REGISTER(0x1000C)
+#define SA11X0_UART1_DATA                       SA11X0_REGISTER(0x10014)
+#define SA11X0_UART1_STATUS0                    SA11X0_REGISTER(0x1001C)
+#define SA11X0_UART1_STATUS1                    SA11X0_REGISTER(0x10020)
+
+/*
+ * SA11X0 UART 3 Registers
+ */
+#define SA11X0_UART3_BASE                       SA11X0_REGISTER(0x50000)
+#define SA11X0_UART3_CONTROL0                   SA11X0_REGISTER(0x50000)
+#define SA11X0_UART3_CONTROL1                   SA11X0_REGISTER(0x50004)
+#define SA11X0_UART3_CONTROL2                   SA11X0_REGISTER(0x50008)
+#define SA11X0_UART3_CONTROL3                   SA11X0_REGISTER(0x5000C)
+#define SA11X0_UART3_DATA                       SA11X0_REGISTER(0x50014)
+#define SA11X0_UART3_STATUS0                    SA11X0_REGISTER(0x5001C)
+#define SA11X0_UART3_STATUS1                    SA11X0_REGISTER(0x50020)
+
+/*
+ * SA11X0 UART Control Register 0 Bit Fields.
+ */
+#define SA11X0_UART_PARITY_DISABLED              0x00
+#define SA11X0_UART_PARITY_ENABLED               0x01
+#define SA11X0_UART_PARITY_ENABLE_MASK           0x01
+#define SA11X0_UART_PARITY_ODD                   0x00
+#define SA11X0_UART_PARITY_EVEN                  0x02
+#define SA11X0_UART_PARITY_MODE_MASK             0x02
+#define SA11X0_UART_STOP_BITS_1                  0x00
+#define SA11X0_UART_STOP_BITS_2                  0x04
+#define SA11X0_UART_STOP_BITS_MASK               0x04
+#define SA11X0_UART_DATA_BITS_7                  0x00
+#define SA11X0_UART_DATA_BITS_8                  0x08
+#define SA11X0_UART_DATA_BITS_MASK               0x08
+#define SA11X0_UART_SAMPLE_CLOCK_DISABLED        0x00
+#define SA11X0_UART_SAMPLE_CLOCK_ENABLED         0x10
+#define SA11X0_UART_SAMPLE_CLOCK_ENABLE_MASK     0x10
+#define SA11X0_UART_RX_RISING_EDGE_SELECT        0x00
+#define SA11X0_UART_RX_FALLING_EDGE_SELECT       0x20
+#define SA11X0_UART_RX_EDGE_SELECT_MASK          0x20
+#define SA11X0_UART_TX_RISING_EDGE_SELECT        0x00
+#define SA11X0_UART_TX_FALLING_EDGE_SELECT       0x40
+#define SA11X0_UART_TX_EDGE_SELECT_MASK          0x20
+
+/*
+ * SA-1100 UART Baud Control Register bit masks
+ */
+#define SA11X0_UART_H_BAUD_RATE_DIVISOR_MASK     0x0000000F
+#define SA11X0_UART_L_BAUD_RATE_DIVISOR_MASK     0x000000FF
+#define SA11X0_UART_BAUD_RATE_DIVISOR(x)         ((3686400/(16*(x)))-1)
+
+/*
+ * SA-1100 UART Control Register 3 Bit Fields.
+ */
+#define SA11X0_UART_RX_DISABLED                  0x00
+#define SA11X0_UART_RX_ENABLED                   0x01
+#define SA11X0_UART_RX_ENABLE_MASK               0x01
+#define SA11X0_UART_TX_DISABLED                  0x00
+#define SA11X0_UART_TX_ENABLED                   0x02
+#define SA11X0_UART_TX_ENABLE_MASK               0x02
+#define SA11X0_UART_BREAK_DISABLED               0x00
+#define SA11X0_UART_BREAK_ENABLED                0x04
+#define SA11X0_UART_BREAK_MASK                   0x04
+#define SA11X0_UART_RX_FIFO_INT_DISABLED         0x00
+#define SA11X0_UART_RX_FIFO_INT_ENABLED          0x08
+#define SA11X0_UART_RX_FIFO_INT_ENABLE_MASK      0x08
+#define SA11X0_UART_TX_FIFO_INT_DISABLED         0x00
+#define SA11X0_UART_TX_FIFO_INT_ENABLED          0x10
+#define SA11X0_UART_TX_FIFO_INT_ENABLE_MASK      0x10
+#define SA11X0_UART_NORMAL_OPERATION             0x00
+#define SA11X0_UART_LOOPBACK_MODE                0x20
+
+/*
+ * SA-1100 UART Data Register bit masks
+ */
+#define SA11X0_UART_DATA_MASK                    0x000000FF
+
+/*
+ * SA-1100 UART Status Register 0 Bit Fields.
+ */
+#define SA11X0_UART_TX_SERVICE_REQUEST           0x01
+#define SA11X0_UART_RX_SERVICE_REQUEST           0x02
+#define SA11X0_UART_RX_IDLE                      0x04
+#define SA11X0_UART_RX_BEGIN_OF_BREAK            0x08
+#define SA11X0_UART_RX_END_OF_BREAK              0x10
+#define SA11X0_UART_ERROR_IN_FIFO                0x20
+
+/*
+ * SA-1100 UART Status Register 1 Bit Fields.
+ */
+#define SA11X0_UART_TX_BUSY                      0x01
+#define SA11X0_UART_RX_FIFO_NOT_EMPTY            0x02
+#define SA11X0_UART_TX_FIFO_NOT_FULL             0x04
+#define SA11X0_UART_PARITY_ERROR                 0x08
+#define SA11X0_UART_FRAMING_ERROR                0x10
+#define SA11X0_UART_RX_FIFO_OVERRUN              0x20
+
+#define UART_BASE_0                              SA11X0_UART_CONTROL_0
+#define UART_BASE_1                              SA11X0_UART_1_CONTROL_0
+
+/*
+ * SA11X0 IRQ Controller Register Definitions.
+ */
+#define SA11X0_ICIP                              SA11X0_REGISTER(0x10050000)
+#define SA11X0_ICMR                              SA11X0_REGISTER(0x10050004)
+#define SA11X0_ICLR                              SA11X0_REGISTER(0x10050008)
+#define SA11X0_ICCR                              SA11X0_REGISTER(0x1005000C)
+#define SA11X0_ICFP                              SA11X0_REGISTER(0x10050010)
+#define SA11X0_ICPR                              SA11X0_REGISTER(0x10050020)
+
+/*
+ * SA11X0 IRQ Controller Control Register Bit Fields.
+ */
+#define SA11X0_ICCR_DISABLE_IDLE_MASK_ALL        0x0
+#define SA11X0_ICCR_DISABLE_IDLE_MASK_ENABLED    0x1
+
+/*
+ * SA11X0 Timer/counter registers
+ */
+#define SA11X0_OSMR0                             SA11X0_REGISTER(0x10000000)
+#define SA11X0_OSMR1                             SA11X0_REGISTER(0x10000004)
+#define SA11X0_OSMR2                             SA11X0_REGISTER(0x10000008)
+#define SA11X0_OSMR3                             SA11X0_REGISTER(0x1000000C)
+#define SA11X0_OSCR                              SA11X0_REGISTER(0x10000010)
+#define SA11X0_OSSR                              SA11X0_REGISTER(0x10000014)
+#define SA11X0_OIER                              SA11X0_REGISTER(0x1000001C)
+#define SA11X0_RCNR                              SA11X0_REGISTER(0x10010004)
+#define SA11X0_RTTR                              SA11X0_REGISTER(0x10010008)
+#define SA11X0_RTSR                              SA11X0_REGISTER(0x10010010)
+
+// Timer status register
+#define SA11X0_OSSR_TIMER0  (1<<0)   // Timer match register #0
+#define SA11X0_OSSR_TIMER1  (1<<1)
+#define SA11X0_OSSR_TIMER2  (1<<2)
+#define SA11X0_OSSR_TIMER3  (1<<3)
+
+// Timer interrupt enable register
+#define SA11X0_OIER_TIMER0  (1<<0)
+#define SA11X0_OIER_TIMER1  (1<<1)
+#define SA11X0_OIER_TIMER2  (1<<2)
+#define SA11X0_OIER_TIMER3  (1<<3)
+
+/*
+ * SA-1100 Reset Controller Register Definition
+ */
+#define SA11X0_RESET_SOFTWARE_RESET              SA11X0_REGISTER(0x10030000)
+#define SA11X0_RESET_STATUS                      SA11X0_REGISTER(0x10030004)
+#define SA11X0_TUCR                              SA11X0_REGISTER(0x10030008)
+
+/*
+ * SA-1100 Reset Controller Bit Field Definitions
+ */
+#define SA11X0_INVOKE_SOFTWARE_RESET             0x1
+
+#define SA11X0_HARDWARE_RESET                    0x1
+#define SA11X0_SOFTWARE_RESET                    0x2
+#define SA11X0_WATCHDOG_RESET                    0x4
+#define SA11X0_SLEEP_MODE_RESET                  0x8
+
+/*
+ * SA-1100 Power Manager Registers
+ */
+#define SA11X0_PWR_MGR_CONTROL                   SA11X0_REGISTER(0x10020000)
+#define SA11X0_PWR_MGR_SLEEP_STATUS              SA11X0_REGISTER(0x10020004)
+#define SA11X0_PWR_MGR_SCRATCHPAD                SA11X0_REGISTER(0x10020008)
+#define SA11X0_PWR_MGR_WAKEUP_ENABLE             SA11X0_REGISTER(0x1002000C)
+#define SA11X0_PWR_MGR_GENERAL_CONFIG            SA11X0_REGISTER(0x10020010)
+#define SA11X0_PWR_MGR_PLL_CONFIG                SA11X0_REGISTER(0x10020014)
+#define SA11X0_PWR_MGR_GPIO_SLEEP_STATE          SA11X0_REGISTER(0x10020018)
+#define SA11X0_PWR_MGR_OSC_STATUS                SA11X0_REGISTER(0x1002001C)
+
+/*
+ * SA-1100 Control Register Bit Field Definitions
+ */
+#define SA11X0_NO_FORCE_SLEEP_MODE               0x00000000
+#define SA11X0_FORCE_SLEEP_MODE                  0x00000001
+#define SA11X0_SLEEP_MODE_MASK                   0x00000001
+
+/*
+ * SA-1100 Power Management Configuration Register Bit Field Definitions
+ */
+#define SA11X0_NO_STOP_OSC_DURING_SLEEP          0x00000000
+#define SA11X0_STOP_OSC_DURING_SLEEP             0x00000001
+#define SA11X0_OSC_DURING_SLEEP_MASK             0x00000001
+#define SA11X0_DRIVE_PCMCIA_DURING_SLEEP         0x00000000
+#define SA11X0_FLOAT_PCMCIA_DURING_SLEEP         0x00000002
+#define SA11X0_PCMCIA_DURING_SLEEP_MASK          0x00000002
+#define SA11X0_DRIVE_CHIPSEL_DURING_SLEEP        0x00000000
+#define SA11X0_FLOAT_CHIPSEL_DURING_SLEEP        0x00000004
+#define SA11X0_CHIPSEL_DURING_SLEEP_MASK         0x00000004
+#define SA11X0_WAIT_OSC_STABLE                   0x00000000
+#define SA11X0_FORCE_OSC_ENABLE_ON               0x00000008
+#define SA11X0_OSC_STABLE_MASK                   0x00000008
+
+/*
+ * SA-1100 PLL Configuration Register Bit Field Definitions
+ */
+#define SA11X0_CLOCK_SPEED_59_0_MHz              0x00000000
+#define SA11X0_CLOCK_SPEED_73_7_MHz              0x00000001
+#define SA11X0_CLOCK_SPEED_88_5_MHz              0x00000002
+#define SA11X0_CLOCK_SPEED_103_2_MHz             0x00000003
+#define SA11X0_CLOCK_SPEED_118_0_MHz             0x00000004
+#define SA11X0_CLOCK_SPEED_132_7_MHz             0x00000005
+#define SA11X0_CLOCK_SPEED_147_5_MHz             0x00000006
+#define SA11X0_CLOCK_SPEED_162_2_MHz             0x00000007
+#define SA11X0_CLOCK_SPEED_176_9_MHz             0x00000008
+#define SA11X0_CLOCK_SPEED_191_7_MHz             0x00000009
+#define SA11X0_CLOCK_SPEED_206_4_MHz             0x0000000A
+#define SA11X0_CLOCK_SPEED_221_2_MHz             0x0000000B
+
+/*
+ * SA-1100 Power Manager Wakeup Register Bit Field Definitions
+ */
+#define SA11X0_WAKEUP_ENABLE(x)                  ((x) & 0x8FFFFFFF)
+
+/*
+ * SA-1100 Power Manager Sleep Status Bit Field Definitions
+ */
+#define SA11X0_SOFTWARE_SLEEP_STATUS             0x00000001
+#define SA11X0_BATTERY_FAULT_STATUS              0x00000002
+#define SA11X0_VDD_FAULT_STATUS                  0x00000004
+#define SA11X0_DRAM_CONTROL_HOLD                 0x00000008
+#define SA11X0_PERIPHERAL_CONTROL_HOLD           0x00000010
+
+/*
+ * SA-1100 Power Manager Oscillator Status Register Bit Field Definitions
+ */
+#define SA11X0_OSCILLATOR_STATUS                 0x00000001
+
+/*
+ * SA-1110 GPCLK Register Definitions
+ */
+#define SA1110_GPCLK_CONTROL_0                   SA11X0_REGISTER(0x00020060)
+#define SA1110_GPCLK_CONTROL_1                   SA11X0_REGISTER(0x0002006C)
+#define SA1110_GPCLK_CONTROL_2                   SA11X0_REGISTER(0x00020070)
+
+/* GPCLK Control Register 0 */
+#define SA1110_GPCLK_SUS_GPCLK   0
+#define SA1110_GPCLK_SUS_UART    1
+#define SA1110_GPCLK_SCE         2
+#define SA1110_GPCLK_SCD_IN      0
+#define SA1110_GPCLK_SCD_OUT     4
+
+/*
+ * SA11X0 Peripheral Port Controller Register Definitions
+ */
+#define SA11X0_PPC_PIN_DIRECTION                 SA11X0_REGISTER(0x10060000)
+#define SA11X0_PPC_PIN_STATE                     SA11X0_REGISTER(0x10060004)
+#define SA11X0_PPC_PIN_ASSIGNMENT                SA11X0_REGISTER(0x10060008)
+#define SA11X0_PPC_PIN_SLEEP_MODE_DIR            SA11X0_REGISTER(0x1006000C)
+#define SA11X0_PPC_PIN_FLAG                      SA11X0_REGISTER(0x10060010)
+
+/*
+ * SA11X0 PPC Bit Field Definitions
+ */
+#define SA11X0_PPC_LCD_PIN_0_DIR_INPUT           0x00000000
+#define SA11X0_PPC_LCD_PIN_0_DIR_OUTPUT          0x00000001
+#define SA11X0_PPC_LCD_PIN_0_DIR_MASK            0x00000001
+#define SA11X0_PPC_LCD_PIN_1_DIR_INPUT           0x00000000
+#define SA11X0_PPC_LCD_PIN_1_DIR_OUTPUT          0x00000002
+#define SA11X0_PPC_LCD_PIN_1_DIR_MASK            0x00000002
+#define SA11X0_PPC_LCD_PIN_2_DIR_INPUT           0x00000000
+#define SA11X0_PPC_LCD_PIN_2_DIR_OUTPUT          0x00000004
+#define SA11X0_PPC_LCD_PIN_2_DIR_MASK            0x00000004
+#define SA11X0_PPC_LCD_PIN_3_DIR_INPUT           0x00000000
+#define SA11X0_PPC_LCD_PIN_3_DIR_OUTPUT          0x00000008
+#define SA11X0_PPC_LCD_PIN_3_DIR_MASK            0x00000008
+#define SA11X0_PPC_LCD_PIN_4_DIR_INPUT           0x00000000
+#define SA11X0_PPC_LCD_PIN_4_DIR_OUTPUT          0x00000010
+#define SA11X0_PPC_LCD_PIN_4_DIR_MASK            0x00000010
+#define SA11X0_PPC_LCD_PIN_5_DIR_INPUT           0x00000000
+#define SA11X0_PPC_LCD_PIN_5_DIR_OUTPUT          0x00000020
+#define SA11X0_PPC_LCD_PIN_5_DIR_MASK            0x00000020
+#define SA11X0_PPC_LCD_PIN_6_DIR_INPUT           0x00000000
+#define SA11X0_PPC_LCD_PIN_6_DIR_OUTPUT          0x00000040
+#define SA11X0_PPC_LCD_PIN_6_DIR_MASK            0x00000040
+#define SA11X0_PPC_LCD_PIN_7_DIR_INPUT           0x00000000
+#define SA11X0_PPC_LCD_PIN_7_DIR_OUTPUT          0x00000080
+#define SA11X0_PPC_LCD_PIN_7_DIR_MASK            0x00000080
+#define SA11X0_PPC_LCD_PIXCLK_DIR_INPUT          0x00000000
+#define SA11X0_PPC_LCD_PIXCLK_DIR_OUTPUT         0x00000100
+#define SA11X0_PPC_LCD_PIXCLK_DIR_MASK           0x00000100
+#define SA11X0_PPC_LCD_LINECLK_DIR_INPUT         0x00000000
+#define SA11X0_PPC_LCD_LINECLK_DIR_OUTPUT        0x00000200
+#define SA11X0_PPC_LCD_LINECLK_DIR_MASK          0x00000200
+#define SA11X0_PPC_LCD_FRAMECLK_DIR_INPUT        0x00000000
+#define SA11X0_PPC_LCD_FRAMECLK_DIR_OUTPUT       0x00000400
+#define SA11X0_PPC_LCD_FRAMECLK_DIR_MASK         0x00000400
+#define SA11X0_PPC_LCD_AC_BIAS_DIR_INPUT         0x00000000
+#define SA11X0_PPC_LCD_AC_BIAS_DIR_OUTPUT        0x00000800
+#define SA11X0_PPC_LCD_AC_BIAS_DIR_MASK          0x00000800
+#define SA11X0_PPC_SERIAL_PORT_1_TX_DIR_INPUT    0x00000000
+#define SA11X0_PPC_SERIAL_PORT_1_TX_DIR_OUTPUT   0x00001000
+#define SA11X0_PPC_SERIAL_PORT_1_TX_DIR_MASK     0x00001000
+#define SA11X0_PPC_SERIAL_PORT_1_RX_DIR_INPUT    0x00000000
+#define SA11X0_PPC_SERIAL_PORT_1_RX_DIR_OUTPUT   0x00002000
+#define SA11X0_PPC_SERIAL_PORT_1_RX_DIR_MASK     0x00002000
+#define SA11X0_PPC_SERIAL_PORT_2_TX_DIR_INPUT    0x00000000
+#define SA11X0_PPC_SERIAL_PORT_2_TX_DIR_OUTPUT   0x00004000
+#define SA11X0_PPC_SERIAL_PORT_2_TX_DIR_MASK     0x00004000
+#define SA11X0_PPC_SERIAL_PORT_2_RX_DIR_INPUT    0x00000000
+#define SA11X0_PPC_SERIAL_PORT_2_RX_DIR_OUTPUT   0x00008000
+#define SA11X0_PPC_SERIAL_PORT_2_RX_DIR_MASK     0x00008000
+#define SA11X0_PPC_SERIAL_PORT_3_TX_DIR_INPUT    0x00000000
+#define SA11X0_PPC_SERIAL_PORT_3_TX_DIR_OUTPUT   0x00010000
+#define SA11X0_PPC_SERIAL_PORT_3_TX_DIR_MASK     0x00010000
+#define SA11X0_PPC_SERIAL_PORT_3_RX_DIR_INPUT    0x00000000
+#define SA11X0_PPC_SERIAL_PORT_3_RX_DIR_OUTPUT   0x00020000
+#define SA11X0_PPC_SERIAL_PORT_3_RX_DIR_MASK     0x00020000
+#define SA11X0_PPC_SERIAL_PORT_4_TX_DIR_INPUT    0x00000000
+#define SA11X0_PPC_SERIAL_PORT_4_TX_DIR_OUTPUT   0x00040000
+#define SA11X0_PPC_SERIAL_PORT_4_TX_DIR_MASK     0x00040000
+#define SA11X0_PPC_SERIAL_PORT_4_RX_DIR_INPUT    0x00000000
+#define SA11X0_PPC_SERIAL_PORT_4_RX_DIR_OUTPUT   0x00080000
+#define SA11X0_PPC_SERIAL_PORT_4_RX_DIR_MASK     0x00080000
+#define SA11X0_PPC_SERIAL_PORT_4_SERCLK_INPUT    0x00000000
+#define SA11X0_PPC_SERIAL_PORT_4_SERCLK_OUTPUT   0x00100000
+#define SA11X0_PPC_SERIAL_PORT_4_SERCLK_MASK     0x00100000
+#define SA11X0_PPC_SERIAL_PORT_4_SERFRM_INPUT    0x00000000
+#define SA11X0_PPC_SERIAL_PORT_4_SERFRM_OUTPUT   0x00200000
+#define SA11X0_PPC_SERIAL_PORT_4_SERFRM_MASK     0x00200000
+
+#define SA11X0_PPC_UART_PIN_NOT_REASSIGNED       0x00000000
+#define SA11X0_PPC_UART_PIN_REASSIGNED           0x00001000
+#define SA11X0_PPC_UART_PIN_REASSIGNMENT_MASK    0x00001000
+#define SA11X0_PPC_SSP_PIN_NOT_REASSIGNED        0x00000000
+#define SA11X0_PPC_SSP_PIN_REASSIGNED            0x00040000
+#define SA11X0_PPC_SSP_PIN_REASSIGNMENT_MASK     0x00040000
+
+/*
+ * SA-1100 MCP Registers
+ */
+#define SA11X0_MCP_CONTROL_0                     SA11X0_REGISTER(0x00060000)
+#define SA11X0_MCP_DATA_0                        SA11X0_REGISTER(0x00060008)
+#define SA11X0_MCP_DATA_1                        SA11X0_REGISTER(0x0006000C)
+#define SA11X0_MCP_DATA_2                        SA11X0_REGISTER(0x00060010)
+#define SA11X0_MCP_STATUS                        SA11X0_REGISTER(0x00060018)
+#define SA11X0_MCP_CONTROL_1                     SA11X0_REGISTER(0x00060030)
+
+/*
+ * SA-1100 Memory Configuration Registers
+ */
+#define SA11X0_DRAM_CONFIGURATION                SA11X0_REGISTER(0x20000000)
+#define SA11X0_DRAM0_CAS_0                       SA11X0_REGISTER(0x20000004)
+#define SA11X0_DRAM0_CAS_1                       SA11X0_REGISTER(0x20000008)
+#define SA11X0_DRAM0_CAS_2                       SA11X0_REGISTER(0x2000000C)
+#define SA11X0_STATIC_CONTROL_0                  SA11X0_REGISTER(0x20000010)
+#define SA11X0_STATIC_CONTROL_1                  SA11X0_REGISTER(0x20000014)
+#define SA11X0_EXP_BUS_CONFIGURATION             SA11X0_REGISTER(0x20000018)
+#define SA11X0_REFRESH_CONFIGURATION             SA11X0_REGISTER(0x2000001C)
+#define SA11X0_DRAM2_CAS_0                       SA11X0_REGISTER(0x20000020)
+#define SA11X0_DRAM2_CAS_1                       SA11X0_REGISTER(0x20000024)
+#define SA11X0_DRAM2_CAS_2                       SA11X0_REGISTER(0x20000028)
+#define SA11X0_STATIC_CONTROL_2                  SA11X0_REGISTER(0x2000002C)
+#define SA11X0_SMROM_CONFIGURATION               SA11X0_REGISTER(0x20000030)
+
+/*
+ * SA-1100 DRAM Configuration Bit Field Definitions
+ */
+#define SA11X0_DRAM_BANK_0_DISABLED              0x00000000
+#define SA11X0_DRAM_BANK_0_ENABLED               0x00000001
+#define SA11X0_DRAM_BANK_0_ENABLE_MASK           0x00000001
+#define SA11X0_DRAM_BANK_1_DISABLED              0x00000000
+#define SA11X0_DRAM_BANK_1_ENABLED               0x00000002
+#define SA11X0_DRAM_BANK_1_ENABLE_MASK           0x00000002
+#define SA11X0_DRAM_BANK_2_DISABLED              0x00000000
+#define SA11X0_DRAM_BANK_2_ENABLED               0x00000004
+#define SA11X0_DRAM_BANK_2_ENABLE_MASK           0x00000004
+#define SA11X0_DRAM_BANK_3_DISABLED              0x00000000
+#define SA11X0_DRAM_BANK_3_ENABLED               0x00000008
+#define SA11X0_DRAM_BANK_3_ENABLE_MASK           0x00000008
+#define SA11X0_DRAM_ROW_ADDRESS_BITS_9           0x00000000
+#define SA11X0_DRAM_ROW_ADDRESS_BITS_10          0x00000010
+#define SA11X0_DRAM_ROW_ADDRESS_BITS_11          0x00000020
+#define SA11X0_DRAM_ROW_ADDRESS_BITS_12          0x00000030
+#define SA11X0_DRAM_ROW_ADDRESS_BITS_MASK        0x00000030
+#define SA11X0_DRAM_CLOCK_CPU_CLOCK              0x00000000
+#define SA11X0_DRAM_CLOCK_CPU_CLOCK_DIV_2        0x00000040
+#define SA11X0_DRAM_CLOCK_CPU_CLOCK_MASK         0x00000040
+#define SA11X0_DRAM_RAS_PRECHARGE(x)             (((x) & 0xF) << 7)
+#define SA11X0_DRAM_CAS_BEFORE_RAS(x)            (((x) & 0xF) << 11)
+#define SA11X0_DATA_INPUT_LATCH_WITH_CAS         0x00000000
+#define SA11X0_DATA_INPUT_LATCH_CAS_PLUS_ONE     0x00008000
+#define SA11X0_DATA_INPUT_LATCH_CAS_PLUS_TWO     0x00010000
+#define SA11X0_DATA_INPUT_LATCH_CAS_PLUS_THREE   0x00018000
+#define SA11X0_DRAM_REFRESH_INTERVAL(x)          (((x) & 0x7FFF) << 17)
+
+/*
+ * SA-1100 Static Memory Control Register Bit Field Definitions
+ */
+#define SA11X0_STATIC_ROM_TYPE_FLASH             0x00000000
+#define SA11X0_STATIC_ROM_TYPE_SRAM              0x00000001
+#define SA11X0_STATIC_ROM_TYPE_BURST_OF_4_ROM    0x00000002
+#define SA11X0_STATIC_ROM_TYPE_BURST_OF_8_ROM    0x00000003
+#define SA11X0_STATIC_ROM_TYPE_MASK              0x00000003
+#define SA11X0_STATIC_ROM_BUS_WIDTH_32_BITS      0x00000000
+#define SA11X0_STATIC_ROM_BUS_WIDTH_16_BITS      0x00000004
+#define SA11X0_STATIC_ROM_BUS_WIDTH_MASK         0x00000004
+#define SA11X0_STATIC_ROM_DELAY_FIRST_ACCESS(x)  (((x) & 0x1F) << 3)
+#define SA11X0_STATIC_ROM_DELAY_NEXT_ACCESS(x)   (((x) & 0x1F) << 8)
+#define SA11X0_STATIC_ROM_RECOVERY(x)            (((x) & 0x7) << 13)
+
+#define SA11X0_STATIC_ROM_BANK_0(x)              (((x) & 0xFFFF) <<  0)
+#define SA11X0_STATIC_ROM_BANK_1(x)              (((x) & 0xFFFF) << 16)
+#define SA11X0_STATIC_ROM_BANK_2(x)              (((x) & 0xFFFF) <<  0)
+#define SA11X0_STATIC_ROM_BANK_3(x)              (((x) & 0xFFFF) << 16)
+
+/*
+ * SA-1100 GPIO Register Definitions
+ */
+#define SA11X0_GPIO_PIN_0                        BIT0
+#define SA11X0_GPIO_PIN_1                        BIT1
+#define SA11X0_GPIO_PIN_2                        BIT2
+#define SA11X0_GPIO_PIN_3                        BIT3
+#define SA11X0_GPIO_PIN_4                        BIT4
+#define SA11X0_GPIO_PIN_5                        BIT5
+#define SA11X0_GPIO_PIN_6                        BIT6
+#define SA11X0_GPIO_PIN_7                        BIT7
+#define SA11X0_GPIO_PIN_8                        BIT8
+#define SA11X0_GPIO_PIN_9                        BIT9
+#define SA11X0_GPIO_PIN_10                       BIT10
+#define SA11X0_GPIO_PIN_11                       BIT11
+#define SA11X0_GPIO_PIN_12                       BIT12
+#define SA11X0_GPIO_PIN_13                       BIT13
+#define SA11X0_GPIO_PIN_14                       BIT14
+#define SA11X0_GPIO_PIN_15                       BIT15
+#define SA11X0_GPIO_PIN_16                       BIT16
+#define SA11X0_GPIO_PIN_17                       BIT17
+#define SA11X0_GPIO_PIN_18                       BIT18
+#define SA11X0_GPIO_PIN_19                       BIT19
+#define SA11X0_GPIO_PIN_20                       BIT20
+#define SA11X0_GPIO_PIN_21                       BIT21
+#define SA11X0_GPIO_PIN_22                       BIT22
+#define SA11X0_GPIO_PIN_23                       BIT23
+#define SA11X0_GPIO_PIN_24                       BIT24
+#define SA11X0_GPIO_PIN_25                       BIT25
+#define SA11X0_GPIO_PIN_26                       BIT26
+#define SA11X0_GPIO_PIN_27                       BIT27
+
+#define SA11X0_GPIO_PIN_LEVEL                    SA11X0_REGISTER(0x10040000)
+#define SA11X0_GPIO_PIN_DIRECTION                SA11X0_REGISTER(0x10040004)
+#define SA11X0_GPIO_PIN_OUTPUT_SET               SA11X0_REGISTER(0x10040008)
+#define SA11X0_GPIO_PIN_OUTPUT_CLEAR             SA11X0_REGISTER(0x1004000C)
+#define SA11X0_GPIO_RISING_EDGE_DETECT           SA11X0_REGISTER(0x10040010)
+#define SA11X0_GPIO_FALLING_EDGE_DETECT          SA11X0_REGISTER(0x10040014)
+#define SA11X0_GPIO_EDGE_DETECT_STATUS           SA11X0_REGISTER(0x10040018)
+#define SA11X0_GPIO_ALTERNATE_FUNCTION           SA11X0_REGISTER(0x1004001C)
+
+#endif /* __HAL_SA11X0_H__ */
diff --git a/packages/hal/arm/sa11x0/var/current/include/plf_stub.h b/packages/hal/arm/sa11x0/var/current/include/plf_stub.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/var/current/include/plf_stub.h
@@ -0,0 +1,95 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+//      plf_stub.h
+//
+//      Platform header for GDB stub support.
+//
+//=============================================================================
+//####COPYRIGHTBEGIN####
+//
+// -------------------------------------------
+// The contents of this file are subject to the Red Hat eCos Public License
+// Version 1.1 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://www.redhat.com/
+//
+// Software distributed under the License is distributed on an "AS IS"
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the
+// License for the specific language governing rights and limitations under
+// the License. 
+//
+// The Original Code is eCos - Embedded Configurable Operating System,
+// released September 30, 1998.
+//
+// The Initial Developer of the Original Code is Red Hat.
+// Portions created by Red Hat are
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
+// All Rights Reserved.
+// -------------------------------------------
+//
+//####COPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   gthomas
+// Contributors:jskov
+//              Travis C. Furrer <furrer@mit.edu>
+// Date:        2000-05-08
+// Purpose:     Platform HAL stub support for Intel SA11x0 boards.
+// Usage:       #include <cyg/hal/plf_stub.h>
+//              
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h>         // CYG_UNUSED_PARAM
+
+#include <cyg/hal/hal_sa11x0.h>         // registers
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_intr.h>           // Interrupt macros
+#include <cyg/hal/arm_stub.h>           // architecture stub support
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL()       cyg_hal_plf_comms_init()
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE       0
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+#define HAL_STUB_PLATFORM_INIT()        CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//----------------------------------------------------------------------------
+// Reset.
+#define HAL_STUB_PLATFORM_RESET()                                          \
+    CYG_MACRO_START                                                        \
+    cyg_uint32 ctrl;                                                       \
+                                                                           \
+    /* By disabling interupts we will just hang in the loop below      */  \
+    /* if for some reason the software reset fails.                    */  \
+    HAL_DISABLE_INTERRUPTS(ctrl);                                          \
+                                                                           \
+    /* Software reset. */                                                  \
+    *SA11X0_RESET_SOFTWARE_RESET = SA11X0_INVOKE_SOFTWARE_RESET;           \
+                                                                           \
+    for(;;); /* hang here forever if reset fails */                        \
+    CYG_MACRO_END
+
+// Fallback (never really used)
+#define HAL_STUB_PLATFORM_RESET_ENTRY 0x00000000
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
diff --git a/packages/hal/arm/sa11x0/var/current/src/hal_diag.c b/packages/hal/arm/sa11x0/var/current/src/hal_diag.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/var/current/src/hal_diag.c
@@ -0,0 +1,542 @@
+/*=============================================================================
+//
+//      hal_diag.c
+//
+//      HAL diagnostic output code
+//
+//=============================================================================
+//####COPYRIGHTBEGIN####
+//
+// -------------------------------------------
+// The contents of this file are subject to the Red Hat eCos Public License
+// Version 1.1 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://www.redhat.com/
+//
+// Software distributed under the License is distributed on an "AS IS"
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the
+// License for the specific language governing rights and limitations under
+// the License. 
+//
+// The Original Code is eCos - Embedded Configurable Operating System,
+// released September 30, 1998.
+//
+// The Initial Developer of the Original Code is Red Hat.
+// Portions created by Red Hat are
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
+// All Rights Reserved.
+// -------------------------------------------
+//
+//####COPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   gthomas
+// Contributors:nickg, gthomas
+//              Travis C. Furrer <furrer@mit.edu>
+// Date:        2000-05-08
+// Purpose:     HAL diagnostic output
+// Description: Implementations of HAL diagnostic output support.
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // basic machine info
+#include <cyg/hal/hal_intr.h>           // interrupt macros
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_if.h>             // Calling interface definitions
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/drv_api.h>            // cyg_drv_interrupt_acknowledge
+#include <cyg/hal/hal_misc.h>           // Helper functions
+#include <cyg/hal/hal_sa11x0.h>         // Hardware definitions
+
+struct sa11x0_serial {
+  volatile cyg_uint32 utcr0;
+  volatile cyg_uint32 utcr1;
+  volatile cyg_uint32 utcr2;
+  volatile cyg_uint32 utcr3;
+  volatile cyg_uint32 pad0010;
+  volatile cyg_uint32 utdr;
+  volatile cyg_uint32 pad0018;
+  volatile cyg_uint32 utsr0;
+  volatile cyg_uint32 utsr1;
+};
+
+/*---------------------------------------------------------------------------*/
+// SA11x0 Serial Port (UARTx) for Debug
+
+static void
+init_channel(void* __ch_data)
+{
+    volatile struct sa11x0_serial* base = (struct sa11x0_serial*)__ch_data;
+    cyg_uint32 brd;
+
+    // Disable Receiver and Transmitter (clears FIFOs)
+    base->utcr3 = SA11X0_UART_RX_DISABLED | SA11X0_UART_TX_DISABLED;
+
+    // Clear sticky (writable) status bits.
+    base->utsr0 = SA11X0_UART_RX_IDLE | SA11X0_UART_RX_BEGIN_OF_BREAK |
+                  SA11X0_UART_RX_END_OF_BREAK;
+
+#if 0 // later
+    if (SA11X0_UART1_BASE == __ch_data) {
+
+        //Set pin 14 as an output (Tx) and pin 15 as in input (Rx).
+        base->gpdr = (*SA11X0_REG_GPDR | SA11X0_GPIO_14) & ~SA11X0_GPIO_15;
+
+        // Use GPIO 14 & 15 pins for serial port 1.
+        base->gafr |= SA11X0_GPIO_14 | SA11X0_GPIO_15;
+
+        // Pin reassignment for serial port 1.
+        base->ppar |= SA11X0_UART_PIN_REASSIGNMENT_MASK;
+    }
+#endif
+
+    // Set UART to 8N1 (8 data bits, no partity, 1 stop bit)
+    base->utcr0 = SA11X0_UART_PARITY_DISABLED | SA11X0_UART_STOP_BITS_1 |
+                  SA11X0_UART_DATA_BITS_8;
+
+    // Set the desired baud rate.
+    brd = SA11X0_UART_BAUD_RATE_DIVISOR(CYGHWR_HAL_ARM_SA11X0_DIAG_BAUD);
+    base->utcr1 = (brd >> 8) & SA11X0_UART_H_BAUD_RATE_DIVISOR_MASK;
+    base->utcr2 = brd & SA11X0_UART_L_BAUD_RATE_DIVISOR_MASK;
+
+    // Enable the receiver and the transmitter.
+    base->utcr3 = SA11X0_UART_RX_ENABLED | SA11X0_UART_TX_ENABLED;
+
+    // All done
+}
+
+void
+cyg_hal_plf_serial_putc(void *__ch_data, char c)
+{
+    volatile struct sa11x0_serial* base = (struct sa11x0_serial*)__ch_data;
+    CYGARC_HAL_SAVE_GP();
+
+    // Wait for Tx FIFO not full
+    while ((base->utsr1 & SA11X0_UART_TX_FIFO_NOT_FULL) == 0)
+        ;
+    base->utdr = c;
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+// FIXME: shouldn't we check for PARITY_ERROR, FRAMING_ERROR, or
+// RECEIVE_FIFO_OVERRUN_ERROR in the received data?  This
+// means check the appropriate bits in UTSR1.
+
+static cyg_bool
+cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+    volatile struct sa11x0_serial* base = (struct sa11x0_serial*)__ch_data;
+
+    // If receive fifo is empty, return false
+    if ((base->utsr1 & SA11X0_UART_RX_FIFO_NOT_EMPTY) == 0)
+        return false;
+
+    *ch = (char)base->utdr;
+
+    // Clear receiver idle status bit, to allow another interrupt to
+    // occur in the case where the receive fifo is almost empty.
+    base->utsr0 = SA11X0_UART_RX_IDLE;
+
+    return true;
+}
+
+cyg_uint8
+cyg_hal_plf_serial_getc(void* __ch_data)
+{
+    cyg_uint8 ch;
+    CYGARC_HAL_SAVE_GP();
+
+    while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+    CYGARC_HAL_RESTORE_GP();
+    return ch;
+}
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) \
+    || defined(CYGPRI_HAL_IMPLEMENTS_IF_SERVICES)
+
+static void
+cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, 
+                         cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void
+cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_int32 msec_timeout[2] = { 1000, 1000 };
+
+cyg_bool
+cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+    int delay_count;
+    int index;
+    cyg_bool res;
+    CYGARC_HAL_SAVE_GP();
+
+    if (SA11X0_UART1_BASE == __ch_data)
+        index = 0;
+    else
+        index = 1;
+
+    delay_count = msec_timeout[index] * 10; // delay in .1 ms steps
+
+    for(;;) {
+        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
+        if (res || 0 == delay_count--)
+            break;
+        
+        CYGACC_CALL_IF_DELAY_US(100);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static int isr_vectors[2] = {CYGNUM_HAL_INTERRUPT_UART1,
+                             CYGNUM_HAL_INTERRUPT_UART3};
+
+static int
+cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+    static int irq_state = 0;
+    volatile struct sa11x0_serial* base = (struct sa11x0_serial*)__ch_data;
+    int ret = 0;
+    int index;
+    CYGARC_HAL_SAVE_GP();
+
+    if (SA11X0_UART1_BASE == __ch_data)
+        index = 0;
+    else
+        index = 1;
+
+    switch (__func) {
+    case __COMMCTL_IRQ_ENABLE:
+        irq_state = 1;
+
+        base->utcr3 |= SA11X0_UART_RX_FIFO_INT_ENABLED;
+
+        HAL_INTERRUPT_UNMASK(isr_vectors[index]);
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = irq_state;
+        irq_state = 0;
+
+        base->utcr3 &= ~SA11X0_UART_RX_FIFO_INT_ENABLED;
+
+        HAL_INTERRUPT_MASK(isr_vectors[index]);
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = isr_vectors[index];
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+    {
+        va_list ap;
+
+        va_start(ap, __func);
+
+        ret = msec_timeout[index];
+        msec_timeout[index] = va_arg(ap, cyg_uint32);
+
+        va_end(ap);
+    }        
+    default:
+        break;
+    }
+    CYGARC_HAL_RESTORE_GP();
+    return ret;
+}
+
+static int
+cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, 
+                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+    int index, res = 0;
+    volatile struct sa11x0_serial* base = (struct sa11x0_serial*)__ch_data;
+    char c;
+    int reg;
+    CYGARC_HAL_SAVE_GP();
+
+    if (SA11X0_UART1_BASE == __ch_data)
+        index = 0;
+    else
+        index = 1;
+
+    reg = base->utsr1;
+
+    // read it anyway just in case - no harm done and we might prevent an
+    // interrupt loop
+    c = (char)base->utdr;
+
+    //Clear receiver idle status bit, to allow another interrupt to
+    //occur in the case where the receive fifo is almost empty.
+    base->utsr0 = SA11X0_UART_RX_IDLE;
+
+    cyg_drv_interrupt_acknowledge(isr_vectors[index]);
+
+    *__ctrlc = 0;
+    if ( (reg & SA11X0_UART_RX_FIFO_NOT_EMPTY) != 0 ) {
+        if( cyg_hal_is_break( &c , 1 ) )
+            *__ctrlc = 1;
+
+        res = CYG_ISR_HANDLED;
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static void
+cyg_hal_plf_serial_init(void)
+{
+    hal_virtual_comm_table_t* comm;
+    int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+    // Init channels
+    init_channel((void*)SA11X0_UART1_BASE);
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS == 2)
+    init_channel((void*)SA11X0_UART3_BASE);
+#endif
+
+    // Setup procs in the vector table
+
+    // Set channel 0
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
+    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+    CYGACC_COMM_IF_CH_DATA_SET(*comm, SA11X0_UART1_BASE);
+    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS == 2)
+    // Set channel 1
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
+    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+    CYGACC_COMM_IF_CH_DATA_SET(*comm, SA11X0_UART3_BASE);
+    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+#endif
+     
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+void
+cyg_hal_plf_comms_init(void)
+{
+    static int initialized = 0;
+
+    if (initialized)
+        return;
+
+    initialized = 1;
+
+    cyg_hal_plf_serial_init();
+}
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGPRI_HAL_IMPLEMENTS_IF_SERVICES
+
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#include <cyg/hal/hal_stub.h>           // cyg_hal_gdb_interrupt
+
+#if (CYGHWR_HAL_ARM_SA11X0_DIAG_PORT == 0)
+# define __BASE ((void*)SA11X0_UART1_BASE)
+#else
+# define __BASE ((void*)SA11X0_UART3_BASE)
+#endif
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+#if defined(CYG_HAL_STARTUP_ROM) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#elif defined(CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGHWR_HAL_ARM_SA11X0_DIAG_PORT != CYGHWR_HAL_ARM_SA11X0_GDB_PORT
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+void 
+hal_diag_init(void)
+{
+    // Init serial device
+    init_channel(__BASE);
+}
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+#ifdef DEBUG_DIAG
+#ifndef CYG_HAL_STARTUP_ROM
+#define DIAG_BUFSIZE 2048
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+#endif
+
+void hal_diag_read_char(char *c)
+{
+    *c = cyg_hal_plf_serial_getc(__BASE);
+}
+
+void hal_diag_write_char(char c)
+{
+#ifdef DEBUG_DIAG
+#ifndef CYG_HAL_STARTUP_ROM
+    diag_buffer[diag_bp++] = c;
+    if (diag_bp == sizeof(diag_buffer)) diag_bp = 0;
+#endif
+#endif
+    cyg_hal_plf_serial_putc(__BASE, c);
+}
+
+#else // not HAL_DIAG_USES_HARDWARE - it uses GDB protocol
+
+void 
+hal_diag_read_char(char *c)
+{
+    *c = cyg_hal_plf_serial_getc(__BASE);
+}
+
+void 
+hal_diag_write_char(char c)
+{
+    static char line[100];
+    static int pos = 0;
+
+    // FIXME: Some LED blinking might be nice right here.
+
+    // No need to send CRs
+    if( c == '\r' ) return;
+
+    line[pos++] = c;
+
+    if( c == '\n' || pos == sizeof(line) )
+    {
+        
+        CYG_INTERRUPT_STATE old;
+
+        // Disable interrupts. This prevents GDB trying to interrupt us
+        // while we are in the middle of sending a packet. The serial
+        // receive interrupt will be seen when we re-enable interrupts
+        // later.
+        
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+        CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+        HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+        while(1)
+        {
+            static char hex[] = "0123456789ABCDEF";
+            cyg_uint8 csum = 0;
+            int i;
+#ifndef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+            char c1;
+#endif        
+            cyg_hal_plf_serial_putc(__BASE, '$');
+            cyg_hal_plf_serial_putc(__BASE, 'O');
+            csum += 'O';
+            for( i = 0; i < pos; i++ )
+            {
+                char ch = line[i];
+                char h = hex[(ch>>4)&0xF];
+                char l = hex[ch&0xF];
+                cyg_hal_plf_serial_putc(__BASE, h);
+                cyg_hal_plf_serial_putc(__BASE, l);
+                csum += h;
+                csum += l;
+            }
+            cyg_hal_plf_serial_putc(__BASE, '#');
+            cyg_hal_plf_serial_putc(__BASE, hex[(csum>>4)&0xF]);
+            cyg_hal_plf_serial_putc(__BASE, hex[csum&0xF]);
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+
+            break; // regardless
+
+#else // not CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT Ie. usually...
+
+            // Wait for the ACK character '+' from GDB here and handle
+            // receiving a ^C instead.  This is the reason for this clause
+            // being a loop.
+            c1 = cyg_hal_plf_serial_getc(__BASE);
+
+            if( c1 == '+' )
+                break;              // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+            cyg_drv_interrupt_acknowledge(CYGHWR_HAL_GDB_PORT_VECTOR);
+            if( c1 == 3 ) {
+                // Ctrl-C: breakpoint.
+                cyg_hal_gdb_interrupt(
+                    (target_register_t)__builtin_return_address(0) );
+                break;
+            }
+#endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+
+#endif // ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+            // otherwise, loop round again
+        }
+        
+        pos = 0;
+
+        
+        // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+        CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+        HAL_RESTORE_INTERRUPTS(old);
+#endif
+        
+    }
+}
+#endif
+
+#endif // !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+
+/*---------------------------------------------------------------------------*/
+/* End of hal_diag.c */
diff --git a/packages/hal/arm/sa11x0/var/current/src/plf_stub.c b/packages/hal/arm/sa11x0/var/current/src/plf_stub.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/var/current/src/plf_stub.c
@@ -0,0 +1,212 @@
+//=============================================================================
+//
+//      plf_stub.c
+//
+//      Platform specific code for GDB stub support.
+//
+//=============================================================================
+//####COPYRIGHTBEGIN####
+//
+// -------------------------------------------
+// The contents of this file are subject to the Red Hat eCos Public License
+// Version 1.1 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://www.redhat.com/
+//
+// Software distributed under the License is distributed on an "AS IS"
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the
+// License for the specific language governing rights and limitations under
+// the License. 
+//
+// The Original Code is eCos - Embedded Configurable Operating System,
+// released September 30, 1998.
+//
+// The Initial Developer of the Original Code is Red Hat.
+// Portions created by Red Hat are
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
+// All Rights Reserved.
+// -------------------------------------------
+//
+//####COPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   gthomas
+// Contributors:gthomas, jskov
+//              Travis C. Furrer <furrer@mit.edu>
+// Date:        2000-05-08
+// Purpose:     Platform specific code for GDB stub support.
+//              
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/hal/hal_stub.h>
+
+#include <cyg/hal/hal_io.h>             // HAL IO macros
+#include <cyg/hal/hal_sa11x0.h>         // Hardware definitions
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+#include <cyg/hal/hal_intr.h>           // HAL interrupt macros
+#include <cyg/hal/drv_api.h>            // HAL ISR support
+#endif
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+static cyg_interrupt gdb_interrupt;
+static cyg_handle_t  gdb_interrupt_handle;
+#endif
+
+#if CYGHWR_HAL_ARM_SA11X0_GDB_PORT == 0
+#define CYG_GDB_DEV_UTCR0       SA11X0_UART1_CONTROL0
+#define CYG_GDB_DEV_UTCR1       SA11X0_UART1_CONTROL1
+#define CYG_GDB_DEV_UTCR2       SA11X0_UART1_CONTROL2
+#define CYG_GDB_DEV_UTCR3       SA11X0_UART1_CONTROL3
+#define CYG_GDB_DEV_UTDR        SA11X0_UART1_DATA
+#define CYG_GDB_DEV_UTSR0       SA11X0_UART1_STATUS0
+#define CYG_GDB_DEV_UTSR1       SA11X0_UART1_STATUS1
+#define CYG_GDB_DEV_INT         CYGNUM_HAL_INTERRUPT_UART1
+#else
+#define CYG_GDB_DEV_UTCR0       SA11X0_UART3_CONTROL0
+#define CYG_GDB_DEV_UTCR1       SA11X0_UART3_CONTROL1
+#define CYG_GDB_DEV_UTCR2       SA11X0_UART3_CONTROL2
+#define CYG_GDB_DEV_UTCR3       SA11X0_UART3_CONTROL3
+#define CYG_GDB_DEV_UTDR        SA11X0_UART3_DATA
+#define CYG_GDB_DEV_UTSR0       SA11X0_UART3_STATUS0
+#define CYG_GDB_DEV_UTSR1       SA11X0_UART3_STATUS1
+#define CYG_GDB_DEV_INT         CYGNUM_HAL_INTERRUPT_UART3
+#endif
+
+
+//-----------------------------------------------------------------------------
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+
+// This ISR is called only for serial receive interrupts.  This is true because
+// we do not enable Tx FIFO interrupts (in hal_sa11x0_init_serial, below).
+static int ISR_count, ISR_c;
+int 
+cyg_hal_gdb_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
+{
+    cyg_uint8 c;
+    c = hal_sa11x0_get_char();  // Fetch the character
+    ISR_count++;  ISR_c = c;
+    if( 3 == c ) {  // ^C
+        // Ctrl-C: set a breakpoint at PC so GDB will display the
+        // correct program context when stopping rather than the
+        // interrupt handler.
+        cyg_hal_gdb_interrupt (regs->pc);
+        // Clear receiver idle status bit, to allow another interrupt to
+        // occur in the case where the receive fifo is almost empty.
+        *CYG_GDB_DEV_UTSR0 = SA11X0_UART_RX_IDLE;
+    }
+    cyg_drv_interrupt_acknowledge(CYG_GDB_DEV_INT);
+    return 0;  // No need to run DSR
+}
+
+int 
+hal_sa11x0_interruptible(int state)
+{
+    if (state) {
+        cyg_drv_interrupt_unmask(CYG_GDB_DEV_INT);
+    } else {
+        cyg_drv_interrupt_mask(CYG_GDB_DEV_INT);
+    }
+    return 0;
+}
+#endif
+
+
+// Initialize the current serial port.
+void hal_sa11x0_init_serial(unsigned long baudRate)
+{
+    cyg_uint32 brd;
+
+    if (baudRate == 0) baudRate = CYGHWR_HAL_ARM_SA11X0_GDB_BAUD;
+
+    // Disable Receiver and Transmitter (clears FIFOs)
+    *CYG_GDB_DEV_UTCR3 = SA11X0_UART_RX_DISABLED |
+                         SA11X0_UART_TX_DISABLED;
+
+    // Clear sticky (writable) status bits.
+    *CYG_GDB_DEV_UTSR0 = SA11X0_UART_RX_IDLE |
+                         SA11X0_UART_RX_BEGIN_OF_BREAK |
+                         SA11X0_UART_RX_END_OF_BREAK;
+
+#if 0 // later
+#if CYGHWR_HAL_ARM_SA11X0_GDB_PORT == 1
+
+    //Set pin 14 as an output (Tx) and pin 15 as in input (Rx).
+    *SA11X0_REG_GPDR = (*SA11X0_REG_GPDR | SA11X0_GPIO_14) & ~SA11X0_GPIO_15;
+
+    // Use GPIO 14 & 15 pins for serial port 1.
+    *SA11X0_REG_GAFR |= SA11X0_GPIO_14 | SA11X0_GPIO_15;
+
+    // Pin reassignment for serial port 1.
+    *SA11X0_REG_PPAR |= SA11X0_UART_PIN_REASSIGNMENT_MASK;
+
+#endif
+#endif
+
+    // Set UART to 8N1 (8 data bits, no partity, 1 stop bit)
+    *CYG_GDB_DEV_UTCR0 = SA11X0_UART_PARITY_DISABLED |
+                         SA11X0_UART_STOP_BITS_1 |
+                         SA11X0_UART_DATA_BITS_8;
+
+    // Set the desired baud rate.
+    brd = SA11X0_UART_BAUD_RATE_DIVISOR(baudRate);
+    *CYG_GDB_DEV_UTCR1 = (brd >> 8) & SA11X0_UART_H_BAUD_RATE_DIVISOR_MASK;
+    *CYG_GDB_DEV_UTCR2 = brd & SA11X0_UART_L_BAUD_RATE_DIVISOR_MASK;
+
+    // Enable the receiver (with interrupts) and the transmitter.
+    *CYG_GDB_DEV_UTCR3 = SA11X0_UART_RX_ENABLED |
+                         SA11X0_UART_TX_ENABLED |
+                         SA11X0_UART_RX_FIFO_INT_ENABLED;
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+    cyg_drv_interrupt_create(CYG_GDB_DEV_INT,
+                             99,                     // Priority - what goes here?
+                             0,                      //  Data item passed to interrupt handler
+                             cyg_hal_gdb_isr,
+                             0,
+                             &gdb_interrupt_handle,
+                             &gdb_interrupt);
+    cyg_drv_interrupt_attach(gdb_interrupt_handle);
+    cyg_drv_interrupt_unmask(CYG_GDB_DEV_INT);
+#endif
+}
+
+// Write C to the current serial port.
+void hal_sa11x0_put_char(int c)
+{
+    // Wait for Tx FIFO not full
+    while ((*CYG_GDB_DEV_UTSR1 & SA11X0_UART_TX_FIFO_NOT_FULL) == 0)
+        ;
+    *CYG_GDB_DEV_UTDR = c;
+}
+
+// Read one character from the current serial port.
+// FIXME: shouldn't we check for PARITY_ERROR, FRAMING_ERROR, or
+// RECEIVE_FIFO_OVERRUN_ERROR in the received data?  This
+// means check the appropriate bits in UTSR1.
+int hal_sa11x0_get_char(void)
+{
+    long timeout = 1000000000;  // A long time...
+    int c;
+    // If receive fifo is empty, block and wait for a new char.
+    while ((*CYG_GDB_DEV_UTSR1 & SA11X0_UART_RX_FIFO_NOT_EMPTY) == 0)
+        if ( --timeout == 0 )
+            return -1;
+    c = *CYG_GDB_DEV_UTDR;
+    // Clear receiver idle status bit, to allow another interrupt to
+    // occur in the case where the receive fifo is almost empty.
+    *CYG_GDB_DEV_UTSR0 = SA11X0_UART_RX_IDLE;
+    return c;
+}
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+//-----------------------------------------------------------------------------
+// End of plf_stub.c
diff --git a/packages/hal/arm/sa11x0/var/current/src/sa11x0_misc.c b/packages/hal/arm/sa11x0/var/current/src/sa11x0_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/sa11x0/var/current/src/sa11x0_misc.c
@@ -0,0 +1,299 @@
+//==========================================================================
+//
+//      sa11x0_misc.c
+//
+//      HAL misc board support code for StrongARM SA11x0
+//
+//==========================================================================
+//####COPYRIGHTBEGIN####
+//
+// -------------------------------------------
+// The contents of this file are subject to the Red Hat eCos Public License
+// Version 1.1 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://www.redhat.com/
+//
+// Software distributed under the License is distributed on an "AS IS"
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the
+// License for the specific language governing rights and limitations under
+// the License. 
+//
+// The Original Code is eCos - Embedded Configurable Operating System,
+// released September 30, 1998.
+//
+// The Initial Developer of the Original Code is Red Hat.
+// Portions created by Red Hat are
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
+// All Rights Reserved.
+// -------------------------------------------
+//
+//####COPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: hmt
+//               Travis C. Furrer <furrer@mit.edu>
+// Date:         2000-05-08
+// Purpose:      HAL board support
+// Description:  Implementations of HAL board interfaces
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_arch.h>           // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h>           // Interrupt names
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_sa11x0.h>         // Hardware definitions
+
+#include <cyg/infra/diag.h>             // diag_printf
+
+// Most initialization has already been done before we get here.
+// All we do here is set up the interrupt environment.
+// FIXME: some of the stuff in hal_platform_setup could be moved here.
+
+externC void plf_hardware_init(void);
+
+void hal_hardware_init(void)
+{
+    // Mask all interrupts
+    *SA11X0_ICMR = 0;
+     
+    // Make all interrupts do IRQ and not FIQ
+    // FIXME: Change this if you use FIQs.
+    *SA11X0_ICLR = 0;
+     
+    // Prevent masked interrupts from bringing us out of idle mode
+    *SA11X0_ICCR = 1;
+
+    // Disable all GPIO interrupt sources
+    *SA11X0_GPIO_RISING_EDGE_DETECT = 0;
+    *SA11X0_GPIO_FALLING_EDGE_DETECT = 0;
+    *SA11X0_GPIO_EDGE_DETECT_STATUS = 0x0FFFFFFF;
+
+    // Perform any platform specific initializations
+    plf_hardware_init();
+
+    // Set up eCos/ROM interfaces
+    hal_if_init();
+
+    // Enable caches
+    HAL_DCACHE_ENABLE();
+    HAL_ICACHE_ENABLE();
+}
+
+
+// -------------------------------------------------------------------------
+static cyg_uint32  clock_period;
+
+void hal_clock_initialize(cyg_uint32 period)
+{
+    // Load match value
+    *SA11X0_OSMR0 = period;
+    clock_period = period;
+
+    // Start the counter
+    *SA11X0_OSCR = 0;
+
+    // Clear any pending interrupt
+    *SA11X0_OSSR = SA11X0_OSSR_TIMER0;
+
+    // Enable timer 0 interrupt    
+    *SA11X0_OIER |= SA11X0_OIER_TIMER0;
+
+    // Unmask timer 0 interrupt
+    HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_TIMER0 );
+
+    // That's all.
+}
+
+// This routine is called during a clock interrupt.
+
+// Define this if you want to ensure that the clock is perfect (i.e. does
+// not drift).  One reason to leave it turned off is that it costs some
+// 1.5us per system clock interrupt for this maintenance.
+#undef COMPENSATE_FOR_CLOCK_DRIFT
+
+void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
+{
+#ifdef COMPENSATE_FOR_CLOCK_DRIFT
+    cyg_int32 ctr = (cyg_int32)*SA11X0_OSCR;    // Current value of the counter
+    ctr -= period;                              // Reset counter
+    if ((ctr < 0) || (ctr >= period)) ctr = 0;  // Adjust for missed interrupts
+    *SA11X0_OSCR = ctr;
+    clock_period = period;
+#else
+    *SA11X0_OSCR = 0;
+#endif
+    *SA11X0_OSMR0 = period;                     // Load new match value
+    *SA11X0_OSSR = SA11X0_OSSR_TIMER0;          // Clear any pending interrupt
+}
+
+// Read the current value of the clock, returning the number of hardware
+// "ticks" that have occurred (i.e. how far away the current value is from
+// the start)
+
+// Note: The "contract" for this function is that the value is the number
+// of hardware clocks that have happened since the last interrupt (i.e.
+// when it was reset).  This value is used to measure interrupt latencies.
+// However, since the hardware counter does not automatically reset, as
+// many do, the value may be larger than the system "tick" interval.
+// If this turns out to be the case, the result will be adjusted to be
+// within the interval [0..N-1], where N is the number of hardware clocks/tick.
+
+void hal_clock_read(cyg_uint32 *pvalue)
+{
+    cyg_uint32 ctr = *SA11X0_OSCR;
+    if (ctr > clock_period) ctr -= clock_period;
+    *pvalue = ctr;
+}
+
+// -------------------------------------------------------------------------
+
+// This routine is called to respond to a hardware interrupt (IRQ).  It
+// should interrogate the hardware and return the IRQ vector number.
+int hal_IRQ_handler(void)
+{
+    cyg_uint32 sources, index;
+
+#if 0 // test FIQ and print alert if active - really for debugging
+    sources = *SA11X0_ICFP;
+    if ( 0 != sources )
+        diag_printf( "FIQ source active!!! - fiqstatus %08x irqstatus %08x\n",
+                     sources, *SA11X0_ICIP );
+    else
+#endif // Scan FIQ sources also
+
+    sources = *SA11X0_ICIP;
+
+// FIXME
+// if we come to support FIQ properly...
+//    if ( 0 == sources )
+//        sources = *SA11X0_ICFP;
+
+    // Nothing wrong with scanning them in any order we choose...
+    // So here we try to make the serial devices steal fewer cycles.
+    // So, knowing this is an ARM:
+    if ( sources & 0xff0000 )
+        index = 16;
+    else if ( sources & 0xff00 )
+        index = 8;
+    else if ( sources & 0xff )
+        index = 0;
+    else // if ( sources & 0xff000000 )
+        index = 24;
+
+    do {
+        if ( (1 << index) & sources ) {
+            if (index == CYGNUM_HAL_INTERRUPT_GPIO) {
+                // Special case of GPIO cascade.  Search for lowest set bit
+                sources = *SA11X0_GPIO_EDGE_DETECT_STATUS & 0x0FFFF800;
+                index = 11;
+                do {
+                    if (sources & (1 << index)) {
+                        index += 32;
+                        break;
+                    }
+                    index++;
+                } while (index < 28);
+            }
+            return index;
+        }
+      index++;
+    } while ( index & 7 );
+    
+    return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
+}
+
+//
+// Interrupt control
+//
+
+void hal_interrupt_mask(int vector)
+{
+    // Non-GPIO interrupt sources can be masked separately.
+    // Note: masking any non-unique GPIO signal (31..11) results in
+    // all GPIO signals (31..11) being masked as only the "lump"
+    // source will be changed.
+    if (vector >= CYGNUM_HAL_INTERRUPT_GPIO11) {
+        vector = CYGNUM_HAL_INTERRUPT_GPIO;
+    }
+    *SA11X0_ICMR &= ~(1 << vector);
+}
+
+void hal_interrupt_unmask(int vector)
+{
+    if (vector >= CYGNUM_HAL_INTERRUPT_GPIO11) {
+        vector = CYGNUM_HAL_INTERRUPT_GPIO;
+    }
+    *SA11X0_ICMR |= (1 << vector);
+}
+
+void hal_interrupt_acknowledge(int vector)
+{
+    // GPIO interrupts are driven by an edge detection mechanism.  This
+    // is latching so these interrupts must be acknowledged directly.
+    // All other interrupts simply go away when the interrupting unit
+    // has been serviced by the ISR.
+    if ((vector < CYGNUM_HAL_INTERRUPT_GPIO) || 
+        (vector >= CYGNUM_HAL_INTERRUPT_GPIO11)) {
+        *SA11X0_GPIO_EDGE_DETECT_STATUS  = (1 << (vector & 0x1F));
+    } else {
+        // Not a GPIO interrupt
+        return;
+    }
+}
+
+void hal_interrupt_configure(int vector, int level, int up)
+{
+    // This function can be used to configure the GPIO interrupts.  All
+    // of these pins can potentially generate an interrupt, but only
+    // 0..10 are unique.  Thus the discontinuity in the numbers.
+    // Also, if 'level' is true, then both edges are enabled if 'up' is
+    // true, otherwise they will be disabled.
+    // Non GPIO sources are ignored.
+    if ((vector < CYGNUM_HAL_INTERRUPT_GPIO) || 
+        (vector >= CYGNUM_HAL_INTERRUPT_GPIO11)) {
+        if (level) {
+            if (up) {
+                // Enable both edges
+                *SA11X0_GPIO_RISING_EDGE_DETECT |= (1 << (vector & 0x1F));
+                *SA11X0_GPIO_FALLING_EDGE_DETECT |= (1 << (vector & 0x1F));
+            } else {
+                // Disable both edges
+                *SA11X0_GPIO_RISING_EDGE_DETECT &= ~(1 << (vector & 0x1F));
+                *SA11X0_GPIO_FALLING_EDGE_DETECT &= ~(1 << (vector & 0x1F));
+            }
+        } else {
+            // Only interested in one edge
+            if (up) {
+                // Set rising edge detect and clear falling edge detect.
+                *SA11X0_GPIO_RISING_EDGE_DETECT |= (1 << (vector & 0x1F));
+                *SA11X0_GPIO_FALLING_EDGE_DETECT &= ~(1 << (vector & 0x1F));
+            } else {
+                // Set falling edge detect and clear rising edge detect.
+                *SA11X0_GPIO_FALLING_EDGE_DETECT |= (1 << (vector & 0x1F));
+                *SA11X0_GPIO_RISING_EDGE_DETECT &= ~(1 << (vector & 0x1F));
+            }
+        }
+    }
+}
+
+void hal_interrupt_set_level(int vector, int level)
+{
+    // Interrupt priorities are not configurable on the SA11X0.
+}
+
+/*------------------------------------------------------------------------*/
+// EOF sa11x0_misc.c
diff --git a/packages/hal/common/current/ChangeLog b/packages/hal/common/current/ChangeLog
--- a/packages/hal/common/current/ChangeLog
+++ b/packages/hal/common/current/ChangeLog
@@ -697,6 +697,7 @@ 1999-04-27  Jesper Skov  <jskov@cygnus.c
 
 	* include/pkgconf/hal.h: GDB_BREAK support now available for ARM
 	targets.
+
 1999-04-16  Bart Veer  <bartv@cygnus.co.uk>
 
 	* src/PKGconf.mak: 
diff --git a/packages/io/serial/current/tests/ser_test_protocol.inl b/packages/io/serial/current/tests/ser_test_protocol.inl
--- a/packages/io/serial/current/tests/ser_test_protocol.inl
+++ b/packages/io/serial/current/tests/ser_test_protocol.inl
@@ -131,6 +131,15 @@
 #  define TEST_TTY_DEV CYGDAT_IO_SERIAL_TTY_TTY1_DEV
 # endif
 #endif
+#if defined(CYGPKG_HAL_ARM_SA11X0_ASSABET)                    \
+    && defined(CYGPKG_IO_SERIAL_ARM_SA11X0)                \
+    && defined(CYGPKG_IO_SERIAL_ARM_SA11X0_SERIAL1)
+# define TEST_CRASH_ID "assabet"
+# define TEST_SER_DEV CYGDAT_IO_SERIAL_ARM_SA11X0_SERIAL1_NAME
+# if defined(CYGPKG_IO_SERIAL_TTY_TTY1)
+#  define TEST_TTY_DEV CYGDAT_IO_SERIAL_TTY_TTY1_DEV
+# endif
+#endif
 #if defined(CYGPKG_HAL_MIPS_TX39_JMR3904)               \
     && defined(CYGPKG_IO_SERIAL_TX39_JMR3904)           \
     && defined(CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0)
diff --git a/packages/kernel/current/tests/dhrystone.c b/packages/kernel/current/tests/dhrystone.c
--- a/packages/kernel/current/tests/dhrystone.c
+++ b/packages/kernel/current/tests/dhrystone.c
@@ -64,6 +64,8 @@ dtime(void)
 #define PASSES 100000
 #elif defined(CYGPKG_HAL_ARM_EBSA285)
 #define PASSES 1000000
+#elif defined(CYGPKG_HAL_ARM_SA11X0)
+#define PASSES 1000000
 #elif defined(CYGPKG_HAL_ARM_CMA230)
 #define PASSES 100000
 #elif defined(CYGPKG_HAL_V85X_V850_CEB)
diff --git a/packages/language/c/libm/current/ChangeLog b/packages/language/c/libm/current/ChangeLog
--- a/packages/language/c/libm/current/ChangeLog
+++ b/packages/language/c/libm/current/ChangeLog
@@ -155,6 +155,7 @@ 1999-04-06  Gary Thomas  <gthomas@cygnus
 
 	* src/PKGconf.mak: More brute-force fix for ARM compiler
 	problems - PR 19772
+
 1999-03-31  Jonathan Larmour  <jlarmour@cygnus.co.uk>
 
 	* include/pkgconf/libm.h: Remove unnecessary define
diff --git a/packages/net/tcpip/current/ChangeLog b/packages/net/tcpip/current/ChangeLog
--- a/packages/net/tcpip/current/ChangeLog
+++ b/packages/net/tcpip/current/ChangeLog
@@ -1,3 +1,8 @@
+2000-07-04  Hugo Tyson  <hmt@cygnus.co.uk>
+
+	* include/bootp.h: Fix namespace pollution from "#define int32
+	int" - it fights against application code too much.
+
 2000-06-26  Hugo Tyson  <hmt@cygnus.co.uk>
 
 	* tests/ping_test.c (net_test): Added use of the
diff --git a/packages/net/tcpip/current/include/bootp.h b/packages/net/tcpip/current/include/bootp.h
--- a/packages/net/tcpip/current/include/bootp.h
+++ b/packages/net/tcpip/current/include/bootp.h
@@ -86,7 +86,7 @@ SOFTWARE.
  */
 
 #ifdef __ECOS
-#define int32 int
+#include <machine/types.h>
 #else
 #include "bptypes.h"	/* for int32, u_int32 */
 #endif
@@ -102,7 +102,11 @@ struct bootp {
     unsigned char    bp_htype;			/* hardware addr type */
     unsigned char    bp_hlen;			/* hardware addr length */
     unsigned char    bp_hops;			/* gateway hops */
-    unsigned int32   bp_xid;			/* transaction ID */
+#ifdef __ECOS
+    u_int32_t        bp_xid;			/* transaction ID */
+#else
+    unsigned int     bp_xid;			/* transaction ID */
+#endif
     unsigned short   bp_secs;			/* seconds since boot began */
     unsigned short   bp_flags;			/* RFC1532 broadcast, etc. */
     struct in_addr   bp_ciaddr;			/* client IP address */
@@ -295,13 +299,21 @@ struct bootp {
 
 struct cmu_vend {
 	char		v_magic[4];	/* magic number */
-	unsigned int32	v_flags;	/* flags/opcodes, etc. */
+#ifdef __ECOS
+	u_int32_t	v_flags;	/* flags/opcodes, etc. */
+#else
+        unsigned int32  v_flags;        /* flags/opcodes, etc. */
+#endif
 	struct in_addr 	v_smask;	/* Subnet mask */
 	struct in_addr 	v_dgate;	/* Default gateway */
 	struct in_addr	v_dns1, v_dns2; /* Domain name servers */
 	struct in_addr	v_ins1, v_ins2; /* IEN-116 name servers */
 	struct in_addr	v_ts1, v_ts2;	/* Time servers */
-	int32		v_unused[6];	/* currently unused */
+#ifdef __ECOS
+	int32_t		v_unused[6];	/* currently unused */
+#else
+        int32           v_unused[6];	/* currently unused */
+#endif
 };