Mercurial > ecos
changeset 3140:53660cdf5b22
Add STM3220G-EVAL / STM3240G-EVAL board support, contributed by eCosCentric
line wrap: on
line diff
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/ChangeLog @@ -0,0 +1,184 @@ +2012-03-29 Jonathan Larmour <jifl@eCosCentric.com> + + * include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi: + Correct number of VSR table entries. + * src/stm32x0g_eval_misc.c (hal_platform_init): Add assertion checks + that layout of vector tables at bottom of SRAM is what it should be. + +2012-03-29 James Smith <jsmith@ecoscentric.com> + + * include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi: + Provide hal_virtual_vector_table_end symbol to allow the + SECTION_sram pre-allocation to be minimised to the actual platform + requirements. + + * src/stm32x0g_eval_misc.c: Provide #error check on linker script + hardwired CYGNUM_CALL_IF_TABLE_SIZE assumption. + +2012-03-23 James Smith <jsmith@ecoscentric.com> + + * include/plf_io.h: Update GPIO pin definitions to use new PIN + wrapper macros. Update the I2C lines to specify PULLUP. + +2012-03-22 James Smith <jsmith@ecoscentric.com> + + * include/plf_io.h (CYGHWR_HAL_STM32_ETH_MII_*): Platform specific + ethernet pin manifests updated to use new GPIO PIN macros. + +2012-03-15 James Smith <jsmith@ecoscentric.com> + + * cdl/hal_cortexm_stm32_stm32x0g_eval.cdl: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.h: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi: + * src/stm32x0g_eval_flash.c: + * src/stm32x0g_eval_misc.c: + * src/stm32x0g_eval_spi.c: + Rename platform from the name "stm3220g_eval" to the generic name + "stm32x0g_eval". This is to make it clear that the platform + supports both the F2 (STM3220G-EVAL) and F4 (STM3240G-EVAL) + platforms. This rename includes renaming of the relevant support + source files. + + * include/plf_io.h (HAL_I2C_EXPORTED_DEVICES): Declare I2C bus1 + for on-board M24C64 device. + +2012-02-08 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32_stm3220g_eval.cdl + (CYGPKG_HAL_CORTEXM_STM32_STM3220G_EVAL_SPI): This should now be a component + since it has no children. Also make description match configuration (Aardvark + expected to be on bus 2). + +2012-02-05 Jonathan Larmour <jifl@eCosCentric.com> + + * misc/redboot_JTAG.ecm, misc/redboot_ROM.ecm: Build in inferences + so there's no output on import. + * misc/redboot_RAM.ecm: New file. For completeness and to make it + easier for RedBoot to update itself. + * cdl/hal_cortexm_stm32_stm3220g_eval.cdl: Make comment description of + UART selection and naming clearer. + +2012-01-31 Jonathan Larmour <jifl@eCosCentric.com> + + * include/plf_io.h: Prototype hal_stm3220_led() for setting board LEDs. + * src/stm3220g_eval_misc.c: Choose correct board SRAM memory timings. + +2012-01-13 Nick Garnett <nickg@ecoscentric.com> + + * misc/redboot_ROM.ecm: + * misc/redboot_JTAG.ecm: Add CYGPKG_IO_WALLCLOCK package to enable + date command for setting on-chip RTC. + +2012-01-12 Nick Garnett <nickg@ecoscentric.com> + + * cdl/hal_cortexm_stm32_stm3220g_eval.cdl: Add SPI and I2C + configuration options. + + * include/plf_io.h: Add SPI and I2C pin and DMA stream definitions. + + * src/stm3220g_eval_spi.c: Add SPI device definition for aardvark + board. + +2011-12-20 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32_stm3220g_eval.cdl: Just set a requires on + RedBoot's number of memory segments to be 2 rather than using a + non-configurable option. + +2011-12-15 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32_stm3220g_eval.cdl + (CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES): New option. Configures + Flash wait states. + (CYGPKG_HAL_CORTEXM_STM32_STM3220G_EVAL_ETH0): New component. Holds + options and CDL to configure ethernet support. + Change default baud rate to 115200. + * include/pkgconf/mlt_cortexm_stm3220g_eval_jtag.h: Add definitions for + sram and flash regions. + * include/pkgconf/mlt_cortexm_stm3220g_eval_ram.h: Add definitions for + flash region. + * include/pkgconf/mlt_cortexm_stm3220g_eval_sram.h: Ditto. Also fix + external SRAM address. + * include/pkgconf/mlt_cortexm_stm3220g_eval_sram.ldi: Fix external SRAM + address. + * include/plf_io.h: Provide platform specific ethernet pin mappings. + (CYGHWR_HAL_STM32_ETH_CONFIGURE_MCO): New macro used to configure MCO1 + as PHY clock. + * misc/redboot_JTAG.ecm, misc/redboot_ROM.ecm: Don't disable + CYGOPT_REDBOOT_FIS_REDBOOT nor CYGOPT_REDBOOT_FIS_REDBOOT_POST - there + is only one flash here and it does contain RedBoot. + * src/stm3220g_eval_flash.c: No longer define private flash structure + here. Internal flash support is no longer an option in this file if this + file is used at all. + * src/stm3220g_eval_misc.c (hal_system_init): Clear FSMC reset bit after + reset otherwise it stays there. + Configure USART4 TX/RX on PC10/11 otherwise RedBoot can get confused. + Set Flash wait states as per configuration. + (cyg_plf_memory_segment): Allow for renaming of external SRAM region to + xram. + +2011-12-12 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32_stm3220g_eval.cdl: Set PLLQ. + +2011-12-08 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32_stm3220g_eval.cdl: + * include/plf_arch.h: + * include/plf_intr.h: + * include/plf_io.h: + * include/pkgconf/mlt_cortexm_stm3220g_eval_jtag.h: + * include/pkgconf/mlt_cortexm_stm3220g_eval_jtag.ldi: + * include/pkgconf/mlt_cortexm_stm3220g_eval_ram.h: + * include/pkgconf/mlt_cortexm_stm3220g_eval_ram.ldi: + * include/pkgconf/mlt_cortexm_stm3220g_eval_rom.h: + * include/pkgconf/mlt_cortexm_stm3220g_eval_romint.h: + * include/pkgconf/mlt_cortexm_stm3220g_eval_romint.ldi: + * include/pkgconf/mlt_cortexm_stm3220g_eval_rom.ldi: + * include/pkgconf/mlt_cortexm_stm3220g_eval_sram.h: + * include/pkgconf/mlt_cortexm_stm3220g_eval_sram.ldi: + * misc/redboot_JTAG.ecm: + * misc/redboot_ROM.ecm: + * src/stm3220g_eval_flash.c: + * src/stm3220g_eval_misc.c: + New package -- ST STM3220G EVAL board HAL. Derived from STM3210E HAL. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/cdl/hal_cortexm_stm32_stm32x0g_eval.cdl @@ -0,0 +1,471 @@ +##========================================================================== +## +## hal_cortexm_stm32_stm32x0g_eval.cdl +## +## Cortex-M STM32X0G EVAL platform HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2012 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): jlarmour +## Based on: stm3210e CDL by nickg +## Date: 2011-11-10 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL { + display "ST STM32x0G-EVAL (STM32 20-21-45-46 G-EVAL) Development Board HAL" + parent CYGPKG_HAL_CORTEXM_STM32 + requires { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4")) } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") ? (CYGHWR_HAL_CORTEXM_STM32_F2 == "F207IG") : (CYGHWR_HAL_CORTEXM_STM32_F4 == "F407IG") } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM == "M3") } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM == "M4") } + # 25MHz crystal feeds HSE + # From STM32F4xx Rev A System Clock Configuration v1.0.1 + # SYSCLK 120MHz 168MHz + # ------ ------ ------ + # HSE 25MHz 25MHz fixed input crystal on board : CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK + # PLL_M 25 25 (6bits) main divisor + # PLL_N 240 336 (9bits) main multiplier + # PLL_P 2 2 (2bits) derived from PLL_N : used for SYSCLK (must not exceed F2:120 or F4:168) + # PLL_Q 5 7 (4bits) derived from PLL_N : used for USB OTG FS, SDIO and RNG (must be >= 2) + # AHB Prescaler 1 1 + # SYSCLK 120MHz 168MHz (((HSE / PLL_M) * PLL_N) / PLL_P) + # HCLK 120MHz 168MHz (SYSCLK / AHB Prescaler) + # APB1 Prescaler 4 4 + # PCLK1 30MHz 42MHz (HCLK / APB1 Prescaler) + # APB2 Prescaler 2 2 + # PCLK2 60MHz 84MHz (HCLK / APB2 Prescaler) + # + # Must use HSE for the PLL settings below + requires { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE == "HSE" } + # F2: + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV == 15) } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL == 288) } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV == 4) } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV == 10) } + # F4: + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV == 25) } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL == 336) } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV == 2) } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV == 7) } + # Common: + requires { CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 1 } + requires { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 4 } + requires { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 2 } + +# define_header hal_cortexm_stm32_stm32x0g_eval.h + include_dir cyg/hal + hardware + description " + The STM32x0G EVAL HAL package provides the support needed to run + eCos on the ST STM32 20-21-45-46 G-EVAL board." + + compile stm32x0g_eval_misc.c + + cdl_option CYGPKG_HAL_CORTEXM_STM32_STM3220G_EVAL { + display "Platform definitions for STM3220G-EVAL (F2) board." + active_if { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2" } + no_define + calculated 1 + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_cortexm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_cortexm_stm32.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"Cortex-M3\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"ST STM3220G-EVAL\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + } + + cdl_option CYGPKG_HAL_CORTEXM_STM32_STM3240G_EVAL { + display "Platform definitions for STM3240G-EVAL (F4) board." + active_if { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4" } + no_define + calculated 1 + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_cortexm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_cortexm_stm32.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"Cortex-M4\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"ST STM3240G-EVAL\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"RAM"} + legal_values {"RAM" "SRAM" "ROM" "ROMINT" "JTAG"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the ST STM32X0G EVAL board it is possible to + build the system for either RAM bootstrap or ROM bootstrap. + Select 'RAM' when building programs to load into RAM using onboard + debug software such as RedBoot or eCos GDB stubs. Select 'ROM' + when building a stand-alone application which will be put + into ROM. The 'JTAG' type allows programs to be downloaded using a + JTAG debugger such as a BDI3000 or PEEDI. The 'SRAM' type allows + programs to be downloaded via a JTAG debugger into on-chip SRAM. + The 'ROMINT' type supports applications with code in on-chip flash + and data/bss in on-chip SRAM, ignoring the external SRAM." + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { (CYG_HAL_STARTUP == "RAM" ) ? "cortexm_stm32x0g_eval_ram" : + (CYG_HAL_STARTUP == "SRAM" ) ? "cortexm_stm32x0g_eval_sram" : + (CYG_HAL_STARTUP == "ROM" ) ? "cortexm_stm32x0g_eval_rom" : + (CYG_HAL_STARTUP == "ROMINT" ) ? "cortexm_stm32x0g_eval_romint" : + (CYG_HAL_STARTUP == "JTAG" ) ? "cortexm_stm32x0g_eval_jtag" : + "undefined" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" } + } + + } + + cdl_option CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK { + display "Input Clock frequency" + flavor data + default_value 25000000 + legal_values 0 to 1000000000 + description "Main clock input." + } + + cdl_option CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES { + display "Flash read wait states" + flavor data + default_value { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") ? 3 : 5 } + legal_values 0 to 7 + description " + This option gives the number of wait states to use for accessing + the flash for reads. The correct setting for this value depends + on both the CPU clock (HCLK) frequency and the voltage. Consult + the STM32 Flash programming manual (PM0059) for appropriate + values for different clock speeds or voltages. The default of + 3 reflects a supply voltage of 3.3V and HCLK of 120MHz." + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_FLASH { + display "Flash driver support" + parent CYGPKG_IO_FLASH + active_if CYGPKG_IO_FLASH + compile -library=libextras.a stm32x0g_eval_flash.c + default_value 1 + description "Control flash device support for STM32X0G-EVAL board." + } + + cdl_component CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL_ETH0 { + display "STM32 Ethernet support" + description " + Hardware specifics for the ethernet interface provided on the + STM32X0G-EVAL board." + parent CYGPKG_IO_ETH_DRIVERS + active_if CYGPKG_IO_ETH_DRIVERS + default_value 1 + requires CYGPKG_DEVS_ETH_CORTEXM_STM32 + requires { is_active(CYGPKG_DEVS_ETH_PHY) implies + (1 == CYGHWR_DEVS_ETH_PHY_DP83847) } + requires { is_active(CYGHWR_HAL_CORTEXM_STM32X0G_ETH_PHY_CLOCK_MCO) implies \ + (CYGHWR_DEVS_ETH_CORTEXM_STM32_PHY_CLK_MCO == CYGHWR_HAL_CORTEXM_STM32X0G_ETH_PHY_CLOCK_MCO) } + + cdl_option CYGHWR_HAL_CORTEXM_STM32X0G_ETH_PHY_CLOCK_MCO { + display "Use MCO as PHY clock" + default_value 1 + description " + The STM32X0G can use the MCO clock signals as the 25MHz clock for + the PHY, or it can use the onboard 25MHz crystal at X1, depending + on the setting of jumper J5. This option should be set to reflect + the J5 setting." + } + } + + implements CYGINT_HAL_VIRTUAL_VECTOR_VPRINTF + + # The 9-pin D connector is connected to PC10 and PC11, which are connected to + # USART3 or UART4 depending on pin config. The main difference between these + # ports is that UART4 doesn't support hardware flow control. This board doesn't + # have the flow control lines hooked up anyway, so to save having to fiddle + # with ignoring the flow control lines on USART3, we choose to use UART4. + # Note that this is UART4 in STM32 speak (counting from 1), but the STM32 port + # uses the name UART3 for it (counting from 0). Hrm. + implements CYGINT_HAL_STM32_UART3 + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + calculated 0 + description " + The ST STM32X0G EVAL board has one serial port. This option + informs the rest of the system which port will be used to connect + to a host running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + calculated 0 + description " + The ST STM32X0G EVAL has one serial port. This option + informs the rest of the system which port will be used for + diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Console serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 115200 + description " + This option controls the default baud rate used for the + console connection. + RedBoot usess polling to transfer data over this port and + might not be able to keep up with baud rates above the + default, particularly when doing XYZmodem downloads. The + interrupt-driven device driver is able to handle these + baud rates, so any high speed application transfers should + use that instead. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 115200 + # Only one channel on this board so: + requires { CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD == CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD } + description " + This option controls the default baud rate used for the + GDB connection. + RedBoot usess polling to transfer data over this port and + might not be able to keep up with baud rates above the + default, particularly when doing XYZmodem downloads. The + interrupt-driven device driver is able to handle these + baud rates, so any high speed application transfers should + use that instead. + Note: this should match the value chosen for the console port if the + console and GDB port are the same." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-eabi" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_component CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL_OPTIONS { + display "STM32X0G HAL build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this HAL." + + cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "-Werror" } + description " + This option modifies the set of compiler flags + for building this HAL. These flags are used + in addition to the set of global flags." + } + cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags + for building this HAL. These flags are + removed from the set of global flags if + present." + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMINT" || CYG_HAL_STARTUP == "JTAG" } + requires { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGBLD_REDBOOT_MAX_MEM_SEGMENTS == 2) } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGBLD_REDBOOT_MAX_MEM_SEGMENTS == 3) } + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary images" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to binary image formats suitable for ROM programming." + + make -priority 325 { + <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + } + } + + cdl_component CYGBLD_HAL_CORTEXM_STM32X0G_EVAL_GDB_STUBS { + display "Create StubROM SREC and binary files" + active_if CYGBLD_BUILD_COMMON_GDB_STUBS + no_define + calculated 1 + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMINT" } + + make -priority 325 { + <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O srec $< $@ + } + make -priority 325 { + <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + + description "This component causes the ELF image generated by the + build process to be converted to S-Record and binary + files." + } +} + +# EOF hal_cortexm_stm32_stm32x0g_eval.cdl
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.h @@ -0,0 +1,26 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGMEM_REGION_ccm (0x10000000) +#define CYGMEM_REGION_ccm_SIZE (0x00010000) +#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#define CYGMEM_REGION_flash (0x08000000) +#define CYGMEM_REGION_flash_SIZE (0x00100000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ram (0x64000000) +#define CYGMEM_REGION_ram_SIZE (0x00200000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi @@ -0,0 +1,50 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x08000000, LENGTH = 0x00100000 + ram : ORIGIN = 0x64000000, LENGTH = 0x00200000 +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) + ccm : ORIGIN = 0x10000000, LENGTH = 0x00010000 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +} + +hal_vsr_table = 0x20000000; +// 97 or 98 entries in this VSR table depending on the processor family +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2) +hal_virtual_vector_table = hal_vsr_table + 97*4; +#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +hal_virtual_vector_table = hal_vsr_table + 98*4; +#endif +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) +hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4; +#else // zero size virtual vector table +hal_virtual_vector_table_end = hal_virtual_vector_table; +#endif + +// SRAM is 128k. +hal_startup_stack = 0x20000000 + 1024*128; + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_sram (sram, hal_virtual_vector_table_end, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x64000000, LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.h @@ -0,0 +1,28 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00020000) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGMEM_REGION_ccm (0x10000000) +#define CYGMEM_REGION_ccm_SIZE (0x00010000) +#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#define CYGMEM_REGION_flash (0x08000000) +#define CYGMEM_REGION_flash_SIZE (0x00100000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ram (0x64000000) +#define CYGMEM_REGION_ram_SIZE (0x00200000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi @@ -0,0 +1,50 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 0x00020000 + flash : ORIGIN = 0x08000000, LENGTH = 0x00100000 + ram : ORIGIN = 0x64000000, LENGTH = 0x00200000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) + ccm : ORIGIN = 0x10000000, LENGTH = 0x00010000 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +} + +hal_vsr_table = 0x20000000; +// 97 or 98 entries in this VSR table depending on the processor family +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2) +hal_virtual_vector_table = hal_vsr_table + 97*4; +#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +hal_virtual_vector_table = hal_vsr_table + 98*4; +#endif +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) +hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4; +#else // zero size virtual vector table +hal_virtual_vector_table_end = hal_virtual_vector_table; +#endif + +// External SRAM is 2MB +hal_startup_stack = 0x64200000; + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_sram (sram, hal_virtual_vector_table_end, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x64008000, LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.h @@ -0,0 +1,26 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGMEM_REGION_ccm (0x10000000) +#define CYGMEM_REGION_ccm_SIZE (0x00010000) +#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#define CYGMEM_REGION_flash (0x08000000) +#define CYGMEM_REGION_flash_SIZE (0x00100000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ram (0x64000000) +#define CYGMEM_REGION_ram_SIZE (0x00200000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi @@ -0,0 +1,51 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x08000000, LENGTH = 0x00100000 + ram : ORIGIN = 0x64000000, LENGTH = 0x00200000 +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) + ccm : ORIGIN = 0x10000000, LENGTH = 0x00010000 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +} + + +hal_vsr_table = 0x20000000; +// 97 or 98 entries in this VSR table depending on the processor family +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2) +hal_virtual_vector_table = hal_vsr_table + 97*4; +#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +hal_virtual_vector_table = hal_vsr_table + 98*4; +#endif +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) +hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4; +#else // zero size virtual vector table +hal_virtual_vector_table_end = hal_virtual_vector_table; +#endif + +// SRAM is 128k. +hal_startup_stack = 0x20000000 + 1024*128; + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x08000000, LMA_EQ_VMA) + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram, hal_virtual_vector_table_end, FOLLOWING (.got)) + SECTION_data (ram, 0x64000000, FOLLOWING (.sram)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.h @@ -0,0 +1,26 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x20000000) +#define CYGMEM_REGION_ram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGMEM_REGION_ccm (0x10000000) +#define CYGMEM_REGION_ccm_SIZE (0x00010000) +#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#define CYGMEM_REGION_flash (0x08000000) +#define CYGMEM_REGION_flash_SIZE (0x00100000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_xram (0x64000000) +#define CYGMEM_REGION_xram_SIZE (0x00200000) +#define CYGMEM_REGION_xram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi @@ -0,0 +1,50 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x08000000, LENGTH = 0x00100000 + xram : ORIGIN = 0x64000000, LENGTH = 0x00200000 +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) + ccm : ORIGIN = 0x10000000, LENGTH = 0x00010000 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +} + +hal_vsr_table = 0x20000000; +// 97 or 98 entries in this VSR table depending on the processor family +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2) +hal_virtual_vector_table = hal_vsr_table + 97*4; +#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +hal_virtual_vector_table = hal_vsr_table + 98*4; +#endif +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) +hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4; +#else // zero size virtual vector table +hal_virtual_vector_table_end = hal_virtual_vector_table; +#endif + +// SRAM is 128k. +hal_startup_stack = 0x20000000 + 1024*128; + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x08000000, LMA_EQ_VMA) + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (ram, hal_virtual_vector_table_end, FOLLOWING (.got)) + SECTION_data (ram, ALIGN( 0x8), FOLLOWING (.sram)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.h @@ -0,0 +1,28 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGMEM_REGION_ccm (0x10000000) +#define CYGMEM_REGION_ccm_SIZE (0x00010000) +#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#define CYGMEM_REGION_flash (0x08000000) +#define CYGMEM_REGION_flash_SIZE (0x00100000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ram (0x64000000) +#define CYGMEM_REGION_ram_SIZE (0x00100000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi @@ -0,0 +1,51 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x08000000, LENGTH = 0x00100000 + ram : ORIGIN = 0x64000000, LENGTH = 0x00200000 +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) + ccm : ORIGIN = 0x10000000, LENGTH = 0x00010000 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +} + + +hal_vsr_table = 0x20000000; +// 97 or 98 entries in this VSR table depending on the processor family +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2) +hal_virtual_vector_table = hal_vsr_table + 97*4; +#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +hal_virtual_vector_table = hal_vsr_table + 98*4; +#endif +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) +hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4; +#else // zero size virtual vector table +hal_virtual_vector_table_end = hal_virtual_vector_table; +#endif + +// SRAM is 128k. +hal_startup_stack = 0x20000000 + 1024*128; + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (sram, hal_virtual_vector_table_end, LMA_EQ_VMA) + SECTION_RELOCS (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (sram, ALIGN(0x8), LMA_EQ_VMA) + SECTION_rodata1 (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_arch.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_PLF_ARCH_H +#define CYGONCE_HAL_PLF_ARCH_H +//============================================================================= +// +// plf_arch.h +// +// Platform specific architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Purpose: STM32X0G EVAL platform specific architecture overrides +// Description: +// Usage: #include <cyg/hal/plf_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_arch.h +#endif // CYGONCE_HAL_PLF_ARCH_H
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_intr.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H +//============================================================================= +// +// plf_intr.h +// +// Platform specific interrupt overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Purpose: STM32X0G EVAL platform specific interrupt overrides +// Description: +// Usage: #include <cyg/hal/plf_intr.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_intr.h +#endif // CYGONCE_HAL_PLF_INTR_H
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_io.h @@ -0,0 +1,171 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// Platform specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Purpose: STM32X0G EVAL platform specific registers +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h> + +//============================================================================= +// Memory access checks. +// +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. These macros allow the GDB stubs to avoid making +// accidental accesses to these areas. + +__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ); + +#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +//============================================================================= +// Board LEDs + +#define CYGHWR_HAL_STM32X0G_LED1 CYGHWR_HAL_STM32_PIN_OUT( G, 6, PUSHPULL, NONE, LOW ) +#define CYGHWR_HAL_STM32X0G_LED2 CYGHWR_HAL_STM32_PIN_OUT( G, 8, PUSHPULL, NONE, LOW ) +#define CYGHWR_HAL_STM32X0G_LED3 CYGHWR_HAL_STM32_PIN_OUT( I, 9, PUSHPULL, NONE, LOW ) +#define CYGHWR_HAL_STM32X0G_LED4 CYGHWR_HAL_STM32_PIN_OUT( C, 7, PUSHPULL, NONE, LOW ) + +// A convenience function to set LEDs. Lowest 4 bits of 'c' correspond to the 4 LEDs. +__externC void hal_stm32x0_led(char c); + +//============================================================================= +// Custom Ethernet pin mappings + +#define CYGHWR_HAL_STM32_ETH_MII_TX_CRS CYGHWR_HAL_STM32_PIN_ALTFN_IN( H, 2, 11, OPENDRAIN, NONE ) +#define CYGHWR_HAL_STM32_ETH_MII_COL CYGHWR_HAL_STM32_PIN_ALTFN_IN( H, 3, 11, OPENDRAIN, NONE ) +#define CYGHWR_HAL_STM32_ETH_MII_RXD2 CYGHWR_HAL_STM32_PIN_ALTFN_IN( H, 6, 11, OPENDRAIN, NONE ) +#define CYGHWR_HAL_STM32_ETH_MII_RXD3 CYGHWR_HAL_STM32_PIN_ALTFN_IN( H, 7, 11, OPENDRAIN, NONE ) +#define CYGHWR_HAL_STM32_ETH_MII_TXD3 CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 8, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_RX_ER CYGHWR_HAL_STM32_PIN_ALTFN_IN( I, 10, 11, OPENDRAIN, NONE ) +#define CYGHWR_HAL_STM32_ETH_MII_TX_EN CYGHWR_HAL_STM32_PIN_ALTFN_OUT( G, 11, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_TXD0 CYGHWR_HAL_STM32_PIN_ALTFN_OUT( G, 13, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_TXD1 CYGHWR_HAL_STM32_PIN_ALTFN_OUT( G, 14, 11, PUSHPULL, NONE, AT_LEAST(50) ) +// NOTE: CYGHWR_HAL_STM32_ETH_MII_PPS_OUT not defined + +#define CYGHWR_HAL_STM32_ETH_CONFIGURE_MCO() \ + CYG_MACRO_START \ + cyg_uint32 cfgr; \ + HAL_READ_UINT32( CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_CFGR, cfgr ); \ + cfgr &= ~CYGHWR_HAL_STM32_RCC_CFGR_MCO1_MASK; \ + cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_MCO1_HSE; \ + cfgr &= ~CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_MASK; \ + cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_1; \ + HAL_WRITE_UINT32( CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_CFGR, cfgr ); \ + CYG_MACRO_END + +//============================================================================= +// GPIO pin and DMA definitions for each SPI bus + +// NOTE: The SPEED_SPI manifest is declared by the device driver +// (e.g. "devs/spi/cortexm/stm32/<vsn>/src/spi_stm32.c") and is not +// currently defined in a header. + +#ifndef CYGHWR_HAL_STM32_SPI1_REMAP +#define CYGHWR_HAL_STM32_SPI1_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A, 5, 5, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI1_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( A, 6, 5, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI1_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A, 7, 5, PUSHPULL, NONE, SPEED_SPI ) +#else +#define CYGHWR_HAL_STM32_SPI1_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 3, 5, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI1_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( B, 4, 5, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI1_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 5, 5, PUSHPULL, NONE, SPEED_SPI ) +#endif +#define CYGHWR_HAL_STM32_SPI1_REMAP_CONFIG 0 + +#define CYGHWR_HAL_STM32_SPI1_DMA_TX CYGHWR_HAL_STM32_DMA( 2, 3, 3, M2P ) +#define CYGHWR_HAL_STM32_SPI1_DMA_RX CYGHWR_HAL_STM32_DMA( 2, 0, 3, P2M ) + + + +#define CYGHWR_HAL_STM32_SPI2_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( I, 1, 5, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI2_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( I, 2, 5, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI2_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( I, 3, 5, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI2_REMAP_CONFIG 0 + +#define CYGHWR_HAL_STM32_SPI2_DMA_TX CYGHWR_HAL_STM32_DMA( 1, 4, 0, M2P ) +#define CYGHWR_HAL_STM32_SPI2_DMA_RX CYGHWR_HAL_STM32_DMA( 1, 3, 0, P2M ) + + + +#ifndef CYGHWR_HAL_STM32_SPI3_REMAP +#define CYGHWR_HAL_STM32_SPI3_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 3, 6, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI3_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( B, 4, 6, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI3_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 5, 6, PUSHPULL, NONE, SPEED_SPI ) +#else +#define CYGHWR_HAL_STM32_SPI3_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 10, 6, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI3_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( C, 11, 6, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI3_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 12, 6, PUSHPULL, NONE, SPEED_SPI ) +#endif +#define CYGHWR_HAL_STM32_SPI3_REMAP_CONFIG 0 + +#define CYGHWR_HAL_STM32_SPI3_DMA_TX CYGHWR_HAL_STM32_DMA( 1, 2, 0, M2P ) +#define CYGHWR_HAL_STM32_SPI3_DMA_RX CYGHWR_HAL_STM32_DMA( 1, 0, 0, P2M ) + + +//============================================================================= +// GPIO pin and DMA definitions for each I2C bus + +#define CYGHWR_HAL_STM32_I2C1_SCL CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 6, 4, OPENDRAIN, PULLUP, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_I2C1_SDA CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 9, 4, OPENDRAIN, PULLUP, AT_LEAST(50) ) + +#define CYGHWR_HAL_STM32_I2C1_DMA_TX CYGHWR_HAL_STM32_DMA( 1, 7, 1, M2P ) +#define CYGHWR_HAL_STM32_I2C1_DMA_RX CYGHWR_HAL_STM32_DMA( 1, 5, 1, P2M ) + +#define CYGHWR_HAL_STM32_I2C2_SCL CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 10, 4, OPENDRAIN, PULLUP, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_I2C2_SDA CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 11, 4, OPENDRAIN, PULLUP, AT_LEAST(50) ) + +#define CYGHWR_HAL_STM32_I2C2_DMA_TX CYGHWR_HAL_STM32_DMA( 1, 7, 7, M2P ) +#define CYGHWR_HAL_STM32_I2C2_DMA_RX CYGHWR_HAL_STM32_DMA( 1, 3, 7, P2M ) + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_HAL_PLF_IO_H
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_JTAG.ecm @@ -0,0 +1,87 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + template redboot ; + + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value JTAG +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES { + user_value 0 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + user_value 0 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGDBG_HAL_CRCTABLE_LOCATION { + inferred_value ROM +};
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_RAM.ecm @@ -0,0 +1,83 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + template redboot ; + + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value RAM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES { + user_value 0 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + user_value 0 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +};
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM.ecm @@ -0,0 +1,87 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + template redboot ; + + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES { + user_value 0 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + user_value 0 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGDBG_HAL_CRCTABLE_LOCATION { + inferred_value ROM +};
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_flash.c @@ -0,0 +1,68 @@ +/*========================================================================== +// +// stm32x0g_eval_flash.c +// +// Cortex-M3 STM32X0G EVAL Flash setup +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jlarmour +// Date: 2011-12-12 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <cyg/io/flash_dev.h> + +//-------------------------------------------------------------------------- +// Internal flash + +#include <cyg/io/stm32_flash.h> + +CYG_FLASH_DRIVER(hal_stm32_flash, + &cyg_stm32_flash_funs, + 0, + 0x08000000, + 0, + 0, + 0, + &hal_stm32_flash_priv +); + +//-------------------------------------------------------------------------- +// EOF stm32x0g_eval_flash.c
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_misc.c @@ -0,0 +1,392 @@ +/*========================================================================== +// +// stm32x0g_eval_misc.c +// +// Cortex-M3/-M4 STM32X0G EVAL HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2011, 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jlarmour based on stm3210e by nickg +// Date: 2008-07-30 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_stm32.h> +#include <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include CYGHWR_MEMORY_LAYOUT_H // Memory regions + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header +#include <cyg/hal/hal_if.h> // HAL header + +//========================================================================== + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) +#if (CYGNUM_CALL_IF_TABLE_SIZE > 64) +// We force a compilation error for this fatal condition since run-time asserts +// may not be enabled for the build. +#error "The CALL_IF_TABLE_SIZE pre-allocation in the linker scripts for this platform need to be updated" +#endif +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + +//========================================================================== +// System init +// +// This is run to set up the basic system, including GPIO setting, +// clock feeds, power supply, and memory initialization. This code +// runs before the DATA is copied from ROM and the BSS cleared, hence +// it cannot make use of static variables or data tables. + +__externC void hal_system_init( void ) +{ + CYG_ADDRESS base; + + // Enable peripheral clocks in RCC + + base = CYGHWR_HAL_STM32_RCC; + + // All GPIO ports + // FIXME: this should be done in variant HAL at point of gpio_set + HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB1ENR, +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) // enable CCM clock + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_CCMDATARAMEN) | +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOA) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOB) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOC) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOD) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOE) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOF) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOG) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOH) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOI) ); + + // Enable FSMC + HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB3ENR, + BIT_(CYGHWR_HAL_STM32_RCC_AHB3ENR_FSMC) ); + +#if defined(CYG_HAL_STARTUP_ROM) | defined(CYG_HAL_STARTUP_ROMINT) | defined(CYG_HAL_STARTUP_SRAM) + + // Reset FSMC in case it was already enabled. This should set + // all regs back to default documented values, so we don't need + // to do any precautionary resets. + HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB3RSTR, + BIT_(CYGHWR_HAL_STM32_RCC_AHB3ENR_FSMC) ); + // Bring out of reset: + HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB3RSTR, 0 ); +#endif + + // Set all unused GPIO lines to input with pull down to prevent + // them floating and annoying any external hardware. + + // GPIO Ports C..I reset GPIOx_MODER to 0x00000000 + // GPIO Ports A..I reset GPIOx_OTYPER to 0x00000000 + // CPIO Ports A,C..I reset GPIOx_OSPEEDR to 0x00000000 + // GPIO Ports C..I reset GPIOx_PUPDR to 0x00000000 + + // GPIO Port A resets GPIOA_MODER to 0xA8000000 + // GPIO Port A resets GPIOA_PUPDR to 0x64000000 + // GPIO Port A keeps the default JTAG pins on PA13,14,15 + base = CYGHWR_HAL_STM32_GPIOA; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x02AAAAAA ); + + // GPIO Port B resets GPIOB_MODER to 0x00000280 + // GPIO Port B resets GPIOB_OSPEEDR to 0x000000C0 + // GPIO Port B resets GPIOB_PUPDR to 0x00000100 + // GPIO Port B keeps the default JTAG pins on PB3,4 + base = CYGHWR_HAL_STM32_GPIOB; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAAAAA82A ); + + // GPIO Port C - setup PC7 for LED4 as GPIO out, RS232 (USART4) on PC10,11. + // Rest stay default, with pulldowns on all except PC14,15 (OSC32) + // just in case that is important. + + base = CYGHWR_HAL_STM32_GPIOC; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0x00008800 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x0A0A2AAA ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00A04000 ); + + // GPIO Port D - setup FSMC for SRAM (PD0-1,3-15) and MicroSDcard (PD2) alternate functions + base = CYGHWR_HAL_STM32_GPIOD; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0xCCCCCCCC ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0xCCCCCCCC ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0xAAAAAAAA ); + // TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz + + // GPIO Port E - setup FSMC alternate function. PE0-1,3-4,7-15. + // But not PE5 (A21), PE6(A22), PE2(A23) which are not connected to SRAM. + base = CYGHWR_HAL_STM32_GPIOE; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0xC00CC0CC ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0xCCCCCCCC ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x00002820 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0xAAAA828A ); + // TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz + + // GPIO Port F - setup FSMC alternate function. PF0-5,12-15. + // But not PF6-11 which aren't connected to SRAM. + base = CYGHWR_HAL_STM32_GPIOF; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0x00CCCCCC ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0xCCCC0000 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x00AAA000 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0xAA000AAA ); + // TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz + + // GPIO Port G - setup FSMC alternate function. PG0-5,9,10. + // Other FSMC pins not connected to SRAM. + // LED1 is PG6, LED2 is PG8, so set as GPIO out. + base = CYGHWR_HAL_STM32_GPIOG; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0x00CCCCCC ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0x00000CC0 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAA808000 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00291AAA ); + // TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz + + // GPIO Port H stays default, with pulldowns on all except PH0,1 (OSC) just in case that is important. + base = CYGHWR_HAL_STM32_GPIOH; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAAAAAAA0 ); + + // GPIO Port I - setup PI9 for LED3 as GPIO out, rest stay default, with pulldowns + base = CYGHWR_HAL_STM32_GPIOI; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAAA2AAAA ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00040000 ); + + + // Set up FSMC NOR/SRAM bank 2 for SRAM + + base = CYGHWR_HAL_STM32_FSMC; + + +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) + // NOTEs: + // - The "STM32 20-21-45-46 G-EVAL" boards we have are populated with the + // IS61WV102416BLL-10MLI part and not the Cypress CY7C1071DV33 part. + // - The F4[01][57]xx devices can operate upto 168MHz (or 144MHz) so maximum HCLK + // timing of 6ns (or 6.94444ns). + // + // NOTE: The code does NOT set BWTR2 for SRAM write-cycle timing (so will be + // the default reset value of 0x0FFFFFFF) since BCRx:EXTMOD bit is NOT set. + + // TODO:IMPROVE: Derive values based on CLK settings. The following "fixed" + // values are based on a 168MHz SYSCLK: + + // BCR2 = MBKEN | MWID=0b01 (16bits) | WREN + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR2, 0x00001015 ); + + // BTR2: + // ADDSET=3 (3 HCLK cycles) + // ADDHLD=0 (SRAM:do not care) + // DATAST=6 (6 HCLK cycles) + // BUSTURN=1 (1 HCLK cycle) + // CLKDIV=0 (SRAM:do not care) + // DATLAT=0 (SRAM:do not care) + // ACCMOD=0 (access mode A) + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR2, 0x00010603 ); +#else // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2 + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR2, 0x00001011 ); + // SRAM timings for the fitted CY7C1071DV33-12BAXI async SRAM + // We could try and make this depend on hclk as it should, but that's + // probably overkill for now. With an hclk of 120MHz, each hclk period + // is 8.33ns, so we just use that. This might mean being slightly + // suboptimal at lower configured hclk speeds. + // It's tricky to get the waveforms in the STM32 FSMC docs and the SRAM + // datasheet, to match up, so there's a small amount of guess work involved + // here. From the SRAM datasheet, ADDSET should be at least 7ns (tHZWE), and + // DATAST should be at least 9ns (tPWE) plus one HCLK (from Fig 397 in FSMC + // docs showing Mode 1 write accesses). This gives ADDSET=1 and + // DATAST=3. + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR2, 0x00000301 ); +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2 + + // Enable flash prefetch buffer, cacheability and set latency to 2 wait states. + // Latency has to be set before clock is switched to a higher speed. + { + cyg_uint32 acr; + + base = CYGHWR_HAL_STM32_FLASH; + + HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr ); + acr |= CYGHWR_HAL_STM32_FLASH_ACR_PRFTEN; + acr |= CYGHWR_HAL_STM32_FLASH_ACR_DCEN|CYGHWR_HAL_STM32_FLASH_ACR_ICEN; + acr |= CYGHWR_HAL_STM32_FLASH_ACR_LATENCY(CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr ); + } +} + +//========================================================================== + +// Set LEDs 1-4 to lowest 4 bits of supplied char. +__externC void hal_stm32x0_led(char c) +{ + CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32X0G_LED1, 0 != (c&1) ); + CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32X0G_LED2, 0 != (c&2) ); + CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32X0G_LED3, 0 != (c&4) ); + CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32X0G_LED4, 0 != (c&8) ); +} + +//========================================================================== + +__externC void hal_platform_init( void ) +{ +#ifdef CYGDBG_USE_ASSERTS + __externC char __sram_data_start[]; +#endif + +#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + // Check the number of VSRs matches the linker script. We can do this + // because we intend the VV table to follow the VSR table with no gaps. + CYG_ASSERT( (char*)&hal_virtual_vector_table[0] - (char*)&hal_vsr_table >= CYGNUM_HAL_VSR_COUNT*4, + "VSR table size does not match" ); + // Now check the declared start of SRAM data follows the VV table end + CYG_ASSERT( (__sram_data_start - (char*)&hal_virtual_vector_table[0]) >= CYGNUM_CALL_IF_TABLE_SIZE*4, + "VV table size does not match sram space" ); +#else + // Check the VSR table fits below declared start of SRAM data + CYG_ASSERT( (__sram_data_start - (char*)&hal_vsr_table[0]) >= CYGNUM_HAL_VSR_COUNT*4, + "VSR table size does not match" ); +#endif + hal_stm32x0_led(1); +} + +//========================================================================== + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//-------------------------------------------------------------------------- +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. +// +// The following table defines the memory areas that GDB is allowed to +// touch. All others are disallowed. +// This table needs to be kept up to date with the set of memory areas +// that are available on the board. + +static struct +{ + CYG_ADDRESS start; // Region start address + CYG_ADDRESS end; // End address (last byte) +} hal_data_access[] = +{ + { CYGMEM_REGION_ram, CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1 }, // External SRAM +#ifdef CYGMEM_REGION_sram + { CYGMEM_REGION_sram, CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1 }, // On-chip SRAM +#endif +#ifdef CYGMEM_REGION_flash + { CYGMEM_REGION_flash, CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1 }, // On-chip flash +#endif + { 0xE0000000, 0x00000000-1 }, // Cortex-M peripherals + { 0x40000000, 0x60000000-1 }, // STM32 peripherals + { 0xA0000000, 0xA0001000-1 }, // FSMC control +#ifdef CYGMEM_REGION_ccm + { CYGMEM_REGION_ccm, CYGMEM_REGION_ccm+CYGMEM_REGION_ccm_SIZE-1 }, // On-chip (close-coupled) SRAM +#endif +}; + +__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ) +{ + int i; + for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) + { + if( (addr >= hal_data_access[i].start) && + (addr+count) <= hal_data_access[i].end) + return true; + } + return false; +} + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//========================================================================== + +#ifdef CYGPKG_REDBOOT +#include <redboot.h> +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Memory layout +// +// We report the on-chip SRAM and external SRAM. + + +void +cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end) +{ + switch (seg) { + case 0: + *start = (unsigned char *)CYGMEM_REGION_ram; + *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE); + break; +#ifdef CYGMEM_REGION_sram + case 1: + *start = (unsigned char *)CYGMEM_REGION_sram; + *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE); + break; +#elif defined(CYGMEM_REGION_xram) + case 1: + *start = (unsigned char *)CYGMEM_REGION_xram; + *end = (unsigned char *)(CYGMEM_REGION_xram + CYGMEM_REGION_xram_SIZE); + break; +#endif +#ifdef CYGMEM_REGION_ccm + case 2: + *start = (unsigned char *)CYGMEM_REGION_ccm; + *end = (unsigned char *)(CYGMEM_REGION_ccm + CYGMEM_REGION_ccm_SIZE); + break; +#endif + default: + *start = *end = NO_MEMORY; + break; + } +} // cyg_plf_memory_segment() + +#endif // CYGPKG_REDBOOT + + +//========================================================================== +// EOF stm32x0g_eval_misc.c