Mercurial > ecos
changeset 473:87f3e026b015
PPC60x improvements
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--- a/packages/hal/powerpc/arch/current/ChangeLog +++ b/packages/hal/powerpc/arch/current/ChangeLog @@ -1,3 +1,9 @@ +2002-12-24 Gary Thomas <gary@mlbassoc.com> + + * src/vectors.S: + * cdl/hal_powerpc.cdl: Add option to allow ROM code to simply + jump to the startup code, instead of using an absolute address. + 2002-11-14 Gary Thomas <gthomas@ecoscentric.com> * src/vectors.S: Provide pointer to saved registers on interrupt. @@ -13,6 +19,11 @@ 2002-08-05 Bob Koninckx <bob.koninckx@m * include/arch.inc: hal_fpu_load regs was not loading registers! +2002-08-01 Gary Thomas <gary@mlbassoc.com> + + * include/hal_io.h: + * include/hal_intr.h: Allow more variant/platform overrides. + 2002-04-29 Jonathan Larmour <jlarmour@redhat.com> * src/vectors.S:
--- a/packages/hal/powerpc/arch/current/cdl/hal_powerpc.cdl +++ b/packages/hal/powerpc/arch/current/cdl/hal_powerpc.cdl @@ -100,6 +100,12 @@ cdl_package CYGPKG_HAL_POWERPC { @rm target.tmp } + cdl_option CYGSEM_HAL_POWERPC_RESET_USES_JUMP { + display "RESET vector jumps to startup" + default_value 0 + description " + Some platforms may need this for ROMRAM startup." + } cdl_option CYGSEM_HAL_POWERPC_COPY_VECTORS { display "Copy exception vectors to RAM"
--- a/packages/hal/powerpc/arch/current/include/hal_intr.h +++ b/packages/hal/powerpc/arch/current/include/hal_intr.h @@ -12,6 +12,7 @@ // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -131,7 +132,9 @@ #define CYGNUM_HAL_EXCEPTION_FP_ASSIST CYGNUM_HAL_VECTOR_FP_ASSIST #define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_RESERVED_0 -#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VECTOR_FP_ASSIST +#ifndef CYGNUM_HAL_EXCEPTION_MAX +#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VSR_MAX +#endif #define CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED @@ -401,8 +404,10 @@ externC void cyg_hal_default_exception_v CYG_MACRO_END #endif +#ifndef HAL_DELAY_US extern void hal_delay_us(int); #define HAL_DELAY_US(n) hal_delay_us(n) +#endif // The vector used by the Real time clock #ifndef CYGNUM_HAL_INTERRUPT_RTC
--- a/packages/hal/powerpc/arch/current/include/hal_io.h +++ b/packages/hal/powerpc/arch/current/include/hal_io.h @@ -12,6 +12,7 @@ // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -60,6 +61,9 @@ //============================================================================= #include <cyg/infra/cyg_type.h> +#ifdef CYGBLD_HAL_PLF_IO_H +#include CYGBLD_HAL_PLF_IO_H +#endif //----------------------------------------------------------------------------- // Enforce in-order IO for all HAL reads/writes using this macro.
--- a/packages/hal/powerpc/arch/current/src/vectors.S +++ b/packages/hal/powerpc/arch/current/src/vectors.S @@ -190,9 +190,14 @@ .p2align 8 .globl __exception_\name __exception_\name: +#ifdef CYGSEM_HAL_POWERPC_RESET_USES_JUMP + bl _start +#else lwi r3,_start mtlr r3 blr +#endif + .endm # Generic vector macro @@ -310,7 +315,7 @@ 0: lwzu r0,4(r3) # Set up exception handlers and VSR table, taking care not to # step on any ROM monitor''s toes. - hal_mon_init + hal_mon_init #if defined(CYG_HAL_STARTUP_ROM)
--- a/packages/hal/powerpc/ppc60x/current/ChangeLog +++ b/packages/hal/powerpc/ppc60x/current/ChangeLog @@ -1,3 +1,20 @@ +2002-08-01 Gary Thomas <gary@mlbassoc.com> + + * src/var_misc.c (cyg_hal_map_memory): Need to set protection bits. + + * include/variant.inc: Additional exceptions. Also allow for + more platform specifics (like INTC lookup macro). + + * include/var_regs.h: Allow for platform registers <cyg/hal/plf_regs.h> + Also, flush out HID0 register (used by cache control). + + * include/var_intr.h: Add PPC60x additional exceptions. + + * include/var_cache.h: Initial cache support. + + * cdl/hal_powerpc_ppc60x.cdl: Support various ROM monitor options, + matching other variants. + 2000-06-13 Jesper Skov <jskov@redhat.com> * cdl/hal_powerpc_ppc60x.cdl: Add vector table location definition.
--- a/packages/hal/powerpc/ppc60x/current/cdl/hal_powerpc_ppc60x.cdl +++ b/packages/hal/powerpc/ppc60x/current/cdl/hal_powerpc_ppc60x.cdl @@ -9,6 +9,7 @@ ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2002 Gary Thomas ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -59,6 +60,28 @@ cdl_package CYGPKG_HAL_POWERPC_PPC60x { for this processor variant. It is also necessary to select a specific target platform HAL package." + cdl_interface CYGINT_HAL_USE_ROM_MONITOR_UNSUPPORTED { + display "ROM monitor configuration is unsupported" + no_define + } + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor bool + default_value { (CYG_HAL_STARTUP == "RAM" && + !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS && + !CYGINT_HAL_USE_ROM_MONITOR_UNSUPPORTED && + !CYGSEM_HAL_POWERPC_COPY_VECTORS) ? 1 : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + requires ! CYGSEM_HAL_POWERPC_COPY_VECTORS + requires ! CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires ! CYGINT_HAL_USE_ROM_MONITOR_UNSUPPORTED + description " + Allow coexistence with ROM monitor (CygMon or GDB stubs) by + only initializing interrupt vectors on startup, thus leaving + exception handling to the ROM monitor." + } + # Note: This should be sub-variant specific to reduce memory use. define_proc { puts $cdl_header "#define CYGHWR_HAL_VSR_TABLE (CYGHWR_HAL_POWERPC_VECTOR_BASE + 0x3000)"
--- a/packages/hal/powerpc/ppc60x/current/include/var_cache.h +++ b/packages/hal/powerpc/ppc60x/current/include/var_cache.h @@ -11,6 +11,7 @@ // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -43,7 +44,7 @@ //#####DESCRIPTIONBEGIN#### // // Author(s): nickg -// Contributors:nickg, jskov +// Contributors:nickg, jskov, gthomas // Date: 2000-04-02 // Purpose: Variant cache control API // Description: The macros defined here provide the HAL APIs for handling @@ -60,7 +61,6 @@ #include <cyg/infra/cyg_type.h> #include <cyg/hal/ppc_regs.h> - #include <cyg/hal/plf_cache.h> @@ -68,14 +68,18 @@ // Cache dimensions // Data cache -#define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes -#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line -#define HAL_DCACHE_WAYS 2 // Associativity of the cache +#ifndef HAL_DCACHE_SIZE +#define HAL_DCACHE_SIZE 16384 // Size of data cache in bytes +#define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line +#define HAL_DCACHE_WAYS 4 // Associativity of the cache +#endif // Instruction cache -#define HAL_ICACHE_SIZE 4096 // Size of cache in bytes -#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line -#define HAL_ICACHE_WAYS 2 // Associativity of the cache +#ifndef HAL_ICACHE_SIZE +#define HAL_ICACHE_SIZE 16384 // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line +#define HAL_ICACHE_WAYS 4 // Associativity of the cache +#endif #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) @@ -84,13 +88,49 @@ // Global control of data cache // Enable the data cache -#define HAL_DCACHE_ENABLE() +#define HAL_DCACHE_ENABLE() \ + CYG_MACRO_START \ + cyg_int32 _scratch; \ + asm volatile ("isync;" \ + "mfspr %0,%1;" \ + "or %0,%0,%2;" \ + "mtspr %1,%0" \ + : "=&r" (_scratch) \ + : "I" (CYGARC_REG_HID0), \ + "r" (_HID0_DCE) \ + ); \ + CYG_MACRO_END // Disable the data cache -#define HAL_DCACHE_DISABLE() +#define HAL_DCACHE_DISABLE() \ + CYG_MACRO_START \ + cyg_int32 _scratch; \ + asm volatile ("isync;" \ + "mfspr %0,%1;" \ + "andc %0,%0,%2;" \ + "mtspr %1,%0" \ + : "=&r" (_scratch) \ + : "I" (CYGARC_REG_HID0), \ + "r" (_HID0_DCE) \ + ); \ + CYG_MACRO_END // Invalidate the entire cache -#define HAL_DCACHE_INVALIDATE_ALL() +#define HAL_DCACHE_INVALIDATE_ALL() \ + CYG_MACRO_START \ + cyg_int32 _scr1, _scr2; \ + asm volatile ("isync;" \ + "mfspr %0,%2;" \ + "mr %1,%0;" \ + "or %0,%0,%3;" \ + "mtspr %2,%0;" \ + "mtspr %2,%1" \ + : "=&r" (_scr1), \ + "=&r" (_scr2) \ + : "I" (CYGARC_REG_HID0), \ + "r" (_HID0_DCFI) \ + ); \ + CYG_MACRO_END // Synchronize the contents of the cache with memory. #define HAL_DCACHE_SYNC() @@ -98,7 +138,15 @@ // Query the state of the data cache #define HAL_DCACHE_IS_ENABLED(_state_) \ CYG_MACRO_START \ - (_state_) = 0; \ + cyg_int32 _scratch; \ + asm volatile ("isync;" \ + "mfspr %0,%1;" \ + "and %0,%0,%2;" \ + : "=&r" (_scratch) \ + : "I" (CYGARC_REG_HID0), \ + "r" (_HID0_DCE) \ + ); \ + (_state_) = _scratch != 0; \ CYG_MACRO_END // Set the data cache refill burst size @@ -129,44 +177,143 @@ // Write dirty cache lines to memory and invalidate the cache entries // for the given address range. -//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) - +#define HAL_DCACHE_FLUSH( _base_ , _size_ ) \ + CYG_MACRO_START \ + cyg_uint32 __base = (cyg_uint32) (_base_); \ + cyg_int32 __size = (cyg_int32) (_size_); \ + while (__size > 0) { \ + asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \ + __base += HAL_DCACHE_LINE_SIZE; \ + __size -= HAL_DCACHE_LINE_SIZE; \ + } \ + CYG_MACRO_END + // Invalidate cache lines in the given range without writing to memory. -//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) +#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \ + CYG_MACRO_START \ + cyg_uint32 __base = (cyg_uint32) (_base_); \ + cyg_int32 __size = (cyg_int32) (_size_); \ + while (__size > 0) { \ + asm volatile ("dcbi 0,%0;sync;" : : "r" (__base)); \ + __base += HAL_DCACHE_LINE_SIZE; \ + __size -= HAL_DCACHE_LINE_SIZE; \ + } \ + CYG_MACRO_END // Write dirty cache lines to memory for the given address range. -//#define HAL_DCACHE_STORE( _base_ , _size_ ) +#define HAL_DCACHE_STORE( _base_ , _size_ ) \ + CYG_MACRO_START \ + cyg_uint32 __base = (cyg_uint32) (_base_); \ + cyg_int32 __size = (cyg_int32) (_size_); \ + while (__size > 0) { \ + asm volatile ("dcbst 0,%0;sync;" : : "r" (__base)); \ + __base += HAL_DCACHE_LINE_SIZE; \ + __size -= HAL_DCACHE_LINE_SIZE; \ + } \ + CYG_MACRO_END // Preread the given range into the cache with the intention of reading // from it later. -//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) +#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) \ + CYG_MACRO_START \ + cyg_uint32 __base = (cyg_uint32) (_base_); \ + cyg_int32 __size = (cyg_int32) (_size_); \ + while (__size > 0) { \ + asm volatile ("dcbt 0,%0;" : : "r" (__base)); \ + __base += HAL_DCACHE_LINE_SIZE; \ + __size -= HAL_DCACHE_LINE_SIZE; \ + } \ + CYG_MACRO_END // Preread the given range into the cache with the intention of writing // to it later. -//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) +#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) \ + CYG_MACRO_START \ + cyg_uint32 __base = (cyg_uint32) (_base_); \ + cyg_int32 __size = (cyg_int32) (_size_); \ + while (__size > 0) { \ + asm volatile ("dcbtst 0,%0;" : : "r" (__base)); \ + __base += HAL_DCACHE_LINE_SIZE; \ + __size -= HAL_DCACHE_LINE_SIZE; \ + } \ + CYG_MACRO_END // Allocate and zero the cache lines associated with the given range. -//#define HAL_DCACHE_ZERO( _base_ , _size_ ) +#define HAL_DCACHE_ZERO( _base_ , _size_ ) \ + CYG_MACRO_START \ + cyg_uint32 __base = (cyg_uint32) (_base_); \ + cyg_int32 __size = (cyg_int32) (_size_); \ + while (__size > 0) { \ + asm volatile ("dcbz 0,%0;" : : "r" (__base)); \ + __base += HAL_DCACHE_LINE_SIZE; \ + __size -= HAL_DCACHE_LINE_SIZE; \ + } \ + CYG_MACRO_END //----------------------------------------------------------------------------- // Global control of Instruction cache // Enable the instruction cache -#define HAL_ICACHE_ENABLE() +#define HAL_ICACHE_ENABLE() \ + CYG_MACRO_START \ + cyg_int32 _scratch; \ + asm volatile ("isync;" \ + "mfspr %0,%1;" \ + "or %0,%0,%2;" \ + "mtspr %1,%0" \ + : "=&r" (_scratch) \ + : "I" (CYGARC_REG_HID0), \ + "r" (_HID0_ICE) \ + ); \ + CYG_MACRO_END // Disable the instruction cache -#define HAL_ICACHE_DISABLE() +#define HAL_ICACHE_DISABLE() \ + CYG_MACRO_START \ + cyg_int32 _scratch; \ + asm volatile ("isync;" \ + "mfspr %0,%1;" \ + "andc %0,%0,%2;" \ + "mtspr %1,%0" \ + : "=&r" (_scratch) \ + : "I" (CYGARC_REG_HID0), \ + "r" (_HID0_ICE) \ + ); \ + CYG_MACRO_END // Invalidate the entire cache -#define HAL_ICACHE_INVALIDATE_ALL() +#define HAL_ICACHE_INVALIDATE_ALL() \ + CYG_MACRO_START \ + cyg_int32 _scr1, _scr2; \ + asm volatile ("isync;" \ + "mfspr %0,%2;" \ + "mr %1,%0;" \ + "or %0,%0,%3;" \ + "mtspr %2,%0;" \ + "mtspr %2,%1" \ + : "=&r" (_scr1), \ + "=&r" (_scr2) \ + : "I" (CYGARC_REG_HID0), \ + "r" (_HID0_ICFI) \ + ); \ + CYG_MACRO_END // Synchronize the contents of the cache with memory. -#define HAL_ICACHE_SYNC() +#define HAL_ICACHE_SYNC() \ + HAL_ICACHE_INVALIDATE_ALL() // Query the state of the instruction cache #define HAL_ICACHE_IS_ENABLED(_state_) \ CYG_MACRO_START \ - (_state_) = 0; \ + cyg_int32 _scratch; \ + asm volatile ("isync;" \ + "mfspr %0,%1;" \ + "and %0,%0,%2;" \ + : "=&r" (_scratch) \ + : "I" (CYGARC_REG_HID0), \ + "r" (_HID0_ICE) \ + ); \ + (_state_) = _scratch != 0; \ CYG_MACRO_END // Set the instruction cache refill burst size
--- a/packages/hal/powerpc/ppc60x/current/include/var_intr.h +++ b/packages/hal/powerpc/ppc60x/current/include/var_intr.h @@ -11,6 +11,7 @@ // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -43,7 +44,7 @@ //#####DESCRIPTIONBEGIN#### // // Author(s): nickg -// Contributors:nickg, jskov, jlarmour, hmt +// Contributors:nickg, jskov, jlarmour, hmt, gthomas // Date: 2000-04-02 // Purpose: Variant interrupt support // Description: The macros defined here provide the HAL APIs for handling @@ -56,8 +57,18 @@ // //============================================================================= +// Additional trap/exceptions on PPC60x +#define CYGNUM_HAL_VECTOR_ITLB_MISS 0x10 +#define CYGNUM_HAL_VECTOR_DTLB_LOAD_MISS 0x11 +#define CYGNUM_HAL_VECTOR_DTLB_STORE_MISS 0x12 +#define CYGNUM_HAL_VECTOR_SMI 0x13 + +#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_SMI + // No builtin interrupt controller in the PPC60x CPUs. +#include <cyg/hal/plf_intr.h> // Maybe something on the platform though + //----------------------------------------------------------------------------- #endif // ifndef CYGONCE_VAR_INTR_H // End of var_intr.h
--- a/packages/hal/powerpc/ppc60x/current/include/var_regs.h +++ b/packages/hal/powerpc/ppc60x/current/include/var_regs.h @@ -59,13 +59,33 @@ // //========================================================================== +#include <cyg/hal/plf_regs.h> // Get any platform specifics + //-------------------------------------------------------------------------- // Cache #define CYGARC_REG_HID0 1008 - -#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS -#define HID0 CYGARC_REG_HID0 -#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#define _HID0 CYGARC_REG_HID0 +#define _HID0_EMCP 0x80000000 // Enable machine check +#define _HID0_EBA 0x20000000 // Enable bus address parity +#define _HID0_EBD 0x10000000 // Enable bus data parity +#define _HID0_BCLK 0x08000000 +#define _HID0_EICE 0x04000000 +#define _HID0_ECLK 0x02000000 +#define _HID0_PAR 0x01000000 +#define _HID0_DOZE 0x00800000 +#define _HID0_NAP 0x00400000 +#define _HID0_SLEEP 0x00200000 +#define _HID0_DPM 0x00100000 +#define _HID0_ICE 0x00008000 // Enable Instruction Cache +#define _HID0_DCE 0x00004000 // Enable Data Cache +#define _HID0_ILOCK 0x00002000 // Instruction Cache Lock +#define _HID0_DLOCK 0x00001000 // Data Cache Lock +#define _HID0_ICFI 0x00000800 // Instruction Cache [flash] Invalidate +#define _HID0_DCFI 0x00000400 // Data Cache [flash] Invalidate +#define _HID0_IFEM 0x00000080 +#define _HID0_FBIOB 0x00000010 +#define _HID0_ABE 0x00000008 +#define _HID0_NOOPT 0x00000001 //-------------------------------------------------------------------------- // BATs
--- a/packages/hal/powerpc/ppc60x/current/include/variant.inc +++ b/packages/hal/powerpc/ppc60x/current/include/variant.inc @@ -11,6 +11,7 @@ ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2002 Gary Thomas ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -43,9 +44,9 @@ #######DESCRIPTIONBEGIN#### ## ## Author(s): jskov -## Contributors:jskov +## Contributors:jskov, gthomas ## Date: 2000-02-04 -## Purpose: MPC8xx family definitions. +## Purpose: PPC60x family definitions. ## Description: This file contains various definitions and macros that are ## useful for writing assembly code for the PPC60x CPU family. ## Usage: @@ -60,11 +61,17 @@ #include <pkgconf/hal.h> #include <cyg/hal/arch.inc> +#include <cyg/hal/platform.inc> ##----------------------------------------------------------------------------- ## PPC60x defined vectors .macro hal_extra_vectors + exception_vector instruction_TLB + exception_vector data_load_TLB + exception_vector data_store_TLB + exception_vector instruction_address_breakpoint + exception_vector system_management_interrupt .endm ##-----------------------------------------------------------------------------
--- a/packages/hal/powerpc/ppc60x/current/src/var_misc.c +++ b/packages/hal/powerpc/ppc60x/current/src/var_misc.c @@ -9,6 +9,7 @@ // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -87,7 +88,7 @@ cyg_hal_map_memory (int id,CYG_ADDRESS v cyg_uint32 ubat, lbat; ubat = (virt & UBAT_BEPIMASK) | UBAT_VS | UBAT_VP; - lbat = (phys & LBAT_BRPNMASK); + lbat = (phys & LBAT_BRPNMASK) | LBAT_PP_RW; if (flags & CYGARC_MEMDESC_CI) lbat |= LBAT_I; if (flags & CYGARC_MEMDESC_GUARDED)