Mercurial > ecos
changeset 3122:ac6418ab8bfa
New package -- Actel SmartFusion Cortex-M3 variant HAL. [Bugzilla 1001291]
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new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/var/current/ChangeLog @@ -0,0 +1,42 @@ +2011-06-26 Christophe Coutand <ecos@hotmail.co.uk> + + * cdl/hal_cortexm_a2fxxx.cdl: + * cdl/hal_cortexm_a2fxxx_irq.cdl: + * include/hal_cache.h: + * include/hal_diag.h: + * include/plf_stub.h: + * include/var_arch.h: + * include/variant.inc: + * include/var_intr.h: + * include/var_io.h: + * src/hal_diag.c: + * src/hal_dma.c: + * src/a2fxxx_misc.c: + * tests/timers.c: + New package -- Actel SmartFusion Cortex-M3 variant HAL. + [Bugzilla 1001291] + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/var/current/cdl/hal_cortexm_a2fxxx.cdl @@ -0,0 +1,732 @@ +##========================================================================== +## +## hal_cortexm_a2f.cdl +## +## Cortex-M A2F variant HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): ccoutand +## Contributors: +## Date: 2011-02-03 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_A2FXXX { + display "Actel Smartfusion A2Fxxx Variant (Cortex-M3)" + parent CYGPKG_HAL_CORTEXM + hardware + include_dir cyg/hal + define_header hal_cortexm_a2fxxx.h + description " + This package provides generic support for the Actel Smarfusiom Cortex-M3 + based microcontroller family. It is also necessary to select a platform + HAL package." + + compile hal_diag.c a2fxxx_misc.c hal_dma.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT + + requires { CYGHWR_HAL_CORTEXM == "M3" } + requires { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX { + display "Actel Smartfusion A2F variant in use" + flavor data + default_value { "A2F200" } + legal_values { "A2F060" "A2F200" "A2F500" } + description "The Smartfusion has several variants, the main differences + being in the size of on-chip FLASH and SRAM and numbers of + some analog peripherals. This option allows the platform HAL + to select the specific microcontroller fitted." + } + + cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS { + display "CPU priority levels" + flavor data + calculated 5 + description "This option defines the number of bits used to + encode the exception priority levels that this + variant of the Cortex-M CPU implements." + } + + cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK { + display "Clocking" + description "Select this option to configure the internal + clock network of the device. Due to large amount of possible combination of + clock configuration, it is recommended to use the Actel MSS configuration tool + and let the system boot handle the clock settings. Some of the requirement for + setting the clock network of the device are : The On-chip Oscillator + clock frequency is fixed to 100 MHz and cannot be changed. The Main Crystal + Oscillator clock frequency must be between 1.5 MHz and 20 MHz when the PLL is + used or between 32 KHz and 20 MHz when the PLL is bypassed. The Main Crystal + Oscillator (RC network configuration) clock frequency must be between 1.5MHz + and 4 MHz when the PLL is used or between 32 KHz and 4 MHz when the PLL is + bypassed. For all other sources, the source clock frequency must be between + 1.5 MHz and 176MHz when the PLL is used or between 32 KHz and 250 MHz when the + PLL is bypassed." + flavor bool + default_value 0 + + cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKIN { + display "Input clock selection" + flavor none + description "Configure the input clocks of the device." + + cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKA { + display "Clock A configuration" + flavor bool + default_value { CYGHWR_HAL_CORTEXM_A2FXXX_PLL } + description "Configure the clock A input of the device." + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC { + display "Clock A source" + flavor data + legal_values { "AUIN" "AUIP" "ADIP" "GLAINT" "RCOSC" "MOSC" } + default_value { "RCOSC" } + description " + Select the clock A source. Valid choices are the main oscillator, + the RC oscillator, the FPGA fabric or the dedicated single-ended or + differential IOs." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_FREQ { + display "Clock A frequency in Hz" + flavor data + legal_values { 1500000 to 176000000 } + default_value { CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC == "RCOSC" ? 100000000 : 20000000 } + description " + Select the clock A source frequency in Hz. Additional restrictions + of the frequency range apply giving the clock source. It is left to + the user to take care of not exceeding the limits provided by the + device user manual." + } + } + + cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKB { + display "Clock B configuration" + flavor bool + description "Configure the clock B input of the device." + default_value 0 + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC { + display "Clock B source" + flavor data + legal_values { "BUIN" "BUIP" "BDIP" "GLBINT" "RCOSC" "MOSC" } + default_value { "MOSC" } + description " + Select the clock B source. Valid choices are the main oscillator, + the RC oscillator, the FPGA fabric or the dedicated single-ended or + differential IOs." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_FREQ { + display "Clock B frequency in Hz" + flavor data + legal_values { 32000 to 350000000 } + default_value { CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC == "RCOSC" ? 100000000 : 20000000 } + description " + Select the clock B source frequency in Hz. Additional restrictions + of the frequency range apply giving the clock source. It is left to + the user to take care of not exceeding the limits provided by the + device user manual." + } + } + + cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKC { + display "Clock C configuration" + flavor bool + description "Configure the clock C input of the device." + default_value 0 + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC { + display "Clock C source" + flavor data + legal_values { "CUIN" "CUIP" "CDIP" "GLCINT" "RCOSC" "32KOSC"} + default_value { "RCOSC" } + description " + Select the clock C source. Valid choices are the main oscillator, + the RC oscillator, the FPGA fabric or the dedicated single-ended or + differential IOs." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_FREQ { + display "Clock C frequency in Hz" + flavor data + legal_values { 32000 to 350000000 } + default_value { CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC == "RCOSC" ? 100000000 : 20000000 } + description " + Select the clock B source frequency in Hz. Additional restrictions + of the frequency range apply giving the clock source. It is left to + the user to take care of not exceeding the limits provided by the + device user manual." + } + } + } + + cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_PLL { + display "PLL configuration" + flavor bool + requires CYGHWR_HAL_CORTEXM_A2FXXX_CLKA + description "Configure the device PLL." + default_value 1 + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PLL_MULT { + display "PLL Multiplier" + flavor data + legal_values { 1 to 128 } + default_value { 1 } + description " + Select the PLL multiplier coefficient (m)." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PLL_DIV { + display "PLL Divider" + flavor data + legal_values { 1 to 128 } + default_value { 1 } + description " + Select the PLL divider coefficient (n)." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ { + display "PLL output frequency" + flavor data + calculated { CYGHWR_HAL_CORTEXM_A2FXXX_PLL ? ( CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_FREQ * CYGHWR_HAL_CORTEXM_A2FXXX_PLL_MULT ) / CYGHWR_HAL_CORTEXM_A2FXXX_PLL_DIV : 0 } + legal_values { 22000000 to 350000000 } + description " + Computed PLL output frequency." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FB_DELAY { + display "PLL Feedback delay" + flavor data + legal_values { 0 to 15 } + default_value { 0 } + description " + Select the PLL Feedback loop delay. Field FBDLY from user manual. + Value from 535 to 5560ns." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PLL_XDELAY { + display "PLL Additional delay" + flavor bool + default_value 0 + description " + Add 2ns additional delay on PLL feedback loop." + } + } + + cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKOUT { + display "Global clock output configuration" + flavor none + description "Configure the Global clocks of the device." + + cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA { + display "Global clock A configuration" + flavor bool + default_value { CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT == "CLKGA" } + description "Configure the Global clock A of the device." + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC { + display "Global clock A source" + flavor data + legal_values { "CLKA" "PLL_VCO0" "PLL_VCO90" "PLL_VCO180" "PLL_VCO270" "PLL_VCO0_DL" } + default_value { "PLL_VCO0" } + requires { CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "CLKA" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKA : CYGHWR_HAL_CORTEXM_A2FXXX_PLL } + description " + Select the Global clock A source. Valid choices are the PLL output (with different phases) + or the clock A input." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV { + display "Global clock A divider" + flavor data + legal_values { 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 + 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 30 31 32 } + default_value { 1 } + description " + Select the Global clock A divider value." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV10 { + display "Global clock A divider * 10" + flavor data + calculated { CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV * 10 } + description " + Computed Global clock A divider value multiplied by 10." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DELAY { + display "Global clock A delay line" + flavor data + legal_values { 0 to 15 } + default_value { 0 } + description " + Select the Global clock A delay value." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_FREQ { + display "Global clock A Frequency" + flavor data + legal_values { 1 to 100000000 } + calculated { ( CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "PLL_VCO0" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "PLL_VCO90" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "PLL_VCO180" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "PLL_VCO270" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "PLL_VCO0_DL" ) ? ( ( CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ * 10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV10 ) : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "CLKA" ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_FREQ * 10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV10 ) : 0 } + description " + Computed Global clock A frequency." + } + } + + cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB { + display "Global clock B configuration" + flavor bool + description "Configure the Global clock B of the device." + default_value { CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK && CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO != 1 } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC { + display "Global clock B source" + flavor data + legal_values { "CLKB" "CLKGA" "PLL_VCO0" "PLL_VCO90" "PLL_VCO180" "PLL_VCO270" "PLL_VCO0_DL" } + default_value { "PLL_VCO0" } + requires { CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "CLKB" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKB : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "CLKGA" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA : CYGHWR_HAL_CORTEXM_A2FXXX_PLL } + description " + Select the Global clock B source. Valid choices are the PLL output (with different phases), + the clock B input or the global clock A output." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV { + display "Global clock B divider" + flavor data + legal_values { 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 + 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 30 31 32 } + default_value { 1 } + description " + Select the Global clock B divider value." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV10 { + display "Global clock B divider * 10" + flavor data + calculated { CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV * 10 } + description " + Computed Global clock B divider value multiplied by 10." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DELAY { + display "Global clock B delay line" + flavor data + legal_values { 0 to 15 } + default_value { 0 } + description " + Select the Global clock B delay value." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_FREQ { + display "Global clock B Frequency" + flavor data + calculated { ( CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "PLL_VCO0" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "PLL_VCO90" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "PLL_VCO180" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "PLL_VCO270" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "PLL_VCO0_DL" ) ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ*10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV10 ) : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "CLKB" ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_FREQ * 10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV10 ) : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "CLKGA" ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_FREQ * 10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV10 ) : 0 } + description " + Computed Global clock B frequency." + } + } + + cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC { + display "Global clock C configuration" + flavor bool + description "Configure the Global clock C of the device." + default_value { CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT == "CLKGC" } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC { + display "Global clock C source" + flavor data + legal_values { "CLKC" "CLKGA" "PLL_VCO0" "PLL_VCO90" "PLL_VCO180" "PLL_VCO270" "PLL_VCO0_DL" } + default_value { "PLL_VCO0" } + requires { CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "CLKC" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKC : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "CLKGA" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA : CYGHWR_HAL_CORTEXM_A2FXXX_PLL } + description " + Select the Global clock C source. Valid choices are the PLL output (with different phases), + the clock C input or the global clock A output." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV { + display "Global clock C divider" + flavor data + legal_values { 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 + 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 30 31 32 } + default_value { 1 } + description " + Select the Global clock C divider value." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV10 { + display "Global clock C divider * 10" + flavor data + calculated { CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV * 10 } + description " + Computed Global clock C divider value multiplied by 10." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DELAY { + display "Global clock C delay line" + flavor data + legal_values { 0 to 15 } + default_value { 0 } + description " + Select the Global clock C delay value." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_FREQ { + display "Global clock C Frequency" + flavor data + calculated { ( CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "PLL_VCO0" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "PLL_VCO90" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "PLL_VCO180" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "PLL_VCO270" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "PLL_VCO0_DL" ) ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ*10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV10 ) : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "CLKC" ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_FREQ * 10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV10 ) : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "CLKGA" ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_FREQ * 10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV10 ) : 0 } + description " + Computed Global clock C frequency." + } + } + + cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_MSS_FPGA { + display "MSS / FPGA Clock configuration" + flavor none + description "Configure the MSS and Fabric master clock." + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT { + display "NGMUX output clock" + flavor data + legal_values { "CLKGA" "CLKGC" } + default_value { "CLKGA" } + requires { CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT == "CLKGA" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA : ( CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC && CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC != "CLKGA" ) } + description " + Select the NGMUX output clock. Valid choices are the Global Clock A or C." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ { + display "NGMUX output clock frequency" + flavor data + legal_values { 1 to 100000000 } + calculated { CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT == "CLKGA" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_FREQ : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_FREQ } + description " + Computed NGMUX output clock frequency." + } + + cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK { + display "Fabric clock configuration" + flavor bool + default_value 0 + description "Set the Fabric master clock. The Fabric frequency ration + specifies which clock source to be used. For a ration of 1, the fabric + and MSS clock source are the same. For a ration of 2 of 4, the fabric + clock source is CLKGB and the ration between CLKGB and the MSS clock must + be configured by the user to be equal to 2 or 4." + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO { + display "Fabric to MSS clock ratio" + flavor data + legal_values { 1 2 4 } + requires { CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO != 1 ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB : 1 } + requires { CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO != 1 ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_FREQ == CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ / CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO : 1 } + default_value { 1 } + description " + Select the Fabric to MSS clock ratio." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_FREQ { + display "Fabric clock Frequency" + flavor data + calculated { ( CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK && CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO != 1 ) ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_FREQ : ( CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK && CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO == 1 ) ? CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ : 0 } + description " + Computed Fabric clock frequency." + } + } + + cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_MSS_CLK { + display "MSS clock configuration" + flavor none + description "Configure the MSS master clock." + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_MSS_CLK_DELAY { + display "MSS clock delay" + flavor data + legal_values { 0 to 15 } + default_value { 0 } + description " + Select the MSS clock delay. Field FBDLY. Value from 535 to 5560ns." + } + + cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_ACE_CLK { + display "ACE clock configuration" + flavor bool + default_value 0 + description "Configure the ACE master clock." + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_ACLK_DIV { + display "ACE clock divider" + flavor data + legal_values { 1 2 4 } + default_value { 1 } + description " + Select the ACE clock divider value." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_ACLK_FREQ { + display "ACE clock Frequency" + flavor data + calculated { CYGHWR_HAL_CORTEXM_A2FXXX_ACE_CLK ? CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ / CYGHWR_HAL_CORTEXM_A2FXXX_ACLK_DIV : 0 } + description " + Computed ACE clock frequency." + } + } + + cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_CLK { + display "PCLK0 clock configuration" + flavor none + description "Configure the PCLK0 clock." + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_DIV { + display "PCLK0 clock divider" + flavor data + legal_values { 1 2 4 } + default_value { 1 } + description " + Select PCLK0 clock divider value." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_FREQ { + display "PCLK0 clock Frequency" + flavor data + calculated { CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ ? CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ / CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_DIV : 0 } + description " + Computed PCLK0 clock frequency." + } + } + + cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_CLK { + display "PCLK1 clock configuration" + flavor none + description "Configure the PCLK1 clock." + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_DIV { + display "PCLK1 clock divider" + flavor data + legal_values { 1 2 4 } + default_value { 1 } + description " + Select PCLK1 clock divider value." + } + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_FREQ { + display "PCLK1 clock Frequency" + flavor data + calculated { CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ ? CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ / CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_DIV : 0 } + description " + Computed PCLK1 clock frequency." + } + } + } + } + + cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_MAC_CLK { + display "Ethernet MAC clock configuration" + flavor bool + default_value 0 + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_MAC_SRC { + display "Ethernet MAC clock source" + flavor data + legal_values { "CLKGC" "EXTERNAL" } + default_value { "CLKGC" } + requires { CYGHWR_HAL_CORTEXM_A2FXXX_MAC_SRC == "CLKGC" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC : 1 } + description " + Select the Ethernet MAC clock source." + } + } + } + } + + cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_DMA { + display "DMA" + flavor none + description " + DMA controller configuration." + + cdl_option CYGDBG_HAL_CORTEXM_A2FXXX_DMA_TRACE { + display "Display status messages during DMA operations" + flavor bool + default_value 0 + description " + Selecting this option will cause the DMA driver to print status + messages as various DMA operations are undertaken." + } + } + + cdl_option CYGSEM_HAL_CORTEXM_A2FXXX_CLOCK_CHATTER { + display "Trace clock network configuration." + default_value 1 + flavor bool + description " + Enable debug tracing of the clock configuration." + } + + cdl_option CYGSEM_HAL_CORTEXM_A2FXXX_DEFINES_IDLE_THREAD_ACTION { + display "Override IDLE thread action" + default_value 1 + flavor bool + description " + Override IDLE thread action defined by the architectural HAL. + The option must be active when running the application from a + debugger. The 'WFI' IDLE instruction defined in the architectural + HAL leads to software crash when application runs from a debugger." + } + + cdl_component CYGPKG_HAL_CORTEXM_A2FXXX_IO { + display "IO configuration" + flavor bool + default_value 0 + description " + Overwrite the default IO configuration + " + + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_IO_WEST_BANK { + display "IO west bank buffer type" + legal_values { "LVCMOS_3V3" "LVCMOS_2V5" "LVCMOS_1V8" "LVCMOS_1V5" } + default_value { "LVCMOS_3V3" } + flavor data + description " + Select the device west bank IO buffer type to be used. + " + } + cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_IO_EAST_BANK { + display "IO east bank buffer type" + legal_values { "LVCMOS_3V3" "LVCMOS_2V5" "LVCMOS_1V8" "LVCMOS_1V5" } + default_value { "LVCMOS_3V3" } + flavor data + description " + Select the device west bank IO buffer type to be used. + " + } + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR { + display "Variant IRQ priority defaults" + no_define + flavor none + parent CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME + description " + Interrupt priorities defined by the variant HAL" + script hal_cortexm_a2fxxx_irq.cdl + } + + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants" + flavor none + no_define + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + default_value 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR + description "The period defined here is something of a fake, it is expressed + in terms of a notional 1MHz clock. The value actually installed + in the hardware is calculated from the current settings of the + clock generation hardware." + } + } + + cdl_interface CYGINT_HAL_A2FXXX_UART0 { + display "Platform has UART0 serial port" + description "The platform has a socket on UART0." + } + + cdl_interface CYGINT_HAL_A2FXXX_UART1 { + display "Platform has UART1 serial port" + description "The platform has a socket on UART1." + } + + cdl_component CYGPKG_HAL_CORTEXM_A2FXXX_OPTIONS { + display "Build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package." + + cdl_option CYGPKG_HAL_CORTEXM_A2FXXX_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the A2F variant HAL package. These flags are used + in addition to the set of global flags." + } + + cdl_option CYGPKG_HAL_CORTEXM_A2FXXX_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the A2F variant HAL package. These flags are removed from + the set of global flags if present." + } + } + + cdl_option CYGPKG_HAL_CORTEXM_A2FXXX_TESTS { + display "A2F tests" + active_if CYGPKG_KERNEL + flavor data + no_define + calculated { "tests/timers" } + description " + This option specifies the set of tests for the A2F HAL." + } + +} \ No newline at end of file
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/var/current/cdl/hal_cortexm_a2fxxx_irq.cdl @@ -0,0 +1,150 @@ +##========================================================================== +## +## hal_cortexm_a2fxxx_irq.cdl +## +## Cortex-M A2F configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2012 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): ccoutand +## Date: 2012-02-20 +## +######DESCRIPTIONEND#### +## +##========================================================================== + + + cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY { + display "Clock interrupt ISR priority" + flavor data + calculated 0xF0 + description "Set clock ISR priority to lowest priority." + } + + + cdl_option CYGNUM_HAL_CORTEXM_A2FXXX_DMA_ISR_PRIORITY { + display "DMA peripheral interrupt ISR priority" + flavor data + default_value 0x70 + legal_values { 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 + 0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98 + 0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8 + 0xF0 } + description " + Set DMA controller ISR priority." + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_I2C { + display "I2C IRQ priorities" + flavor none + no_define + + cdl_option CYGNUM_DEVS_I2C_CORTEXM_A2FXXX_I2C0_ISR_PRIORITY { + display "I2C bus 0 interrupt priority" + flavor data + active_if CYGPKG_DEVS_I2C_CORTEXM_A2FXXX + legal_values { 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 + 0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98 + 0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8 + 0xF0 } + default_value 0x78 + } + + cdl_option CYGNUM_DEVS_I2C_CORTEXM_A2FXXX_I2C1_ISR_PRIORITY { + display "I2C bus 1 interrupt priority" + flavor data + active_if CYGPKG_DEVS_I2C_CORTEXM_A2FXXX + legal_values { 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 + 0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98 + 0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8 + 0xF0 } + default_value 0x78 + } + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_ETH { + display "Ethernet IRQ priorities" + flavor none + no_define + + cdl_option CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_ISR_SP { + display "Ethernet interrupt ISR priority" + active_if CYGPKG_DEVS_ETH_CORTEXM_A2FXXX + flavor data + no_define + default_value 0x78 + legal_values { 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 + 0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98 + 0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8 + 0xF0 } + description " + Set the Ethernet controller ISR priority." + } + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_SERIAL { + display "Serial controller IRQ priorities" + flavor none + no_define + + cdl_option CYGNUM_DEVS_SERIAL_CORTEXM_A2FXXX_SERIAL0_ISR_SP { + display "Serial port 0 driver ISR priority" + active_if CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0 + flavor data + no_define + default_value 0x78 + legal_values { 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 + 0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98 + 0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8 + 0xF0 } + description " + Set the serial 0 controller ISR priority." + } + + cdl_option CYGNUM_DEVS_SERIAL_CORTEXM_A2FXXX_SERIAL1_ISR_SP { + display "Serial port 1 driver ISR priority" + active_if CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1 + flavor data + no_define + default_value 0x80 + legal_values { 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 + 0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98 + 0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8 + 0xF0 } + description " + Set the serial 1 controller ISR priority." + } + } \ No newline at end of file
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/var/current/include/hal_cache.h @@ -0,0 +1,116 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H + +//============================================================================= +// +// hal_cache.h +// +// HAL cache control API +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jlarmour +// Contributors: +// Date: 2011-00-03 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// +// For the Atcel SmartFusion, these are empty macros as there +// is no cache. +// Usage: +// #include <cyg/hal/hal_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/infra/cyg_type.h> + +//----------------------------------------------------------------------------- +// Cache dimensions + + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() + +// Purge contents of data cache +#define HAL_DCACHE_PURGE_ALL() + +// Query the state of the data cache (does not affect the caching) +#define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() + +// Query the state of the instruction cache (does not affect the caching) +#define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_CACHE_H +// End of hal_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/var/current/include/hal_diag.h @@ -0,0 +1,91 @@ +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H +//============================================================================= +// +// hal_diag.h +// +// HAL diagnostics +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Original: nickg (STM32 HAL) +// Date: 2011-02-03 +// Purpose: HAL diagnostics +// Description: +// Usage: #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_if.h> + +//----------------------------------------------------------------------------- + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +#else + +__externC void hal_a2fxxx_diag_init(void); +__externC void hal_a2fxxx_diag_putc(char); +__externC cyg_uint8 hal_a2fxxx_diag_getc(void); + +# ifndef HAL_DIAG_INIT +# define HAL_DIAG_INIT() hal_a2fxxx_diag_init() +# endif + +# ifndef HAL_DIAG_WRITE_CHAR +# define HAL_DIAG_WRITE_CHAR(__c) hal_a2fxxx_diag_putc(__c) +# endif + +# ifndef HAL_DIAG_READ_CHAR +# define HAL_DIAG_READ_CHAR(__c) (__c) = hal_a2fxxx_diag_getc() +# endif + +#endif + +//----------------------------------------------------------------------------- +// end of hal_diag.h +#endif // CYGONCE_HAL_DIAG_H
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/var/current/include/plf_stub.h @@ -0,0 +1,89 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008 +// Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:jskov, gthomas, jlarmour +// Date: 2008-07-30 +// Purpose: Platform HAL stub support for STM32 variant boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_PLATFORM_H + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM + +#include <cyg/hal/cortexm_stub.h> // architecture stub support + +#include <cyg/hal/hal_io.h> + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +__externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Stub initializer. + +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/var/current/include/var_arch.h @@ -0,0 +1,66 @@ +#ifndef CYGONCE_HAL_VAR_ARCH_H +#define CYGONCE_HAL_VAR_ARCH_H +//============================================================================= +// +// var_arch.h +// +// Actel SmartFusion Cortex-M3 variant architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Date: 2011-01-18 +// Purpose: Actel SmartFusion Cortex-M3 variant architecture overrides +// Description: +// Usage: #include <cyg/hal/hal_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_io.h> + +#include <cyg/hal/plf_arch.h> + +#ifdef CYGSEM_HAL_CORTEXM_A2FXXX_DEFINES_IDLE_THREAD_ACTION +externC void hal_idle_thread_action( cyg_uint32 ); + +# define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_) +#endif +//----------------------------------------------------------------------------- +// end of var_arch.h +#endif // CYGONCE_HAL_VAR_ARCH_H
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/var/current/include/var_intr.h @@ -0,0 +1,232 @@ +#ifndef CYGONCE_HAL_VAR_INTR_H +#define CYGONCE_HAL_VAR_INTR_H +//========================================================================== +// +// var_intr.h +// +// HAL Interrupt and clock assignments for Smartfusion Cortex-M3 variants +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Date: 2011-01-18 +// Purpose: Define Interrupt support +// Description: The interrupt specifics for Actel Smartfusion Cortex-M3 +// are defined here. +// +// Usage: #include <cyg/hal/var_intr.h> +// However applications should include using <cyg/hal/hal_intr.h> +// instead to allow for platform overrides. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/plf_intr.h> + +//========================================================================== + +#define CYGNUM_HAL_INTERRUPT_WD (0+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_VR_PSM_5V (1+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_VR_PSM_3V (2+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_RTC0_0 (3+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_RTC0_1 (4+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_MAC0 (5+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_IAP (6+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ENVM0 (7+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ENVM1 (8+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_DMA (9+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_UART0 (10+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_UART1 (11+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_SPI0 (12+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_SPI1 (13+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C0_0 (14+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C0_1 (15+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C0_2 (16+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C1_0 (17+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C1_1 (18+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C1_2 (19+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM0_1 (20+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM0_2 (21+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_MSS_CCC_0 (22+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_MSS_CCC_1 (23+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_AHB (24+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_RESERVED0 (25+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_RESERVED1 (26+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_RESERVED2 (27+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_RESERVED3 (28+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_RESERVED4 (29+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_RESERVED5 (30+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_FAB (31+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO0 (32+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO1 (33+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO2 (34+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO3 (35+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO4 (36+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO5 (37+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO6 (38+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO7 (39+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO8 (40+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO9 (41+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO10 (42+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO11 (43+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO12 (44+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO13 (45+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO14 (46+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO15 (47+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO16 (48+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO17 (49+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO18 (50+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO19 (51+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO20 (52+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO21 (53+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO22 (54+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO23 (55+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO24 (56+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO25 (57+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO26 (58+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO27 (59+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO28 (60+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO29 (61+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO30 (62+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIO31 (63+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PC0_FLAG0 (64+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PC0_FLAG1 (65+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PC0_FLAG2 (66+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PC0_FLAG3 (67+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PC1_FLAG0 (68+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PC1_FLAG1 (69+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PC1_FLAG2 (70+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PC1_FLAG3 (71+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PC2_FLAG0 (72+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PC2_FLAG1 (73+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PC2_FLAG2 (74+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PC2_FLAG3 (75+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_ADC0_DV (76+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_ADC1_DV (77+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_ADC2_DV (78+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_ADC0_CD (79+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_ADC1_CD (80+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_ADC2_CD (81+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_ADC0_CS (81+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_ADC1_CS (83+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_ADC2_CS (84+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP0_FALL (85+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP1_FALL (86+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP2_FALL (87+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP3_FALL (88+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP4_FALL (89+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP5_FALL (90+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP6_FALL (91+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP7_FALL (92+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP8_FALL (93+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP9_FALL (94+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP10_FALL (95+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP11_FALL (96+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP0_RISE (97+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP1_RISE (98+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP2_RISE (99+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP3_RISE (100+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP4_RISE (101+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP5_RISE (102+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP6_RISE (103+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP7_RISE (104+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP8_RISE (105+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP9_RISE (106+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP10_RISE (107+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_COMP11_RISE (108+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_ADC0_FF (109+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_ADC0_FAF (110+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_ADC0_FE (111+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_ADC1_FF (112+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_ADC1_FAF (113+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_ADC1_FE (114+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_ADC2_FF (115+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_ADC2_FAF (116+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_ADC2_FE (117+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG0 (118+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG1 (119+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG2 (120+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG3 (121+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG4 (122+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG5 (123+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG6 (124+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG7 (125+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG8 (126+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG9 (127+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG10 (128+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG11 (129+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG12 (130+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG13 (131+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG14 (132+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG15 (133+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG16 (134+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG17 (135+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG18 (136+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG19 (137+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG20 (138+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG21 (139+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG22 (140+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG23 (141+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG24 (142+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG25 (143+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG26 (144+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG27 (145+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG28 (146+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG29 (147+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG30 (148+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG31 (149+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +#ifndef CYGNUM_HAL_INTERRUPT_NVIC_MAX +#define CYGNUM_HAL_INTERRUPT_NVIC_MAX (CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG31) +#endif + +#define CYGNUM_HAL_ISR_MIN 0 +#ifndef CYGNUM_HAL_ISR_MAX +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_NVIC_MAX +#endif +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1) + +#define CYGNUM_HAL_VSR_MIN 0 +#ifndef CYGNUM_HAL_VSR_MAX +#define CYGNUM_HAL_VSR_MAX (CYGNUM_HAL_VECTOR_SYS_TICK+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#endif +#define CYGNUM_HAL_VSR_COUNT (CYGNUM_HAL_VSR_MAX+1) + + +//---------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_INTR_H +// EOF var_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/var/current/include/var_io.h @@ -0,0 +1,1196 @@ +#ifndef CYGONCE_HAL_VAR_IO_H +#define CYGONCE_HAL_VAR_IO_H +//============================================================================= +// +// var_io.h +// +// Variant specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Date: 2011-02-03 +// Purpose: Smartfusion Cortex-M3 variant specific registers +// Description: +// Usage: #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal_cortexm_a2fxxx.h> + +#include <cyg/hal/plf_io.h> + +//============================================================================= +// Peripherals + +#define CYGHWR_HAL_A2FXXX_SC 0xE0042000 + +// Device peripherals +#define CYGHWR_HAL_A2FXXX_UART0 0x40000000 +#define CYGHWR_HAL_A2FXXX_SPI0 0x40001000 +#define CYGHWR_HAL_A2FXXX_I2C0 0x40002000 +#define CYGHWR_HAL_A2FXXX_MAC 0x40003000 +#define CYGHWR_HAL_A2FXXX_DMA 0x40004000 +#define CYGHWR_HAL_A2FXXX_TIMER 0x40005000 +#define CYGHWR_HAL_A2FXXX_WD 0x40006000 +#define CYGHWR_HAL_A2FXXX_FABRIC_IIC 0x40007000 +#define CYGHWR_HAL_A2FXXX_UART1 0x40010000 +#define CYGHWR_HAL_A2FXXX_SPI1 0x40011000 +#define CYGHWR_HAL_A2FXXX_I2C1 0x40012000 +#define CYGHWR_HAL_A2FXXX_MSS_GPIO 0x40013000 +#define CYGHWR_HAL_A2FXXX_RTC 0x40014000 +#define CYGHWR_HAL_A2FXXX_EFROM 0x40015000 +#define CYGHWR_HAL_A2FXXX_IAP 0x40016000 +#define CYGHWR_HAL_A2FXXX_ANALOG_ENGINE 0x40020000 +#define CYGHWR_HAL_A2FXXX_FPAG_ESRAM 0x40040000 +#define CYGHWR_HAL_A2FXXX_FPGA 0x40050000 +#define CYGHWR_HAL_A2FXXX_PERIPH 0x42000000 + +// Internal flash (Embedded Non-volatile Memory, ENVM) +#define CYGHWR_HAL_A2FXXX_ENVM_ARRAY 0x60000000 +#define CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES 0x60080000 +#define CYGHWR_HAL_A2FXXX_ENVM_AUX_BLOCK_A 0x60084000 +#define CYGHWR_HAL_A2FXXX_ENVM_AUX_BLOCK_SP 0x60088000 +#define CYGHWR_HAL_A2FXXX_ENVM 0x60100000 + +// External memory base address +#define CYGHWR_HAL_A2FXXX_EMEM_TYPE0 0x70000000 +#define CYGHWR_HAL_A2FXXX_EMEM_TYPE1 0x74000000 + +//============================================================================= +// Bit-Band base address +#define CYGHWR_HAL_A2FXXX_I2C0_BB ( CYGHWR_HAL_A2FXXX_PERIPH + 0x00040000 ) +#define CYGHWR_HAL_A2FXXX_I2C1_BB ( CYGHWR_HAL_A2FXXX_PERIPH + 0x00240000 ) +#define CYGHWR_HAL_A2FXXX_MSS_GPIO_BB ( CYGHWR_HAL_A2FXXX_PERIPH + 0x00260000 ) +#define CYGHWR_HAL_A2FXXX_MAC_BB ( CYGHWR_HAL_A2FXXX_PERIPH + 0x00060000 ) + +//============================================================================= +// Device signature and ID registers + +#define CYGHWR_HAL_A2FXXX_MCU_ID (CYGHWR_HAL_A2FXXX_CORTEXM3 + 0xD00) +#define CYGHWR_HAL_A2FXXX_MCU_ID_REV(__x) ((__x)&0xF) +#define CYGHWR_HAL_A2FXXX_MCU_PART_NO(__x) (((__x)>>4)&0x0FFF) +#define CYGHWR_HAL_A2FXXX_MCU_VAR_NO(__x) (((__x)>>20)&0xF) + + +//============================================================================= +// System Control +// +#define CYGHWR_HAL_A2FXXX_SC_ESRAM_CR 0x000 +#define CYGHWR_HAL_A2FXXX_SC_ENVM_CR 0x004 +#define CYGHWR_HAL_A2FXXX_SC_ENVM_REMAP_SYS_CR 0x008 +#define CYGHWR_HAL_A2FXXX_SC_ENVM_REMAP_FAB_CR 0x00C +#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_CR 0x010 +#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_BASE_CR 0x014 +#define CYGHWR_HAL_A2FXXX_SC_AHB_MATRIX_CR 0x018 +#define CYGHWR_HAL_A2FXXX_SC_MSS_SR 0x01C +#define CYGHWR_HAL_A2FXXX_SC_CLR_MSS_SR 0x020 +#define CYGHWR_HAL_A2FXXX_SC_EFROM_CR 0x024 +#define CYGHWR_HAL_A2FXXX_SC_IAP_CR 0x028 +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTIRQ_CR 0x02C +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR 0x030 +#define CYGHWR_HAL_A2FXXX_SC_DEVICE_SR 0x034 +#define CYGHWR_HAL_A2FXXX_SC_SYSTICK_CR 0x038 +#define CYGHWR_HAL_A2FXXX_SC_EMC_MUX_CR 0x03C +#define CYGHWR_HAL_A2FXXX_SC_EMC_CS0_CR 0x040 +#define CYGHWR_HAL_A2FXXX_SC_EMC_CS1_CR 0x044 +#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR 0x048 +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR 0x04C +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR 0x050 +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR 0x054 +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR 0x058 +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_SR 0x05C +#define CYGHWR_HAL_A2FXXX_SC_VRPSM_CR 0x064 +#define CYGHWR_HAL_A2FXXX_SC_FAB_APB_HW_DR 0x070 +#define CYGHWR_HAL_A2FXXX_SC_LOOPBACK_CR 0x074 +#define CYGHWR_HAL_A2FXXX_SC_MSS_IO_BANK_CR 0x078 +#define CYGHWR_HAL_A2FXXX_SC_GPIN_SOURCE_CR 0x07C +#define CYGHWR_HAL_A2FXXX_SC_IOMUX(_x_) ( 0x100 + (_x_ << 0x2) ) + +// Reset register +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_PAD BIT_(19) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_F2M BIT_(18) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_FPGA BIT_(17) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_EXT BIT_(16) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_IAP BIT_(15) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_GPIO BIT_(14) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_ACE BIT_(13) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_I2C1 BIT_(12) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_I2C0 BIT_(11) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_SPI1 BIT_(10) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_SPI0 BIT_(9) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_UART1 BIT_(8) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_UART0 BIT_(7) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_TIMER BIT_(6) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_PDMA BIT_(5) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_MAC BIT_(4) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_EMC BIT_(3) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_ESRAM1 BIT_(2) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_ESRAM0 BIT_(1) +#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_ENVM BIT_(0) + +#define CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(_periph) CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_##_periph + +void hal_a2fxxx_periph_reset( cyg_uint32 ); +void hal_a2fxxx_periph_release( cyg_uint32 ); + +#define CYGHWR_HAL_A2FXXX_PERIPH_RESET hal_a2fxxx_periph_reset +#define CYGHWR_HAL_A2FXXX_PERIPH_RELEASE hal_a2fxxx_periph_release + +#if 0 +#define CYGHWR_HAL_A2FXXX_PERIPH_START(_x) \ +{ \ + volatile int c = 0; \ + hal_a2fxxx_periph_reset(_x); \ + while( c++ < 20 ); \ + hal_a2fxxx_periph_release(_x); \ +} +#endif + +// MSS CLK register +#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GLBDIV(_x) VALUE_(12, ((_x)&0x3)) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_RTCIF(_x) VALUE_( 8, ((_x)&0xf)) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_ACLKDIV(_x) VALUE_( 6, ((_x)&0x3)) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_PCLK1DIV(_x) VALUE_( 4, ((_x)&0x3)) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_PCLK0DIV(_x) VALUE_( 2, ((_x)&0x3)) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GET_PCLK0DIV(_x) ((_x & 0x000C) >> 2) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GET_PCLK1DIV(_x) ((_x & 0x0030) >> 4) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GET_GLBDIV(_x) ((_x & 0x0C00) >> 12) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_RMIICLKSEL BIT_(0) + +// MSS CCC DIV register +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIVRST BIT_(22) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIVHALF BIT_(21) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIV(_x) VALUE_(16, _x) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIVRST BIT_(14) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIVHALF BIT_(13) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIV(_x) VALUE_( 8, _x) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIVRST BIT_(6) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIVHALF BIT_(5) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIV(_x) VALUE_( 0, _x) + +// MSS CCC MUX register +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_MAINOSCM(_x) VALUE_(30, _x) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_MAINOSCEN BIT_(29) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXCFG(_x) VALUE_(26, _x) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXSEL(_x) VALUE_(24, _x) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSC BIT_(22) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OCMUX(_x) VALUE_(19, _x) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_DYNCSEL BIT_(18) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_RXCSEL BIT_(17) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_STATCSEL BIT_(16) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSB BIT_(14) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OBMUX(_x) VALUE_(11, _x) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_DYNBSEL BIT_(10) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_RXBSEL BIT_(9) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_STATBSEL BIT_(8) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSA BIT_(6) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OAMUX(_x) VALUE_( 3, _x) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_DYNASEL BIT_(2) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_RXASEL BIT_(1) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_STATASEL BIT_(0) + +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLA 0 +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLC 1 +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLINT 2 +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GND 3 + +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_CLKA_SEL(_x_) \ +({ \ + cyg_uint32 _i = _x_; \ + _i; \ +}) + +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_CLKB_SEL(_x_) \ +({ \ + cyg_uint32 _i = _x_; \ + _i = _i << 8; \ + _i; \ +}) + +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_CLKC_SEL(_x_) \ +({ \ + cyg_uint32 _i = _x_; \ + _i = _i << 16; \ + _i; \ +}) + +// MSS CCC PLL register +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_PLLEN BIT_(31) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_VCOSEL2_1(_x) VALUE_(23, _x) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_VCOSEL0 BIT_(22) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_XDLYSEL(_x) VALUE_(21, _x) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FBDLY(_x) VALUE_(16, _x) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FBSEL(_x) VALUE_(14, _x) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FBDIV(_x) VALUE_(7, _x) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FINDIV(_x) VALUE_(0, _x) + +// Delay Configuration Register +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA1(_x) VALUE_(20, _x) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA0(_x) VALUE_(15, _x) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYC(_x) VALUE_(10, _x) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYB(_x) VALUE_(5, _x) +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA(_x) VALUE_(0, _x) + +// CCC Status Register +#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_SR_PLL_LOCK_SYNC BIT_(0) + +// ESRAM control register +#define CYGHWR_HAL_A2FXXX_SC_ESRAM_CR_REMAP BIT_(0) + +// ENVM control register +#define CYGHWR_HAL_A2FXXX_SC_ENVM_CR_SIX_CYCLE BIT_(7) +#define CYGHWR_HAL_A2FXXX_SC_ENVM_CR_PIPE_BYPASS BIT_(6) +#define CYGHWR_HAL_A2FXXX_SC_ENVM_CR_REMAP_SIZE(_s_) VALUE_(0, _s_) + +// ENVM re-mapping in system or fabric master space register +#define CYGHWR_HAL_A2FXXX_SC_ENVM_REMAP_BASE(_b_) VALUE_(1, _b_) +#define CYGHWR_HAL_A2FXXX_SC_ENVM_REMAP_EN BIT_(0) + +// Fabric protect size +#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_128B VALUE_(0, 6) +#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_2KB VALUE_(0, 10) +#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_16KB VALUE_(0, 13) +#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_32KB VALUE_(0, 14) +#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_64KB VALUE_(0, 15) +#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_128KB VALUE_(0, 16) +#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_256KB VALUE_(0, 17) +#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_512KB VALUE_(0, 18) +#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_8MB VALUE_(0, 22) +#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_128MB VALUE_(0, 26) +#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_2GB VALUE_(0, 30) + +// Fabric protect control register +#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_BASE_CR_VAL(_x) VALUE_( 1, _x) +#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_BASE_CR_EN BIT_(0) + +// Embedded FlashROM control register +#define CYGHWR_HAL_A2FXXX_SC_EFROM_CR_SYS_TOPT3_1(_v_) VALUE_(1, _v_) +#define CYGHWR_HAL_A2FXXX_SC_EFROM_CR_SYS_TOPT0 BIT_(0) + +//============================================================================= +// DMA +// + +#define CYGHWR_HAL_A2FXXX_DMA_RATIO 0x0 +#define CYGHWR_HAL_A2FXXX_DMA_BUFFER_STATUS 0x4 +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(_x_) (0x20 + (_x_ * 0x20)) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_STATUS(_x_) (0x24 + (_x_ * 0x20)) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_BA_SRC(_x_) (0x28 + (_x_ * 0x20)) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_BA_DST(_x_) (0x2C + (_x_ * 0x20)) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_BA_COUNT(_x_) (0x30 + (_x_ * 0x20)) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_BB_SRC(_x_) (0x34 + (_x_ * 0x20)) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_BB_DST(_x_) (0x38 + (_x_ * 0x20)) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_BB_COUNT(_x_) (0x3C + (_x_ * 0x20)) + +// Ratio +#define CYGHWR_HAL_A2FXXX_DMA_RATIO_HILO(_x_) VALUE_(0, _x_) + +// Buffer status +#define CYGHWR_HAL_A2FXXX_DMA_BUFFER_STATUS_CHAxx(_x_) VALUE_( (_x_ << 1), 1) +#define CYGHWR_HAL_A2FXXX_DMA_BUFFER_STATUS_CHAx(_x_) VALUE_(((_x_ << 1)+1), 1) + +// Channel control +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_PERIPH_SEL(_p_) VALUE_(23, _p_) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_WR_ADJ(_v_) VALUE_(14, _v_) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR_4B VALUE_(12, 0x3) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR_2B VALUE_(12, 0x2) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR_1B VALUE_(12, 0x1) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR_0B VALUE_(12, 0x0) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR(_x_) VALUE_(12, ((_x_) & 0x3)) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR_4B VALUE_(10, 0x3) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR_2B VALUE_(10, 0x2) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR_1B VALUE_(10, 0x1) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR_0B VALUE_(10, 0x0) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR(_x_) VALUE_(10, ((_x_) & 0x3)) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_HI_PRI BIT_(9) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_COMPB BIT_(8) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_COMPA BIT_(7) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_INTEN BIT_(6) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_RESET BIT_(5) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_PAUSE BIT_(4) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_XFER_WORD VALUE_(2, 0x2) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_XFER_HWORD VALUE_(2, 0x1) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_XFER_BYTE VALUE_(2, 0x0) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DIR BIT_(1) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_PERIPH BIT_(0) + +// DMA transfer type +#define CYGHWR_HAL_A2FXXX_DMA_XFER_FROM_UART0 0x0 +#define CYGHWR_HAL_A2FXXX_DMA_XFER_TO_UART0 0x1 +#define CYGHWR_HAL_A2FXXX_DMA_XFER_FROM_UART1 0x2 +#define CYGHWR_HAL_A2FXXX_DMA_XFER_TO_UART1 0x3 +#define CYGHWR_HAL_A2FXXX_DMA_XFER_FROM_SPI0 0x4 +#define CYGHWR_HAL_A2FXXX_DMA_XFER_TO_SPI0 0x5 +#define CYGHWR_HAL_A2FXXX_DMA_XFER_FROM_SPI1 0x6 +#define CYGHWR_HAL_A2FXXX_DMA_XFER_TO_SPI1 0x7 +#define CYGHWR_HAL_A2FXXX_DMA_XFER_FROM_FPGA 0x8 +#define CYGHWR_HAL_A2FXXX_DMA_XFER_TO_FPGA 0x9 +#define CYGHWR_HAL_A2FXXX_DMA_XFER_FROM_ACE 0x10 +#define CYGHWR_HAL_A2FXXX_DMA_XFER_TO_ACE 0x11 +#define CYGHWR_HAL_A2FXXX_DMA_XFER_MEMORY 0xff + +#define CYGHWR_HAL_A2FXXX_DMA_XFER(_x) CYGHWR_HAL_A2FXXX_DMA_XFER_##_x + +#define CYGHWR_HAL_A2FXXX_DMA_GET_SUB_ID(_x) ((_x>>2) & 0x01) + +// Channel status +#define CYGHWR_HAL_A2FXXX_DMA_CHx_STATUS_BUF_SEL BIT_(2) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_STATUS_COMPB BIT_(1) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_STATUS_COMPA BIT_(0) + +// Buffer count +#define CYGHWR_HAL_A2FXXX_DMA_CHx_BA_COUNT_FIELD(_c) VALUE_(0, _c) +#define CYGHWR_HAL_A2FXXX_DMA_CHx_BB_COUNT_FIELD(_c) VALUE_(0, _c) + +#define CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL 8 +#define CYGHWR_HAL_A2FXXX_DMA_MAX_SUB_CHANNEL 2 + +// DMA access prototypes +void hal_dma_init ( void ); +cyg_uint32 a2fxxx_dma_xfer (cyg_uint8 , cyg_bool , cyg_uint32 len, cyg_uint8* , cyg_uint8* ); +cyg_uint32 a2fxxx_dma_ch_setup (cyg_uint8 , cyg_uint8 , cyg_bool , cyg_uint8 , cyg_uint8 , cyg_bool, cyg_uint8); +void a2fxxx_dma_ch_detach (cyg_uint8 ); +void a2fxxx_dma_update_incr (cyg_uint8 , cyg_bool , cyg_uint8 ); +void a2fxxx_dma_clear_interrupt (cyg_uint8 ); +cyg_uint8 a2fxxx_dma_get_comp_flag (cyg_uint8 ); + +#define CYGHWR_HAL_A2FXXX_DMA_OUTBOUND true +#define CYGHWR_HAL_A2FXXX_DMA_INBOUND false + +//============================================================================= +// ENVM +// +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS 0x00 +#define CYGHWR_HAL_A2FXXX_ENVM_CTRL 0x04 +#define CYGHWR_HAL_A2FXXX_ENVM_IRQ 0x08 +#define CYGHWR_HAL_A2FXXX_ENVM0_CR 0x10 +#define CYGHWR_HAL_A2FXXX_ENVM1_CR 0x14 +#define CYGHWR_HAL_A2FXXX_ENVM0_PAGE_STATUS 0x18 +#define CYGHWR_HAL_A2FXXX_ENVM1_PAGE_STATUS 0x1C + +// Status Register +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ILLEGAL_CMD_1 BIT_(31) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_1 VALUE_(24, 0x3) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_OP_DONE_1 BIT_(23) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ECC2_ERR_1 BIT_(22) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ECC1_ERR_1 BIT_(21) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_OVER_THR_1 BIT_(20) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ERASE_ERR_1 BIT_(19) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_PROG_ERR_1 BIT_(18) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_PROT_ERR_1 BIT_(17) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_BSY_1 BIT_(16) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ILLEGAL_CMD_0 BIT_(15) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_0 VALUE_( 8, 0x3) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_OP_DONE_0 BIT_(7) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ECC2_ERR_0 BIT_(6) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ECC1_ERR_0 BIT_(5) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_OVER_THR_0 BIT_(4) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ERASE_ERR_0 BIT_(3) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_PROG_ERR_0 BIT_(2) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_PROT_ERR_0 BIT_(1) +#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_BSY_0 BIT_(0) + +// Control Register +#define CYGHWR_HAL_A2FXXX_ENVM_CTRL_COMMAND(_x_) VALUE_(24, _x_) +#define CYGHWR_HAL_A2FXXX_ENVM_CTRL_PAGE_ADDR(_x_) VALUE_( 0, _x_) + +// Interrupt Enable +#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ILLEGAL_CMD_1 BIT_(31) +#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_OP_DONE_1 BIT_(23) +#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ECC2_ERR_1 BIT_(22) +#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ECC1_ERR_1 BIT_(21) +#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_OVER_THR_1 BIT_(20) +#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ERASE_ERR_1 BIT_(19) +#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_PROG_ERR_1 BIT_(18) +#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_PROT_ERR_1 BIT_(17) +#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ILLEGAL_CMD_0 BIT_(15) +#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_OP_DONE_0 BIT_(7) +#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ECC2_ERR_0 BIT_(6) +#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ECC1_ERR_0 BIT_(5) +#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_OVER_THR_0 BIT_(4) +#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ERASE_ERR_0 BIT_(3) +#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_PROG_ERR_0 BIT_(2) +#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_PROT_ERR_0 BIT_(1) + +// Configuration Register +#define CYGHWR_HAL_A2FXXX_ENVMx_CR_LOCK BIT_(2) +#define CYGHWR_HAL_A2FXXX_ENVMx_CR_PAGE_LOSS BIT_(1) +#define CYGHWR_HAL_A2FXXX_ENVMx_CR_READ_NEXT BIT_(0) + +// Page status +#define CYGHWR_HAL_A2FXXX_ENVMx_PAGE_STATUS_WCOUNT VALUE_(8, 0x00ffffffff) +#define CYGHWR_HAL_A2FXXX_ENVMx_PAGE_STATUS_OVER_THR BIT_(3) +#define CYGHWR_HAL_A2FXXX_ENVMx_PAGE_STATUS_RPROT BIT_(2) +#define CYGHWR_HAL_A2FXXX_ENVMx_PAGE_STATUS_WPROT BIT_(1) +#define CYGHWR_HAL_A2FXXX_ENVMx_PAGE_STATUS_OPROT BIT_(0) + + +//============================================================================= +// eSRAM +// + +#define CYGHWR_HAL_A2FXXX_ESRAM_CR 0xE0002000 +#define CYGHWR_HAL_A2FXXX_AHB_MATRIX_CR 0xE0002018 + +#define CYGHWR_HAL_A2FXXX_ESRAM_CR_REMAP BIT_(0) + + +//============================================================================= +// SPI +// +#define CYGHWR_HAL_A2FXXX_SPI_CTRL 0x00 +#define CYGHWR_HAL_A2FXXX_SPI_TXRXDF_SIZE 0x04 +#define CYGHWR_HAL_A2FXXX_SPI_STATUS 0x08 +#define CYGHWR_HAL_A2FXXX_SPI_IRQ_CLEAR 0x0C +#define CYGHWR_HAL_A2FXXX_SPI_RX 0x10 +#define CYGHWR_HAL_A2FXXX_SPI_TX 0x14 +#define CYGHWR_HAL_A2FXXX_SPI_CLK_GEN 0x18 +#define CYGHWR_HAL_A2FXXX_SPI_SLAVE_SEL 0x1C +#define CYGHWR_HAL_A2FXXX_SPI_MIS 0x20 +#define CYGHWR_HAL_A2FXXX_SPI_RIS 0x24 + +// Control Register +#define CYGHWR_HAL_A2FXXX_SPI_CTRL_SPH BIT_(25) +#define CYGHWR_HAL_A2FXXX_SPI_CTRL_SPO BIT_(24) +#define CYGHWR_HAL_A2FXXX_SPI_CTRL_COUNT(_x) VALUE_(8, _x) +#define CYGHWR_HAL_A2FXXX_SPI_CTRL_IRQ_TX_UNRRUN BIT_(7) +#define CYGHWR_HAL_A2FXXX_SPI_CTRL_IRQ_RX_OVRFLO BIT_(6) +#define CYGHWR_HAL_A2FXXX_SPI_CTRL_IRQ_TX BIT_(5) +#define CYGHWR_HAL_A2FXXX_SPI_CTRL_IRQ_RX BIT_(4) +#define CYGHWR_HAL_A2FXXX_SPI_CTRL_PROTO_NS VALUE_(2, 0x2) +#define CYGHWR_HAL_A2FXXX_SPI_CTRL_PROTO_TI VALUE_(2, 0x1) +#define CYGHWR_HAL_A2FXXX_SPI_CTRL_PROTO_MOTOROLA VALUE_(2, 0x0) +#define CYGHWR_HAL_A2FXXX_SPI_CTRL_MASTER BIT_(1) +#define CYGHWR_HAL_A2FXXX_SPI_CTRL_EN BIT_(0) + +// Status Register +#define CYGHWR_HAL_A2FXXX_SPI_STATUS_TX_FIFO_EMPTY_N BIT_(11) +#define CYGHWR_HAL_A2FXXX_SPI_STATUS_TX_FIFO_EMPTY BIT_(10) +#define CYGHWR_HAL_A2FXXX_SPI_STATUS_TX_FIFO_FULL_N BIT_(9) +#define CYGHWR_HAL_A2FXXX_SPI_STATUS_TX_FIFO_FULL BIT_(8) +#define CYGHWR_HAL_A2FXXX_SPI_STATUS_RX_FIFO_EMPTY_N BIT_(7) +#define CYGHWR_HAL_A2FXXX_SPI_STATUS_RX_FIFO_EMPTY BIT_(6) +#define CYGHWR_HAL_A2FXXX_SPI_STATUS_RX_FIFO_FULL_N BIT_(5) +#define CYGHWR_HAL_A2FXXX_SPI_STATUS_RX_FIFO_FULL BIT_(4) +#define CYGHWR_HAL_A2FXXX_SPI_STATUS_TX_UNDERRUN BIT_(3) +#define CYGHWR_HAL_A2FXXX_SPI_STATUS_RX_OVERFLOW BIT_(2) +#define CYGHWR_HAL_A2FXXX_SPI_STATUS_RX_RCED BIT_(1) +#define CYGHWR_HAL_A2FXXX_SPI_STATUS_TX_SENT BIT_(0) + +// Interrupt Clear Register +#define CYGHWR_HAL_A2FXXX_SPI_IRQ_CLEAR_TXUNDRUN BIT_(3) +#define CYGHWR_HAL_A2FXXX_SPI_IRQ_CLEAR_RXOVRFLW BIT_(2) +#define CYGHWR_HAL_A2FXXX_SPI_IRQ_CLEAR_RXRDY BIT_(1) +#define CYGHWR_HAL_A2FXXX_SPI_IRQ_CLEAR_TXDONE BIT_(0) + +// Masked Interrupt +#define CYGHWR_HAL_A2FXXX_SPI_MIS_TXUNDRUN BIT_(3) +#define CYGHWR_HAL_A2FXXX_SPI_MIS_RXOVRFLW BIT_(2) +#define CYGHWR_HAL_A2FXXX_SPI_MIS_RXRDY BIT_(1) +#define CYGHWR_HAL_A2FXXX_SPI_MIS_TXDONE BIT_(0) + +// Raw Interrupt Status +#define CYGHWR_HAL_A2FXXX_SPI_RIS_TXUNDRUN BIT_(3) +#define CYGHWR_HAL_A2FXXX_SPI_RIS_RXOVRFLW BIT_(2) +#define CYGHWR_HAL_A2FXXX_SPI_RIS_RXRDY BIT_(1) +#define CYGHWR_HAL_A2FXXX_SPI_RIS_TXDONE BIT_(0) + +// Chip select selection +#define CYGHWR_HAL_A2FXXX_SPI_CS_SEL(_dev) (0x1 << _dev) + +// Peripherals IOs mapping +#define CYGHWR_HAL_A2FXXX_SPI0_DO CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_DO, DISABLE ) +#define CYGHWR_HAL_A2FXXX_SPI0_DI CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_DI, DISABLE ) +#define CYGHWR_HAL_A2FXXX_SPI0_CLK CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_CLK, DISABLE ) +#define CYGHWR_HAL_A2FXXX_SPI0_SS0 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_SS_0, DISABLE ) +#define CYGHWR_HAL_A2FXXX_SPI0_SS1 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_SS_1, DISABLE ) +#define CYGHWR_HAL_A2FXXX_SPI0_SS2 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_SS_2, DISABLE ) +#define CYGHWR_HAL_A2FXXX_SPI0_SS3 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_SS_3, DISABLE ) + +#define CYGHWR_HAL_A2FXXX_SPI1_DO CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_DO, DISABLE ) +#define CYGHWR_HAL_A2FXXX_SPI1_DI CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_DI, DISABLE ) +#define CYGHWR_HAL_A2FXXX_SPI1_CLK CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_CLK, DISABLE ) +#define CYGHWR_HAL_A2FXXX_SPI1_SS0 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_0, DISABLE ) +#define CYGHWR_HAL_A2FXXX_SPI1_SS1 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_1, DISABLE ) +#define CYGHWR_HAL_A2FXXX_SPI1_SS2 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_2, DISABLE ) +#define CYGHWR_HAL_A2FXXX_SPI1_SS3 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_3, DISABLE ) +#define CYGHWR_HAL_A2FXXX_SPI1_SS4 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_4, DISABLE ) +#define CYGHWR_HAL_A2FXXX_SPI1_SS5 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_5, DISABLE ) +#define CYGHWR_HAL_A2FXXX_SPI1_SS6 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_6, DISABLE ) +#define CYGHWR_HAL_A2FXXX_SPI1_SS7 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_7, DISABLE ) + +// This is a special GPIO macro accommodated for SPI slave select +#define CYGHWR_HAL_A2FXXX_CS_GPIO( \ + __bit, \ + __mode, \ + __p_io, \ + __irq) \ +( \ + (__bit << 23) | \ + (CYGHWR_HAL_A2FXXX_GPIO_MODE_ ## __mode) | \ + CYGHWR_HAL_A2FXXX_GPIO_PERIPH_GPIO(__p_io) | \ + (CYGHWR_HAL_A2FXXX_GPIO_IRQ_ ## __irq) \ +) + +__externC cyg_uint32 hal_a2fxxx_spi_clock( cyg_uint32 ); + +//============================================================================= +// I2C +// +#define CYGHWR_HAL_A2FXXX_I2C_CTRL 0x00 +#define CYGHWR_HAL_A2FXXX_I2C_STATUS 0x04 +#define CYGHWR_HAL_A2FXXX_I2C_DATA 0x08 +#define CYGHWR_HAL_A2FXXX_I2C_ADDR 0x0C +#define CYGHWR_HAL_A2FXXX_I2C_SMBUS 0x10 +#define CYGHWR_HAL_A2FXXX_I2C_FREQ 0x14 +#define CYGHWR_HAL_A2FXXX_I2C_GLITCH 0x18 + +// Control Register +#define CYGHWR_HAL_A2FXXX_I2C_CTRL_CR2 BIT_(7) +#define CYGHWR_HAL_A2FXXX_I2C_CTRL_ENS1 BIT_(6) +#define CYGHWR_HAL_A2FXXX_I2C_CTRL_STA BIT_(5) +#define CYGHWR_HAL_A2FXXX_I2C_CTRL_STO BIT_(4) +#define CYGHWR_HAL_A2FXXX_I2C_CTRL_SI BIT_(3) +#define CYGHWR_HAL_A2FXXX_I2C_CTRL_AA BIT_(2) +#define CYGHWR_HAL_A2FXXX_I2C_CTRL_CR1 BIT_(1) +#define CYGHWR_HAL_A2FXXX_I2C_CTRL_CR0 BIT_(0) + +// I2C clock divider +#define CYGHWR_HAL_A2FXXX_I2C_DIV_8 0x7 +#define CYGHWR_HAL_A2FXXX_I2C_DIV_60 0x6 +#define CYGHWR_HAL_A2FXXX_I2C_DIV_120 0x5 +#define CYGHWR_HAL_A2FXXX_I2C_DIV_960 0x4 +#define CYGHWR_HAL_A2FXXX_I2C_DIV_160 0x3 +#define CYGHWR_HAL_A2FXXX_I2C_DIV_192 0x2 +#define CYGHWR_HAL_A2FXXX_I2C_DIV_224 0x1 +#define CYGHWR_HAL_A2FXXX_I2C_DIV_256 0x0 + +// Status Registers +#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_START 0x08 +#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_REPEAT_START 0x10 +#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_ADDR_ACK 0x18 +#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_ADDR_NACK 0x20 +#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_DATA_ACK 0x28 +#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_DATA_NACK 0x30 +#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_ARBLOST 0x38 + +#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_START 0x08 +#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_REPEAT_START 0x10 +#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_ARBLOST 0x38 +#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_ADDR_ACK 0x40 +#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_ADDR_NACK 0x48 +#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_DATA_ACK 0x50 +#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_DATA_NACK 0x58 + +#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRESET 0xD0 + +// SMB +#define CYGHWR_HAL_A2FXXX_I2C_SMBUS_RST BIT_(7) +#define CYGHWR_HAL_A2FXXX_I2C_SMBUS_NO BIT_(6) +#define CYGHWR_HAL_A2FXXX_I2C_SMBUS_NI BIT_(5) +#define CYGHWR_HAL_A2FXXX_I2C_SMBALERT_NO BIT_(4) +#define CYGHWR_HAL_A2FXXX_I2C_SMBALERT_NI BIT_(3) +#define CYGHWR_HAL_A2FXXX_I2C_SMBUS_EN BIT_(2) +#define CYGHWR_HAL_A2FXXX_I2C_SMBUS_IRQ_EN BIT_(1) +#define CYGHWR_HAL_A2FXXX_I2C_SMBUS_ALERT_IRQ_EN BIT_(0) + +// Peripherals IOs mapping +#define CYGHWR_HAL_A2FXXX_I2C0_SDA CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, I2C0_SDA, DISABLE ) +#define CYGHWR_HAL_A2FXXX_I2C0_SCL CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, I2C0_SCL, DISABLE ) + +#define CYGHWR_HAL_A2FXXX_I2C1_SDA CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, I2C1_SDA, DISABLE ) +#define CYGHWR_HAL_A2FXXX_I2C1_SCL CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, I2C1_SCL, DISABLE ) + +__externC cyg_uint32 hal_a2fxxx_i2c_clock( cyg_uint32 ); + +//============================================================================= +// GPIO +// +#define CYGHWR_HAL_A2FXXX_MSS_GPIO_CFG(_io) (_io << 2) +#define CYGHWR_HAL_A2FXXX_MSS_GPIO_INT 0x080 +#define CYGHWR_HAL_A2FXXX_MSS_GPIO_DIN 0x084 +#define CYGHWR_HAL_A2FXXX_MSS_GPIO_DOUT 0x088 + +#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR 0xe0042078 +#define CYGHWR_HAL_A2FXXX_GPIN_SOURCE_CR 0xe004207c +#define CYGHWR_HAL_A2FXXX_IOMUX_CR 0xe0042100 + +// CFG +#define CYGHWR_HAL_A2FXXX_GPIO_CFG_INTYPE(_t) VALUE_(5, (_t & 0x7)) +#define CYGHWR_HAL_A2FXXX_GPIO_CFG_GPINTEN BIT_(3) +#define CYGHWR_HAL_A2FXXX_GPIO_CFG_OUTBUFEN BIT_(2) +#define CYGHWR_HAL_A2FXXX_GPIO_CFG_GPINEN BIT_(1) +#define CYGHWR_HAL_A2FXXX_GPIO_CFG_GPOUTEN BIT_(0) + +// MSS GPIO +#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_LVCMOS_3V3 0x0 +#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_LVCMOS_2V5 0x1 +#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_LVCMOS_1V8 0x2 +#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_LVCMOS_1V5 0x3 + +#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTEAST(_t) VALUE_(0, (CYGHWR_HAL_A2FXXX_MSS_IO_BANK_##_t & 0x3)) +#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTWEST(_t) VALUE_(2, (CYGHWR_HAL_A2FXXX_MSS_IO_BANK_##_t & 0x3)) + +// HAL definitions +#define CYGHWR_HAL_A2FXXX_GPIO_MODE_IN VALUE_(0,0) // Input mode +#define CYGHWR_HAL_A2FXXX_GPIO_MODE_OUT VALUE_(0,1) // Output mode +#define CYGHWR_HAL_A2FXXX_GPIO_MODE_PERIPH VALUE_(0,2) // Peripheral function mode + +#define CYGHWR_HAL_A2FXXX_GPIO_PERIPH_IO(_name_) VALUE_(2, CYGHWR_HAL_A2FXXX_IOMUX_##_name_) +#define CYGHWR_HAL_A2FXXX_GPIO_PERIPH_GPIO(_id_) VALUE_(2, (CYGHWR_HAL_A2FXXX_IOMUX_GPIO_0+_id_)) + +#define CYGHWR_HAL_A2FXXX_GPIO_IRQ_DISABLE VALUE_(10,0) // Interrupt disable +#define CYGHWR_HAL_A2FXXX_GPIO_IRQ_FALLING_EDGE VALUE_(10,1) // Interrupt on falling edge +#define CYGHWR_HAL_A2FXXX_GPIO_IRQ_RISING_EDGE VALUE_(10,2) // Interrupt on rising edge +#define CYGHWR_HAL_A2FXXX_GPIO_IRQ_BOTH_EDGES VALUE_(10,3) // Interrupt on both edges +#define CYGHWR_HAL_A2FXXX_GPIO_IRQ_LOW_LEVEL VALUE_(10,4) // Interrupt on low level +#define CYGHWR_HAL_A2FXXX_GPIO_IRQ_HIGH_LEVEL VALUE_(10,5) // Interrupt on high level + +typedef struct +{ + cyg_uint32 val; +} default_io_mux_type; + +// IOMUX index setting for peripherals +#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_DO 0 +#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_DI 1 +#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_CLK 2 +#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_SS_0 3 +#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_TX 4 +#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_RX 5 +#define CYGHWR_HAL_A2FXXX_IOMUX_I2C0_SDA 6 +#define CYGHWR_HAL_A2FXXX_IOMUX_I2C0_SCL 7 +#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_DO 8 +#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_DI 9 +#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_CLK 10 +#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_0 11 +#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_TX 12 +#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_RX 13 +#define CYGHWR_HAL_A2FXXX_IOMUX_I2C1_SDA 14 +#define CYGHWR_HAL_A2FXXX_IOMUX_I2C1_SCL 15 +#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_TXD0 16 +#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_TXD1 17 +#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_RXD0 18 +#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_RXD1 19 +#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_TXEN 20 +#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_CRSDV 21 +#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_RXER 22 +#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_MDIO 23 +#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_MDC 24 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_0 25 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_1 26 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_2 27 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_3 28 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_4 29 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_5 30 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_6 31 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_7 32 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_8 33 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_9 34 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_10 35 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_11 36 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_12 37 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_13 38 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_14 39 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_15 40 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_16 41 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_17 42 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_18 43 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_19 44 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_20 45 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_21 46 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_22 47 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_23 48 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_24 49 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_25 50 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_26 51 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_27 52 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_28 53 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_29 54 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_30 55 +#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_31 56 +#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_SS_1 57 +#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_SS_2 58 +#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_SS_3 59 +// 60 to 63 not used +#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_RTS 64 +#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_DTR 65 +#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_CTS 66 +#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_DSR 67 +#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_RI 68 +#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_DCD 69 +#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_1 70 +#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_2 71 +#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_3 72 +#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_4 73 +#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_5 74 +#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_6 75 +#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_7 76 +#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_RTS 77 +#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_DTR 78 +#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_CTS 79 +#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_DSR 80 +#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_RI 81 +#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_DCD 82 +#define CYGHWR_HAL_A2FXXX_IOMUX_NONE 83 + +// This macro packs the port, bit number, mode, buffer and irq +// for a GPIO pin into a single word. +// The packing puts: + +#define CYGHWR_HAL_A2FXXX_GPIO( \ + __bit, \ + __mode, \ + __name, \ + __irq) \ +( \ + (__bit << 23) | \ + (CYGHWR_HAL_A2FXXX_GPIO_MODE_ ## __mode) | \ + CYGHWR_HAL_A2FXXX_GPIO_PERIPH_IO(__name) | \ + (CYGHWR_HAL_A2FXXX_GPIO_IRQ_ ## __irq) \ +) + + +// Macros to extract encoded values +#define CYGHWR_HAL_A2FXXX_GPIO_BIT(__pin) (((__pin)>>23) & 0x1F) +#define CYGHWR_HAL_A2FXXX_GPIO_MODE(__pin) ((__pin)&0x0003) +#define CYGHWR_HAL_A2FXXX_GPIO_IOMUX_IDX(__pin) ((__pin>>2) & 0xff) +#define CYGHWR_HAL_A2FXXX_GPIO_IRQ(__pin) ((__pin>>10) & 0x07) +#define CYGHWR_HAL_A2FXXX_GPIO_NONE (0xFFFFFFFF) + +__externC void hal_a2fxxx_gpio_set( cyg_uint32 pin ); +__externC void hal_a2fxxx_gpio_out( cyg_uint32 pin, int val ); +__externC void hal_a2fxxx_gpio_in ( cyg_uint32 pin, int *val ); + +#define CYGHWR_HAL_A2FXXX_GPIO_SET(__pin ) hal_a2fxxx_gpio_set( __pin ) +#define CYGHWR_HAL_A2FXXX_GPIO_OUT(__pin, __val ) hal_a2fxxx_gpio_out( __pin, __val ) +#define CYGHWR_HAL_A2FXXX_GPIO_IN(__pin, __val ) hal_a2fxxx_gpio_in( __pin, __val ) + + +//============================================================================= +// UART +// +#define CYGHWR_HAL_A2FXXX_UART16550_RBR 0x00 +#define CYGHWR_HAL_A2FXXX_UART16550_THR 0x00 +#define CYGHWR_HAL_A2FXXX_UART16550_DLR 0x00 +#define CYGHWR_HAL_A2FXXX_UART16550_DMR 0x04 +#define CYGHWR_HAL_A2FXXX_UART16550_IER 0x04 +#define CYGHWR_HAL_A2FXXX_UART16550_IIR 0x08 +#define CYGHWR_HAL_A2FXXX_UART16550_FCR 0x08 +#define CYGHWR_HAL_A2FXXX_UART16550_LCR 0x0C +#define CYGHWR_HAL_A2FXXX_UART16550_MCR 0x10 +#define CYGHWR_HAL_A2FXXX_UART16550_LSR 0x14 +#define CYGHWR_HAL_A2FXXX_UART16550_MSR 0x18 +#define CYGHWR_HAL_A2FXXX_UART16550_SR 0x1C + +// IER +#define CYGHWR_HAL_A2FXXX_UART16550_IER_EDSSI BIT_(3) +#define CYGHWR_HAL_A2FXXX_UART16550_IER_ELSI BIT_(2) +#define CYGHWR_HAL_A2FXXX_UART16550_IER_ETBEI BIT_(1) +#define CYGHWR_HAL_A2FXXX_UART16550_IER_ERBFI BIT_(0) + +// IIR (by priority) +#define CYGHWR_HAL_A2FXXX_UART16550_IIR_MODEM_STATUS VALUE_(0, 0x0) +#define CYGHWR_HAL_A2FXXX_UART16550_IIR_THRE VALUE_(0, 0x2) +#define CYGHWR_HAL_A2FXXX_UART16550_IIR_CTI VALUE_(0, 0xC) +#define CYGHWR_HAL_A2FXXX_UART16550_IIR_RXD VALUE_(0, 0x4) +#define CYGHWR_HAL_A2FXXX_UART16550_IIR_RLS VALUE_(0, 0x6) + +// Fifo control +#define CYGHWR_HAL_A2FXXX_UART16550_FCR_RX_TRIG_1BYTE VALUE_(6, 0x0) +#define CYGHWR_HAL_A2FXXX_UART16550_FCR_RX_TRIG_4BYTE VALUE_(6, 0x1) +#define CYGHWR_HAL_A2FXXX_UART16550_FCR_RX_TRIG_8BYTE VALUE_(6, 0x2) +#define CYGHWR_HAL_A2FXXX_UART16550_FCR_RX_TRIG_14BYTE VALUE_(6, 0x3) +#define CYGHWR_HAL_A2FXXX_UART16550_FCR_EN_TXRX_DY BIT_(3) +#define CYGHWR_HAL_A2FXXX_UART16550_FCR_CLEAR_TX_FIFO BIT_(2) +#define CYGHWR_HAL_A2FXXX_UART16550_FCR_CLEAR_RX_FIFO BIT_(1) +#define CYGHWR_HAL_A2FXXX_UART16550_FCR_RESERVED BIT_(0) + +// Line control +#define CYGHWR_HAL_A2FXXX_UART16550_LCR_DLAB BIT_(7) +#define CYGHWR_HAL_A2FXXX_UART16550_LCR_SB BIT_(6) +#define CYGHWR_HAL_A2FXXX_UART16550_LCR_SP BIT_(5) +#define CYGHWR_HAL_A2FXXX_UART16550_LCR_EPS BIT_(4) +#define CYGHWR_HAL_A2FXXX_UART16550_LCR_PEN BIT_(3) +#define CYGHWR_HAL_A2FXXX_UART16550_LCR_STOP_1 VALUE_(2,0) +#define CYGHWR_HAL_A2FXXX_UART16550_LCR_STOP_2 VALUE_(2,1) +#define CYGHWR_HAL_A2FXXX_UART16550_LCR_WLS_5BITS VALUE_(0, 0x0) +#define CYGHWR_HAL_A2FXXX_UART16550_LCR_WLS_6BITS VALUE_(0, 0x1) +#define CYGHWR_HAL_A2FXXX_UART16550_LCR_WLS_7BITS VALUE_(0, 0x2) +#define CYGHWR_HAL_A2FXXX_UART16550_LCR_WLS_8BITS VALUE_(0, 0x3) + +// MCR register +#define CYGHWR_HAL_A2FXXX_UART16550_MCR_LOOP BIT_(4) +#define CYGHWR_HAL_A2FXXX_UART16550_MCR_OUT2 BIT_(3) +#define CYGHWR_HAL_A2FXXX_UART16550_MCR_OUT1 BIT_(2) +#define CYGHWR_HAL_A2FXXX_UART16550_MCR_RTS BIT_(1) +#define CYGHWR_HAL_A2FXXX_UART16550_MCR_DTR BIT_(0) + +// LSR register +#define CYGHWR_HAL_A2FXXX_UART16550_LSR_FIER BIT_(6) +#define CYGHWR_HAL_A2FXXX_UART16550_LSR_TEMT BIT_(6) +#define CYGHWR_HAL_A2FXXX_UART16550_LSR_THRE BIT_(5) +#define CYGHWR_HAL_A2FXXX_UART16550_LSR_BI BIT_(4) +#define CYGHWR_HAL_A2FXXX_UART16550_LSR_FE BIT_(3) +#define CYGHWR_HAL_A2FXXX_UART16550_LSR_PE BIT_(2) +#define CYGHWR_HAL_A2FXXX_UART16550_LSR_OE BIT_(1) +#define CYGHWR_HAL_A2FXXX_UART16550_LSR_DR BIT_(0) + +// MSR +#define CYGHWR_HAL_A2FXXX_UART16550_MSR_DCD BIT_(7) +#define CYGHWR_HAL_A2FXXX_UART16550_MSR_RI BIT_(6) +#define CYGHWR_HAL_A2FXXX_UART16550_MSR_DSR BIT_(5) +#define CYGHWR_HAL_A2FXXX_UART16550_MSR_CTS BIT_(4) +#define CYGHWR_HAL_A2FXXX_UART16550_MSR_DDCD BIT_(3) +#define CYGHWR_HAL_A2FXXX_UART16550_MSR_TERI BIT_(2) +#define CYGHWR_HAL_A2FXXX_UART16550_MSR_DDSR BIT_(1) +#define CYGHWR_HAL_A2FXXX_UART16550_MSR_DCTS BIT_(0) + +__externC cyg_uint32 hal_a2fxxx_pclk0; +__externC cyg_uint32 hal_a2fxxx_pclk1; + +__externC void hal_a2fxxx_uart_setbaud(cyg_uint32 , cyg_uint32 ); + +// Consider adding rounding ? +#define CYG_HAL_CORTEXM_A2FXXX_BAUD_GENERATOR( id, baud ) \ +({ \ + cyg_uint16 _divider; \ + if( id == 0 ) \ + _divider = (hal_a2fxxx_pclk0/(baud << 4)); \ + else \ + _divider = (hal_a2fxxx_pclk1/(baud << 4)); \ + _divider; \ +}) + +// Peripherals IOs mapping +#define CYGHWR_HAL_A2FXXX_UART0_TX CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, UART0_TX, DISABLE ) +#define CYGHWR_HAL_A2FXXX_UART0_RX CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, UART0_RX, DISABLE ) + +#define CYGHWR_HAL_A2FXXX_UART1_TX CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, UART1_TX, DISABLE ) +#define CYGHWR_HAL_A2FXXX_UART1_RX CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, UART1_RX, DISABLE ) + + +//============================================================================= +// Watchdog +// +#define CYGHWR_HAL_A2FXXX_WD_VALUE 0x00 +#define CYGHWR_HAL_A2FXXX_WD_LOAD 0x04 +#define CYGHWR_HAL_A2FXXX_WD_MVRP 0x08 +#define CYGHWR_HAL_A2FXXX_WD_REFRESH 0x0C +#define CYGHWR_HAL_A2FXXX_WD_ENABLE 0x10 +#define CYGHWR_HAL_A2FXXX_WD_CTRL 0x14 +#define CYGHWR_HAL_A2FXXX_WD_STATUS 0x18 +#define CYGHWR_HAL_A2FXXX_WD_RIS 0x1C +#define CYGHWR_HAL_A2FXXX_WD_MIS 0x20 + +// Keys +#define CYGHWR_HAL_A2FXXX_WD_REFRESH_KEY 0xAC15DE42 +#define CYGHWR_HAL_A2FXXX_WD_DISABLE_KEY 0x4C6E55FA + + +//============================================================================= +// Timer +// +#define CYGHWR_HAL_A2FXXX_TIMER1 CYGHWR_HAL_A2FXXX_TIMER +#define CYGHWR_HAL_A2FXXX_TIMER2 (CYGHWR_HAL_A2FXXX_TIMER + 0x18) + +#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_VAL 0x00 +#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_LOADVAL 0x04 +#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_BGLOADVAL 0x08 +#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL 0x0c +#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_RIS 0x10 +#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_MIS 0x14 +#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_VAL_U 0x30 +#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_VAL_L 0x34 +#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_LOADVAL_U 0x38 +#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_LOADVAL_L 0x3C +#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_BGLOADVAL_U 0x40 +#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_BGLOADVAL_L 0x44 +#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_CTRL 0x48 +#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_RIS 0x4C +#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_MIS 0x50 +#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_MODE 0x54 + +// Timer control +#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL_INTEN BIT_(2) +#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL_ONESHOT BIT_(1) +#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL_EN BIT_(0) + +// Timer control 64 bits +#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_MODE_64BITS BIT_(0) + + +//============================================================================= +// MAC +// +#if defined(CYGHWR_HAL_CORTEXM_A2FXXX_A2F200) || \ + defined(CYGHWR_HAL_CORTEXM_A2FXXX_A2F500) + +#define CYGHWR_HAL_A2FXXX_MAC_CSR0 0x00 +#define CYGHWR_HAL_A2FXXX_MAC_CSR1 0x08 +#define CYGHWR_HAL_A2FXXX_MAC_CSR2 0x10 +#define CYGHWR_HAL_A2FXXX_MAC_CSR3 0x18 +#define CYGHWR_HAL_A2FXXX_MAC_CSR4 0x20 +#define CYGHWR_HAL_A2FXXX_MAC_CSR5 0x28 +#define CYGHWR_HAL_A2FXXX_MAC_CSR6 0x30 +#define CYGHWR_HAL_A2FXXX_MAC_CSR7 0x38 +#define CYGHWR_HAL_A2FXXX_MAC_CSR8 0x40 +#define CYGHWR_HAL_A2FXXX_MAC_CSR9 0x48 +#define CYGHWR_HAL_A2FXXX_MAC_CSR10 0x50 +#define CYGHWR_HAL_A2FXXX_MAC_CSR11 0x58 + +// Bus Mode Register (CSR0) +#define CYGHWR_HAL_A2FXXX_MAC_CSR0_CLEAR 0xFE000000 +#define CYGHWR_HAL_A2FXXX_MAC_CSR0_SPD BIT_(21) +#define CYGHWR_HAL_A2FXXX_MAC_CSR0_DBO BIT_(20) +#define CYGHWR_HAL_A2FXXX_MAC_CSR0_TAP(_x) VALUE_(17, (_x & 0x7)) +#define CYGHWR_HAL_A2FXXX_MAC_CSR0_PBL(_x) VALUE_(8, (_x & 0x2f)) +#define CYGHWR_HAL_A2FXXX_MAC_CSR0_BLE BIT_(7) +#define CYGHWR_HAL_A2FXXX_MAC_CSR0_DSL(_x) VALUE_(2, (_x & 0x1f)) +#define CYGHWR_HAL_A2FXXX_MAC_CSR0_BAR BIT_(1) +#define CYGHWR_HAL_A2FXXX_MAC_CSR0_SWR BIT_(0) + +// Transmit Poll Demand Register (CSR1) +#define CYGHWR_HAL_A2FXXX_MAC_CSR1_TPD(_x) VALUE_(0, _x) + +// Receive Poll Demand Register (CSR2) +#define CYGHWR_HAL_A2FXXX_MAC_CSR2_RPD(_x) VALUE_(0, _x) + +// Receive Descriptor List Base Address Register (CSR3) +#define CYGHWR_HAL_A2FXXX_MAC_CSR3_RLA(_x) VALUE_(0, _x) + +// Transmit Descriptor List Base Address Register (CSR4) +#define CYGHWR_HAL_A2FXXX_MAC_CSR4_TLA(_x) VALUE_(0, _x) + +// Status and Control Register (CSR5) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_CLOSE_TXD VALUE_(20, 0x7) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_SUSPEND VALUE_(20, 0x6) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_SETUP_PACKET VALUE_(20, 0x5) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_XFER VALUE_(20, 0x3) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_WAIT_EOT VALUE_(20, 0x2) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_FETCH_TXD VALUE_(20, 0x1) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_STOP VALUE_(20, 0x0) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_MASK VALUE_(20, 0x7) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_XFER VALUE_(17, 0x7) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_CLOSE_RXD VALUE_(17, 0x5) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_SUSPEND VALUE_(17, 0x4) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_WAIT_PACKET VALUE_(17, 0x3) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_WAIT_EOR VALUE_(17, 0x2) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_FETCH_RXD VALUE_(17, 0x1) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_STOP VALUE_(17, 0x0) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_MASK VALUE_(17, 0x7) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_NIS BIT_(16) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_AIS BIT_(15) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_ERI BIT_(14) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_GTE BIT_(11) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_ETI BIT_(10) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RPS BIT_(8) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RU BIT_(7) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RI BIT_(6) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_UNF BIT_(5) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TU BIT_(2) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TPS BIT_(1) +#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TI BIT_(0) + +// Define MAC state +#define A2FXXX_MAC_TX_STATE(_x_) CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_##_x_ +#define A2FXXX_MAC_RX_STATE(_x_) CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_##_x_ +#define A2FXXX_MAC_TX_STATE_MASK VALUE_(20, 0x7) +#define A2FXXX_MAC_RX_STATE_MASK VALUE_(17, 0x7) + +// Operation Mode Register (CSR6) +#define CYGHWR_HAL_A2FXXX_MAC_CSR6_CLEAR 0xBF9F1D20 +#define CYGHWR_HAL_A2FXXX_MAC_CSR6_RA BIT_(30) +#define CYGHWR_HAL_A2FXXX_MAC_CSR6_TTM BIT_(22) +#define CYGHWR_HAL_A2FXXX_MAC_CSR6_SF BIT_(21) +#define CYGHWR_HAL_A2FXXX_MAC_CSR6_TR(_x) VALUE_(14, _x) +#define CYGHWR_HAL_A2FXXX_MAC_CSR6_ST BIT_(13) +#define CYGHWR_HAL_A2FXXX_MAC_CSR6_FD BIT_(9) +#define CYGHWR_HAL_A2FXXX_MAC_CSR6_PM BIT_(7) +#define CYGHWR_HAL_A2FXXX_MAC_CSR6_PR BIT_(6) +#define CYGHWR_HAL_A2FXXX_MAC_CSR6_IF BIT_(4) +#define CYGHWR_HAL_A2FXXX_MAC_CSR6_PB BIT_(3) +#define CYGHWR_HAL_A2FXXX_MAC_CSR6_HO BIT_(2) +#define CYGHWR_HAL_A2FXXX_MAC_CSR6_SR BIT_(1) +#define CYGHWR_HAL_A2FXXX_MAC_CSR6_HP BIT_(0) + +// Interrupt Enable Register (CSR7) +#define CYGHWR_HAL_A2FXXX_MAC_CSR7_NIE BIT_(16) +#define CYGHWR_HAL_A2FXXX_MAC_CSR7_AIE BIT_(15) +#define CYGHWR_HAL_A2FXXX_MAC_CSR7_ERE BIT_(14) +#define CYGHWR_HAL_A2FXXX_MAC_CSR7_GTE BIT_(11) +#define CYGHWR_HAL_A2FXXX_MAC_CSR7_ETE BIT_(10) +#define CYGHWR_HAL_A2FXXX_MAC_CSR7_RSE BIT_(8) +#define CYGHWR_HAL_A2FXXX_MAC_CSR7_RUE BIT_(7) +#define CYGHWR_HAL_A2FXXX_MAC_CSR7_RIE BIT_(6) +#define CYGHWR_HAL_A2FXXX_MAC_CSR7_UNE BIT_(5) +#define CYGHWR_HAL_A2FXXX_MAC_CSR7_TUE BIT_(2) +#define CYGHWR_HAL_A2FXXX_MAC_CSR7_TSE BIT_(1) +#define CYGHWR_HAL_A2FXXX_MAC_CSR7_TIE BIT_(0) + +// Missed Frames and Overflow Counter Register (CSR8) +#define CYGHWR_HAL_A2FXXX_MAC_CSR8_OCO BIT_(28) +#define CYGHWR_HAL_A2FXXX_MAC_CSR8_MFO BIT_(16) + +// RMII Management Interface Register (CSR9) +#define CYGHWR_HAL_A2FXXX_MAC_CSR9_MDI BIT_(19) +#define CYGHWR_HAL_A2FXXX_MAC_CSR9_MDEN BIT_(18) +#define CYGHWR_HAL_A2FXXX_MAC_CSR9_MDO BIT_(17) +#define CYGHWR_HAL_A2FXXX_MAC_CSR9_MDC BIT_(16) + +// General-Purpose Timer and Interrupt Mitigation Control Register (CSR11) +#define CYGHWR_HAL_A2FXXX_MAC_CSR11_CS BIT_(31) +#define CYGHWR_HAL_A2FXXX_MAC_CSR11_TT(_x) VALUE_(27, (_x & 0xf)) +#define CYGHWR_HAL_A2FXXX_MAC_CSR11_NTP(_x) VALUE_(24, (_x & 0x7)) +#define CYGHWR_HAL_A2FXXX_MAC_CSR11_RT(_x) VALUE_(20, (_x & 0xf)) +#define CYGHWR_HAL_A2FXXX_MAC_CSR11_NRP(_x) VALUE_(17, (_x & 0x7)) +#define CYGHWR_HAL_A2FXXX_MAC_CSR11_CON BIT_(16) +#define CYGHWR_HAL_A2FXXX_MAC_CSR11_TIM(_x) VALUE_(0, _x) + +// Receive Descriptors (RDESx) +#define CYGHWR_HAL_A2FXXX_MAC_RDES0_OWN BIT_(31) +#define CYGHWR_HAL_A2FXXX_MAC_RDES0_FF BIT_(30) +#define CYGHWR_HAL_A2FXXX_MAC_RDES0_FL(_x) VALUE_(16, _x) +#define CYGHWR_HAL_A2FXXX_MAC_RDES0_ES BIT_(15) +#define CYGHWR_HAL_A2FXXX_MAC_RDES0_DE BIT_(14) +#define CYGHWR_HAL_A2FXXX_MAC_RDES0_RF BIT_(11) +#define CYGHWR_HAL_A2FXXX_MAC_RDES0_MF BIT_(10) +#define CYGHWR_HAL_A2FXXX_MAC_RDES0_FS BIT_(9) +#define CYGHWR_HAL_A2FXXX_MAC_RDES0_LS BIT_(8) +#define CYGHWR_HAL_A2FXXX_MAC_RDES0_TL BIT_(7) +#define CYGHWR_HAL_A2FXXX_MAC_RDES0_CS BIT_(6) +#define CYGHWR_HAL_A2FXXX_MAC_RDES0_FT BIT_(5) +#define CYGHWR_HAL_A2FXXX_MAC_RDES0_RE BIT_(3) +#define CYGHWR_HAL_A2FXXX_MAC_RDES0_DB BIT_(2) +#define CYGHWR_HAL_A2FXXX_MAC_RDES0_CE BIT_(1) +#define CYGHWR_HAL_A2FXXX_MAC_RDES0_ZERO BIT_(0) + +#define CYGHWR_HAL_A2FXXX_MAC_RDES1_RER BIT_(25) +#define CYGHWR_HAL_A2FXXX_MAC_RDES1_RCH BIT_(24) +#define CYGHWR_HAL_A2FXXX_MAC_RDES1_RBS2(_x) VALUE_(11, _x) +#define CYGHWR_HAL_A2FXXX_MAC_RDES1_RBS1(_x) VALUE_(0, _x) + +// Receive Descriptors (TDESx) +#define CYGHWR_HAL_A2FXXX_MAC_TDES0_OWN BIT_(31) +#define CYGHWR_HAL_A2FXXX_MAC_TDES0_ES BIT_(15) +#define CYGHWR_HAL_A2FXXX_MAC_TDES0_LO BIT_(11) +#define CYGHWR_HAL_A2FXXX_MAC_TDES0_NC BIT_(10) +#define CYGHWR_HAL_A2FXXX_MAC_TDES0_LC BIT_(9) +#define CYGHWR_HAL_A2FXXX_MAC_TDES0_EC BIT_(8) +#define CYGHWR_HAL_A2FXXX_MAC_TDES0_CC(_x) VALUE_(3, _x) +#define CYGHWR_HAL_A2FXXX_MAC_TDES0_UF BIT_(1) +#define CYGHWR_HAL_A2FXXX_MAC_TDES0_DE BIT_(0) + +#define CYGHWR_HAL_A2FXXX_MAC_TDES1_IC BIT_(31) +#define CYGHWR_HAL_A2FXXX_MAC_TDES1_LS BIT_(30) +#define CYGHWR_HAL_A2FXXX_MAC_TDES1_FS BIT_(29) +#define CYGHWR_HAL_A2FXXX_MAC_TDES1_FT1 BIT_(28) +#define CYGHWR_HAL_A2FXXX_MAC_TDES1_SET BIT_(27) +#define CYGHWR_HAL_A2FXXX_MAC_TDES1_AC BIT_(26) +#define CYGHWR_HAL_A2FXXX_MAC_TDES1_TER BIT_(25) +#define CYGHWR_HAL_A2FXXX_MAC_TDES1_TCH BIT_(24) +#define CYGHWR_HAL_A2FXXX_MAC_TDES1_DPD BIT_(23) +#define CYGHWR_HAL_A2FXXX_MAC_TDES1_FT0 BIT_(22) +#define CYGHWR_HAL_A2FXXX_MAC_TDES1_TBS2(_x) VALUE_(11, _x) +#define CYGHWR_HAL_A2FXXX_MAC_TDES1_TBS1(_x) VALUE_(0, _x) + +#define CYGHWR_HAL_A2FXXX_MAC0_MDIO CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_MDIO, DISABLE ) +#define CYGHWR_HAL_A2FXXX_MAC0_MDC CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_MDC, DISABLE ) +#define CYGHWR_HAL_A2FXXX_MAC0_TXD0 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_TXD0, DISABLE ) +#define CYGHWR_HAL_A2FXXX_MAC0_TXD1 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_TXD1, DISABLE ) +#define CYGHWR_HAL_A2FXXX_MAC0_RXD0 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_RXD0, DISABLE ) +#define CYGHWR_HAL_A2FXXX_MAC0_RXD1 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_RXD1, DISABLE ) +#define CYGHWR_HAL_A2FXXX_MAC0_TXEN CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_TXEN, DISABLE ) +#define CYGHWR_HAL_A2FXXX_MAC0_CRSDV CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_CRSDV, DISABLE ) +#define CYGHWR_HAL_A2FXXX_MAC0_RXER CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_RXER, DISABLE ) + +#endif + +//============================================================================= +// Spare page + +#define CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_KEY 0x081C +#define CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_VERSION 0x0840 +#define CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_1_3_FCLK 0x162C +#define CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_2_x_FCLK 0x1EAC + +// System boot key value +#define CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_KEY_VALUE 0x4C544341 + +// System boot version +#define CYGHWR_HAL_A2FXXX_SYSBOOT_VERSION(_x, _y, _z) ((_x << 16) | (_y << 8) | (_z)) + +#define CYGHWR_HAL_A2FXXX_GET_SYSBOOT_VERSION() \ +({ \ + cyg_uint32 _i; \ + cyg_uint32 base = CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES; \ + HAL_READ_UINT32( base + CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_VERSION, _i); \ + _i; \ +}) + +#define CYGHWR_HAL_A2FXXX_GET_SYSBOOT_KEY() \ +({ \ + cyg_uint32 _i; \ + cyg_uint32 base = CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES; \ + HAL_READ_UINT32( base + CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_KEY, _i); \ + _i; \ +}) + +#define CYGHWR_HAL_A2FXXX_GET_SYSBOOT_1_3_FCLK() \ +({ \ + cyg_uint32 _i; \ + cyg_uint32 base = CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES; \ + HAL_READ_UINT32( base + CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_1_3_FCLK, _i); \ + _i; \ +}) + +#define CYGHWR_HAL_A2FXXX_GET_SYSBOOT_2_0_FCLK() \ +({ \ + cyg_uint32 _i; \ + cyg_uint32 base = CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES; \ + HAL_READ_UINT32( base + CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_2_x_FCLK, _i); \ + _i; \ +}) + +#define CYGHWR_HAL_A2FXXX_BITSET 0x1 +#define CYGHWR_HAL_A2FXXX_BITCLEAR 0x0 +// +//----------------------------------------------------------------------------- +// end of var_io.h +#endif // CYGONCE_HAL_VAR_IO_H
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/var/current/include/variant.inc @@ -0,0 +1,54 @@ +/*========================================================================== +// +// variant.inc +// +// Variant specific asm definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal_cortexm_a2fxxx.h> + +//========================================================================== +// EOF variant.inc +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/var/current/src/a2fxxx_misc.c @@ -0,0 +1,1214 @@ +/*========================================================================== +// +// a2f_misc.c +// +// Cortex-M Actel A2F HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Contributors: +// Date: 2011-02-03 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_a2fxxx.h> + +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header +#include <cyg/hal/hal_if.h> // HAL header + + +//========================================================================== +// Clock Initialization values + +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK + +#define CLKx_SRC_CLKA 0 +#define CLKx_SRC_CLKB 1 +#define CLKx_SRC_CLKC 2 +#define CLKx_SRC_CLKGA 3 +#define CLKx_SRC_CLKGB 4 +#define CLKx_SRC_CLKGC 5 +#define CLKx_SRC_CLKGINT 6 + +#define CLKx_SRC_UIN 0 +#define CLKx_SRC_DIP 1 +#define CLKx_SRC_UIP 4 +#define CLKx_SRC_GLxINT 5 +#define CLKx_SRC_RCOSC 2 +#define CLKx_SRC_MOSC 6 +#define CLKx_SRC_32KOSC 6 + +// Select source of CLKA + +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC_AUIN +# define CLKA_SRC_SEL CLKx_SRC_UIN +#elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC_AUIP) +# define CLKA_SRC_SEL CLKx_SRC_UIP +#elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC_ADIP) +# define CLKA_SRC_SEL CLKx_SRC_DIP +#elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC_GLAINT) +# define CLKA_SRC_SEL CLKx_SRC_GLxINT +#elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC_RCOSC) +# define CLKA_SRC_SEL CLKx_SRC_RCOSC +#else +# define CLKA_SRC_SEL CLKx_SRC_MOSC +#endif + +// Select source of CLKB + +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKB +# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC_BUIN +# define CLKB_SRC_SEL CLKx_SRC_UIN +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC_BUIP) +# define CLKB_SRC_SEL CLKx_SRC_UIP +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC_BDIP) +# define CLKB_SRC_SEL CLKx_SRC_DIP +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC_GLBINT) +# define CLKB_SRC_SEL CLKx_SRC_GLxINT +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC_RCOSC) +# define CLKB_SRC_SEL CLKx_SRC_RCOSC +# else +# define CLKB_SRC_SEL CLKx_SRC_MOSC +# endif +#endif + +// Select source of CLKC + +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKC +# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC_CUIN +# define CLKC_SRC_SEL CLKx_SRC_UIN +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC_CUIP) +# define CLKC_SRC_SEL CLKx_SRC_UIP +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC_CDIP) +# define CLKC_SRC_SEL CLKx_SRC_DIP +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC_GLCINT) +# define CLKC_SRC_SEL CLKx_SRC_GLxINT +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC_RCOSC) +# define CLKC_SRC_SEL CLKx_SRC_RCOSC +# else +# define CLKC_SRC_SEL CLKx_SRC_32KOSC +# endif +#endif + +// Select source of CLKGA + +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA +# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC_CLKA +# define CLKGA_SRC_SEL 1 +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC_PLL_VCO0) +# define CLKGA_SRC_SEL 4 +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC_PLL_VCO90) +# define CLKGA_SRC_SEL 5 +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC_PLL_VCO180) +# define CLKGA_SRC_SEL 6 +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC_PLL_VCO270) +# define CLKGA_SRC_SEL 7 +# else +# define CLKGA_SRC_SEL 2 +# endif +#endif + +// Select source of CLKGB + +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB +# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC_CLKB +# define CLKGB_SRC_SEL 1 +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC_CLKGA +# define CLKGB_SRC_SEL 3 +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC_PLL_VCO0) +# define CLKGB_SRC_SEL 4 +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC_PLL_VCO90) +# define CLKGB_SRC_SEL 5 +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC_PLL_VCO180) +# define CLKGB_SRC_SEL 6 +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC_PLL_VCO270) +# define CLKGB_SRC_SEL 7 +# else +# define CLKGB_SRC_SEL 2 +# endif +#endif + +// Select source of CLKGC + +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC +# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_CLKC +# define CLKGC_SRC_SEL 1 +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_CLKGA) +# define CLKGC_SRC_SEL 3 +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_PLL_VCO0) +# define CLKGC_SRC_SEL 4 +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_PLL_VCO90) +# define CLKGC_SRC_SEL 5 +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_PLL_VCO180) +# define CLKGC_SRC_SEL 6 +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_PLL_VCO270) +# define CLKGC_SRC_SEL 7 +# else +# define CLKGC_SRC_SEL 2 +# endif +#endif + +#if CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_DIV == 1 +# define PCLK0DIV 0 +#elif CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_DIV == 2 +# define PCLK0DIV 1 +#else +# define PCLK0DIV 2 +#endif + +#if CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_DIV == 1 +# define PCLK1DIV 0 +#elif CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_DIV == 2 +# define PCLK1DIV 1 +#else +# define PCLK1DIV 2 +#endif + +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_ACE_CLK +# if CYGHWR_HAL_CORTEXM_A2FXXX_ACLK_DIV == 1 +# define ACLKDIV 0 +# elif CYGHWR_HAL_CORTEXM_A2FXXX_ACLK_DIV == 2 +# define ACLKDIV 1 +# else +# define ACLKDIV 2 +# endif +#endif + +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_PLL +# if CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ < 43750000 +# define PLL_RANGE 0 +# elif CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ < 87500000 +# define PLL_RANGE 1 +# elif CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ < 175000000 +# define PLL_RANGE 2 +# else +# define PLL_RANGE 3 +# endif +#endif + +#define OXDIV_CLEAR 0x1F +#define OXMUX_CLEAR 0x07 +#define DLYX_CLEAR 0x1F +#define DIV_CLEAR 0x03 + +#endif // CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK + +//========================================================================== +// IO settings + +#ifdef CYGPKG_HAL_CORTEXM_A2FXXX_IO + +# if defined(CYGHWR_HAL_CORTEXM_A2FXXX_IO_WEST_BANK_LVCMOS_3V3) +# define IO_WEST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTWEST(LVCMOS_3V3) +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_IO_WEST_BANK_LVCMOS_2V5) +# define IO_WEST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTWEST(LVCMOS_2V5) +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_IO_WEST_BANK_LVCMOS_1V8) +# define IO_WEST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTWEST(LVCMOS_1V8) +# else +# define IO_WEST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTWEST(LVCMOS_1V5) +# endif + +# if defined(CYGHWR_HAL_CORTEXM_A2FXXX_IO_EAST_BANK_LVCMOS_3V3) +# define IO_EAST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTEAST(LVCMOS_3V3) +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_IO_EAST_BANK_LVCMOS_2V5) +# define IO_EAST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTEAST(LVCMOS_2V5) +# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_IO_EAST_BANK_LVCMOS_1V8) +# define IO_EAST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTEAST(LVCMOS_1V8) +# else +# define IO_EAST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTEAST(LVCMOS_1V5) +# endif + +#endif // CYGPKG_HAL_CORTEXM_A2FXXX_IO + + +#ifdef CYGSEM_HAL_CORTEXM_A2FXXX_CLOCK_CHATTER +# define A2FXXX_CLOCK_TRACE(args...) diag_printf(args) +#else +# define A2FXXX_CLOCK_TRACE(args...) /* NOOP */ +#endif + + +//========================================================================== +// Clock frequencies +// +// These are set to the frequencies of the various system clocks. + +cyg_uint32 hal_a2fxxx_pclk0; // Peripheral clock (connected to APB_0) +cyg_uint32 hal_a2fxxx_pclk1; // Peripheral clock (connected to APB_1) +cyg_uint32 hal_a2fxxx_aclk; // Analog Peripheral clock (ADC /DAC etc..) +cyg_uint32 hal_a2fxxx_pclk_fpga; // FPGA clock + +cyg_uint32 hal_a2fxxx_glb; // Global Clock B +cyg_uint32 hal_a2fxxx_glc; // Global Clock C + +cyg_uint32 hal_cortexm_systick_clock; // NGMUx output or FCLK or SysTick clock +cyg_uint32 hal_a2fxxx_fclk; // FCLK + + +//========================================================================== +// Local prototypes + +static void hal_a2fxxx_clk_network_chatter( cyg_uint8 ); + +static cyg_uint8 hal_start_clocks( void ); +static cyg_uint8 hal_a2fxxx_get_system_boot_clk( void ); + +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK +static void hal_a2fxxx_set_clk_network( void ); +static void hal_a2fxxx_set_envm_timing( void ); +static void hal_a2fxxx_set_clkx( cyg_uint8 x, cyg_uint8 src ); +static void hal_a2fxxx_set_clkgx( cyg_uint8 x ); +static void hal_a2fxxx_set_clkgx_default( cyg_uint8 x ); +static void hal_a2fxxx_set_ngmux( cyg_uint8 ); +static cyg_uint8 hal_a2fxxx_get_ngmux( void ); + +# if defined(CYGHWR_HAL_CORTEXM_A2FXXX_PLL) +static inline void hal_a2fxxx_set_pll( void ); +# endif +#endif + + +//========================================================================== + +void +hal_variant_init( void ) +{ +#if !defined(CYG_HAL_STARTUP_RAM) + cyg_uint8 sysboot_miss; +#endif + cyg_uint32 base = CYGHWR_HAL_A2FXXX_WD; + + // Disable Watch-dog + HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_WD_ENABLE, + CYGHWR_HAL_A2FXXX_WD_DISABLE_KEY); + +#if !defined(CYG_HAL_STARTUP_RAM) + sysboot_miss = hal_start_clocks(); +#endif + + // Release GPIO + CYGHWR_HAL_A2FXXX_PERIPH_RELEASE( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(GPIO) ); + + // Setup IO banks +#ifdef CYGPKG_HAL_CORTEXM_A2FXXX_IO + HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR, (IO_WEST_BANK | IO_EAST_BANK) ); +#endif + + // Reset UART0 +#if CYGINT_HAL_A2FXXX_UART0>0 + CYGHWR_HAL_A2FXXX_PERIPH_RELEASE( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(UART0) ); +#endif + + // Reset UART1 +#if CYGINT_HAL_A2FXXX_UART1>0 + CYGHWR_HAL_A2FXXX_PERIPH_RELEASE( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(UART1) ); +#endif + +#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + hal_if_init(); +#endif + +#if !defined(CYG_HAL_STARTUP_RAM) + hal_a2fxxx_clk_network_chatter( sysboot_miss ); +#endif +} + +//========================================================================== +// Setup up system clocks +// +// Set up clocks from configuration. In the future this should be extended so +// that clock rates can be changed at runtime. + +static cyg_uint8 +hal_start_clocks( void ) +{ + if( ! hal_a2fxxx_get_system_boot_clk( ) ) + return 0; + + // + // User has chosen to re-configure the clock network and + // overwrite the settings provided by the system boot + // +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK + hal_a2fxxx_set_clk_network( ); + + // Adjust the ENVM timing according to the core clock + // frequency + hal_a2fxxx_set_envm_timing( ); +#endif + + return 1; +} + + +//========================================================================== +// Read clock configuration as setup by the system boot + +static cyg_uint8 +hal_a2fxxx_get_system_boot_clk( void ) +{ + cyg_uint32 sysboot_key, sysboot_ver, clk_cr, clkga0; + + sysboot_ver = CYGHWR_HAL_A2FXXX_GET_SYSBOOT_VERSION(); + sysboot_key = CYGHWR_HAL_A2FXXX_GET_SYSBOOT_KEY(); + + // Verify that the system boot is present, if not we must give up? + if( CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_KEY_VALUE + != sysboot_key ) + return 0; + + // Read the MSS CLGA0 frequency value. Address varies with system boot + // version + if ( sysboot_ver < CYGHWR_HAL_A2FXXX_SYSBOOT_VERSION(2, 0, 0) ) { + clkga0 = CYGHWR_HAL_A2FXXX_GET_SYSBOOT_1_3_FCLK(); + } + else { + clkga0 = CYGHWR_HAL_A2FXXX_GET_SYSBOOT_2_0_FCLK(); + } + + // Compute the BUS and fabric clock frequency + hal_cortexm_systick_clock = clkga0; + + HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR, clk_cr); + + hal_a2fxxx_pclk0 = + clkga0 >> CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GET_PCLK0DIV( clk_cr ); + hal_a2fxxx_pclk1 = + clkga0 >> CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GET_PCLK1DIV( clk_cr ); + hal_a2fxxx_pclk_fpga = + clkga0 >> CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GET_GLBDIV( clk_cr ); + + return 1; +} + + +//========================================================================== +// Chatter function + +static void +hal_a2fxxx_clk_network_chatter( cyg_uint8 hal_clk_network_chatter ) +{ + if ( hal_clk_network_chatter == 0 ) + diag_printf("Actel System Boot Missing\n Clock network configuration failed!!\n"); + + A2FXXX_CLOCK_TRACE("Device clock network configuration:\n"); + A2FXXX_CLOCK_TRACE("Global Clock A (Systick): %d [Hz]\n", + hal_cortexm_systick_clock); + A2FXXX_CLOCK_TRACE("PCLK0: %d [Hz]\n", hal_a2fxxx_pclk0); + A2FXXX_CLOCK_TRACE("PCLK1: %d [Hz]\n", hal_a2fxxx_pclk1); +} + + +//========================================================================== +// Setup device clock network + +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK + +static void +hal_a2fxxx_set_clk_network( void ) +{ + cyg_uint32 mss_ccc_mux; + cyg_uint32 mss_clk_cr; + cyg_uint8 ngmux; +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_PLL + cyg_bool pll = false; +#endif +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKA + cyg_bool clka = false; +#endif +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKC + cyg_bool clkc = false; +#endif +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA + cyg_bool clkga = false; +#endif +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC + cyg_bool clkgc = false; +#endif + + // Find out which CLKGx is currently used as FLCK + ngmux = hal_a2fxxx_get_ngmux( ); + + // + // Start by configuring NGMUX. In the following case, if + // the current NGMUX output is already CLKGA, first move + // to CLKGC to keep a stable ground otherwise go ahead and + // configure CLKGA. + // +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_CLKGA + if( ngmux == CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLA ) + { + // Setup CLKGC to use the On-Chip RC oscillator and move + // the MSS clock to CLKGC. No division factor is applied + // therefore FCLK = 100MHz + + // CLKC = RCOSC + hal_a2fxxx_set_clkx( CLKx_SRC_CLKC, CLKx_SRC_RCOSC ); + + // CLKGC = CLKC + hal_a2fxxx_set_clkgx_default( CLKx_SRC_CLKGC ); + + // FCLK = CLKGC + hal_a2fxxx_set_ngmux( CLKx_SRC_CLKGC ); + } + else { + HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux); + mss_ccc_mux &= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OCMUX(OXMUX_CLEAR); + mss_ccc_mux = mss_ccc_mux >> 19; + + // Make sure PLL is bypassed. + if ( mss_ccc_mux != 1 ){ + hal_a2fxxx_set_clkx( CLKx_SRC_CLKC, CLKx_SRC_RCOSC ); + hal_a2fxxx_set_clkgx_default( CLKx_SRC_CLKGC ); + } + } + + // Now we can configure CLKGA as specified by the + // user. Check is PLL should be configured. + hal_a2fxxx_set_clkx( CLKx_SRC_CLKA, CLKA_SRC_SEL ); + +# if defined(CYGHWR_HAL_CORTEXM_A2FXXX_PLL) + hal_a2fxxx_set_pll( ); + pll = true; +# endif + + // Move to CLKGA + hal_a2fxxx_set_clkgx( CLKx_SRC_CLKGA ); + clka = clkga = true; + hal_a2fxxx_set_ngmux( CLKx_SRC_CLKGA ); + +#endif // CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_CLKGA + + + // + // In the following case, NGMUX is configured to use CLKGC. + // This can be tricky as CLKGC can be routed from CLKGA... + // +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_CLKGC + + HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux); + mss_ccc_mux &= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OCMUX(OXMUX_CLEAR); + mss_ccc_mux = mss_ccc_mux >> 19; + + // If CLKGC is not routed form CLKC or if CLKGC is not used + // as NGMUX output, proceed to configure CLKGC = CLKC + if( ((ngmux == CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLC) && (mss_ccc_mux != 1)) || + (ngmux == CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLA) ) + { + + // Set CLKC source, use on-chip oscillator as default + // value +# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_CLKC + hal_a2fxxx_set_clkx( CLKx_SRC_CLKC, CLKC_SRC_SEL ); + clkc = true; +# else + hal_a2fxxx_set_clkx( CLKx_SRC_CLKC, CLKx_SRC_RCOSC ); +# endif + + // Set CLKGC = CLKC + hal_a2fxxx_set_clkgx_default( CLKx_SRC_CLKGC ); + + // Set NGMUX = CLKGC + hal_a2fxxx_set_ngmux( CLKx_SRC_CLKGC ); + + // Configure PLL input if in use +# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_PLL + hal_a2fxxx_set_clkx( CLKx_SRC_CLKA, CLKA_SRC_SEL ); + clka = true; +# endif + + } + else { + + // Set CLKA source, use on-chip oscillator as default + // value +# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKA + hal_a2fxxx_set_clkx( CLKx_SRC_CLKA, CLKA_SRC_SEL ); + clka = true; +# else + hal_a2fxxx_set_clkx( CLKx_SRC_CLKA, CLKx_SRC_RCOSC ); +# endif + +# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_CLKC + // CLKGA = CLKA + hal_a2fxxx_set_clkgx_default( CLKx_SRC_CLKGA ); + + // Move NGMUX = CLKGA + hal_a2fxxx_set_ngmux( CLKx_SRC_CLKGA ); + + // Now we can Configure CLKC + hal_a2fxxx_set_clkx( CLKx_SRC_CLKC, CLKC_SRC_SEL ); +# endif + + } + +# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_PLL + hal_a2fxxx_set_pll( ); + pll = true; +# endif + + clkgc = true; + hal_a2fxxx_set_clkgx( CLKx_SRC_CLKGC ); + hal_a2fxxx_set_ngmux( CLKx_SRC_CLKGC ); + +#endif // CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_CLKGC + + + // Configure CLKA +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKA + if ( clka == false ){ + hal_a2fxxx_set_clkx( CLKx_SRC_CLKA, CLKA_SRC_SEL ); + } +#endif + + // Configure the PLL +#if defined(CYGHWR_HAL_CORTEXM_A2FXXX_PLL) + if ( pll == false ){ + hal_a2fxxx_set_pll( ); + } +#endif + + // Configure CLKB +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKB + hal_a2fxxx_set_clkx( CLKx_SRC_CLKB, CLKB_SRC_SEL ); +#endif + + // Configure CLKC +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKC + if ( clkc == false ){ + hal_a2fxxx_set_clkx( CLKx_SRC_CLKC, CLKC_SRC_SEL ); + } +#endif + + // Configure CLKGA +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA + if ( clkga == false ){ + hal_a2fxxx_set_clkgx( CLKx_SRC_CLKA ); + } +#endif + + // Configure CLKGB +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB + hal_a2fxxx_set_clkgx( CLKx_SRC_CLKB ); +#endif + + // Configure CLKGC +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC + if ( clkgc == false ){ + hal_a2fxxx_set_clkgx( CLKx_SRC_CLKC ); + } +#endif + + // Now, configure all MSS clock dividers + // + HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux); + HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR, mss_clk_cr); + +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_ACE_CLK + mss_clk_cr &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_ACLKDIV(DIV_CLEAR) ); + mss_clk_cr |= ( CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_ACLKDIV(ACLKDIV) ); +#endif + + mss_clk_cr &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_PCLK1DIV(DIV_CLEAR) | + CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_PCLK0DIV(DIV_CLEAR) ); + + mss_clk_cr |= ( CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_PCLK1DIV(PCLK1DIV) | + CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_PCLK0DIV(PCLK0DIV) ); + + // Record the different clock frequencies + hal_cortexm_systick_clock = CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ; + hal_a2fxxx_fclk = CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ; + hal_a2fxxx_pclk0 = CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_FREQ; + hal_a2fxxx_pclk1 = CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_FREQ; + +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK + hal_a2fxxx_pclk_fpga = CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_FREQ; +#endif + + // Configure the MAC clock +#if defined(CYGHWR_HAL_CORTEXM_A2FXXX_MAC_CLK) && \ + defined(CYGHWR_HAL_CORTEXM_A2FXXX_MAC_SRC_CLKGC) + + mss_clk_cr |= CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_RMIICLKSEL; + +#elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_MAC_CLK) && \ + defined(CYGHWR_HAL_CORTEXM_A2FXXX_MAC_SRC_EXTERNAL) + + mss_clk_cr &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_RMIICLKSEL; + +#endif + + HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR, + mss_clk_cr); + + // PLL is disable if not in used +#if !defined(CYGHWR_HAL_CORTEXM_A2FXXX_PLL) + HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR, 0x0); +#endif +} + + +//========================================================================== +// Get / Set NGMUX settings + +static cyg_uint8 +hal_a2fxxx_get_ngmux( void ) +{ + cyg_uint32 mss_ccc_mux; + cyg_uint8 ngmux_setting; + HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux); + + mss_ccc_mux = mss_ccc_mux >> 24; + switch( mss_ccc_mux & 0xf ){ + case 0: + case 2: + case 4: + case 6: + case 12: + ngmux_setting = CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLA; + break; + case 1: + case 3: + case 8: + case 10: + case 13: + ngmux_setting = CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLC; + break; + case 5: + case 7: + case 9: + case 11: + case 14: + ngmux_setting = CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLINT; + break; + default: + ngmux_setting = CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GND; + break; + } + + return ngmux_setting; +} + + +static void +hal_a2fxxx_set_ngmux( cyg_uint8 x ) +{ + cyg_uint32 mss_ccc_mux; + HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux); + + // Clear bits + mss_ccc_mux &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXSEL(0x3) | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXCFG(0x3) ); + + if( x == CLKx_SRC_CLKGA ){ + mss_ccc_mux |= ( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXSEL(0) | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXCFG(0) ); + } + else if (x == CLKx_SRC_CLKGC ){ + mss_ccc_mux |= ( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXSEL(1) | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXCFG(0) ); + } + else{ + mss_ccc_mux |= ( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXSEL(2) | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXCFG(3) ); + } + + HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux); +} + + +//========================================================================== +// Setup PLL + +#if defined(CYGHWR_HAL_CORTEXM_A2FXXX_PLL) +static inline void +hal_a2fxxx_set_pll( void ) +{ + cyg_uint32 x = + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FINDIV((CYGHWR_HAL_CORTEXM_A2FXXX_PLL_DIV-1)) | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FBDIV((CYGHWR_HAL_CORTEXM_A2FXXX_PLL_MULT-1)) | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FBSEL(1) | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FBDLY(CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FB_DELAY) | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_VCOSEL0 | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_VCOSEL2_1(PLL_RANGE) | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_PLLEN; + + HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR, x); + + // Wait PLL lock + do { + HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_SR, x); + } while( (x & CYGHWR_HAL_A2FXXX_SC_MSS_CCC_SR_PLL_LOCK_SYNC) == 0); +} +#endif + + +//========================================================================== +// Setup CLKA, CLKB or CLKC input clock + +static void +hal_a2fxxx_set_clkx( cyg_uint8 x, cyg_uint8 src ) +{ + cyg_uint32 mss_ccc_mux; + HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux); + if( x == CLKx_SRC_CLKA ){ + mss_ccc_mux &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_DYNASEL | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_RXASEL | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_STATASEL ); + mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_CLKA_SEL (src); + } + else if (x == CLKx_SRC_CLKB ){ + mss_ccc_mux &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_DYNBSEL | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_RXBSEL | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_STATBSEL ); + mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_CLKB_SEL (src); + } + else{ + mss_ccc_mux &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_DYNCSEL | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_RXCSEL | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_STATCSEL ); + mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_CLKC_SEL (src); + } + HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux); +} + + +//========================================================================== +// Setup CLKGA, CLKGB or CLKGC output clock + +static void +hal_a2fxxx_set_clkgx( cyg_uint8 x ) +{ + cyg_uint32 mss_ccc_mux; + cyg_uint32 mss_ccc_dly; + cyg_uint32 mss_ccc_div; + cyg_uint8 div10; + cyg_uint8 div; + HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux); + HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR, mss_ccc_dly); + HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR, mss_ccc_div); + + if( x == CLKx_SRC_CLKGA ){ +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA + // Clear bits + mss_ccc_div &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIV(OXDIV_CLEAR) | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIVHALF ); + mss_ccc_dly &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA(DLYX_CLEAR); + mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OAMUX(OXMUX_CLEAR); + mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSA; + // Compute divider + div10 = CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV10; + div = (cyg_uint8) CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV; + if( div10 % 10 ){ + div += 1; + mss_ccc_div |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIVHALF; + } + else { + div -= 1; + } + // CLKA = CLGA, bypass MUX + if (div == 0 && CLKGA_SRC_SEL == 1) { + mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSA; + } + else { + mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OAMUX(CLKGA_SRC_SEL); + mss_ccc_div |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIV(div); + } + mss_ccc_dly |= + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DELAY); +#endif + } + if ( x == CLKx_SRC_CLKGB ){ +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB + // Clear bits + mss_ccc_div &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIV(OXDIV_CLEAR) | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIVHALF ); + mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OBMUX(OXMUX_CLEAR); + mss_ccc_dly &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYB(DLYX_CLEAR); + mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSB; + // Compute divider + div10 = CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV10; + div = (cyg_uint8) CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV; + if( div10 % 10 ){ + div += 1; + mss_ccc_div |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIVHALF; + } + else { + div -= 1; + } + // CLKB = CLGB, bypass MUX + if (div == 0 && CLKGB_SRC_SEL == 1) { + mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSB; + } + else { + mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OBMUX(CLKGB_SRC_SEL); + mss_ccc_div |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIV(div); + mss_ccc_dly |= + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYB(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DELAY); + } +#endif + } + if ( x == CLKx_SRC_CLKGC ){ +#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC + // Clear bits + mss_ccc_div &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIV(OXDIV_CLEAR) | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIVHALF ); + mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OCMUX(OXMUX_CLEAR); + mss_ccc_dly &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYC(DLYX_CLEAR); + mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSC; + // Compute divider + div10 = CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV10; + div = (cyg_uint8) CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV; + if( div10 % 10 ){ + div += 1; + mss_ccc_div |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIVHALF; + } + else { + div -= 1; + } + // CLKC = CLGC, bypass MUX + if (div == 0 && CLKGC_SRC_SEL == 1) { + mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSC; + } + else { + mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OCMUX(CLKGC_SRC_SEL); + mss_ccc_div |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIV(div); + } + mss_ccc_dly |= + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYC(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DELAY); +#endif + } + HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR, mss_ccc_div); + HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR, mss_ccc_dly); + HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux); +} + +//========================================================================== +// Setup CLKGA CLKGC output clock + +static void +hal_a2fxxx_set_clkgx_default( cyg_uint8 x ) +{ + cyg_uint32 mss_ccc_mux; + cyg_uint32 mss_ccc_dly; + cyg_uint32 mss_ccc_div; + + HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux); + HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR, mss_ccc_dly); + HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR, mss_ccc_div); + + if( x == CLKx_SRC_CLKGA ){ + // Clear bits + mss_ccc_div &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIV(OXDIV_CLEAR) | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIVHALF ); + mss_ccc_dly &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA(DLYX_CLEAR); + mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OAMUX(OXMUX_CLEAR); + // CLKGA = CLKA, Division factor = 1 and minimum delay of 535ps + mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSA; + mss_ccc_dly |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA(0); + } + if ( x == CLKx_SRC_CLKGC ){ + // Clear bits + mss_ccc_div &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIV(OXDIV_CLEAR) | + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIVHALF ); + mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OCMUX(OXMUX_CLEAR); + mss_ccc_dly &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYC(DLYX_CLEAR); + // CLKGC = CLKC, Division factor = 1 and minimum delay of 535ps + mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSC; + mss_ccc_dly |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYC(0); + } + HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR, mss_ccc_div); + HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR, mss_ccc_dly); + HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux); +} + + +//========================================================================== +// Adjust ENVM timing + +static void +hal_a2fxxx_set_envm_timing( void ) { + cyg_uint32 x; + HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + CYGHWR_HAL_A2FXXX_SC_ENVM_CR, x); + x &= ~CYGHWR_HAL_A2FXXX_SC_ENVM_CR_SIX_CYCLE; + if( hal_a2fxxx_fclk <= 80e6 ){ + x |= CYGHWR_HAL_A2FXXX_SC_ENVM_CR_PIPE_BYPASS; + } else { + x &= ~CYGHWR_HAL_A2FXXX_SC_ENVM_CR_PIPE_BYPASS; + } + HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + CYGHWR_HAL_A2FXXX_SC_ENVM_CR, x); +} + +#endif // CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK + + +//========================================================================== +// Reset modules + +__externC void +hal_a2fxxx_periph_release( cyg_uint32 bit ) +{ + cyg_uint32 sc, base = CYGHWR_HAL_A2FXXX_SC; + HAL_READ_UINT32( base + CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR, sc ); + sc &= ~( bit ); + HAL_WRITE_UINT32( base + CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR, sc ); +} + + +__externC void +hal_a2fxxx_periph_reset( cyg_uint32 bit ) +{ + cyg_uint32 sc, base = CYGHWR_HAL_A2FXXX_SC; + HAL_READ_UINT32( base + CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR , sc ); + sc |= ( bit ); + HAL_WRITE_UINT32( base + CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR , sc ); +} + + +//========================================================================== +// GPIO support +// + +const default_io_mux_type default_io_mux[] = { + // SPI0 + {0x00}, {0x0a}, {0x00}, {0x00}, + // UART0 + {0x18}, {0x00}, + // I2C0 + {0x00}, {0x00}, + // SPI1 + {0x00}, {0x0a}, {0x00}, {0x00}, + // UART1 + {0x18}, {0x00}, + // I2C1 + {0x00}, {0x00}, + // MAC0 + {0x18}, {0x18}, {0x0a}, {0x0a}, {0x18}, {0x0a}, {0x0a}, {0x00}, {0x18}, + // GPIO + {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, + {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, + {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, + {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, + // SPI0 CS + {0x00}, {0x00}, {0x00}, + // Unused + {0x00}, {0x00}, {0x00}, {0x00}, + // UART0 misc + {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, + // SPI1 CS + {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, + // UART1 misc + {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, + {0x0} +}; + +// These functions provide configuration and IO for GPIO pins. + +__externC void +hal_a2fxxx_gpio_set( cyg_uint32 pin ) +{ + cyg_uint32 bit = CYGHWR_HAL_A2FXXX_GPIO_BIT( pin ); + cyg_uint32 mode = CYGHWR_HAL_A2FXXX_GPIO_MODE( pin ); + cyg_uint32 mux = CYGHWR_HAL_A2FXXX_GPIO_IOMUX_IDX( pin ); + cyg_uint32 irq = CYGHWR_HAL_A2FXXX_GPIO_IRQ( pin ); + cyg_uint32 reg = 0; + cyg_uint32 io_mux = 0; + + if (pin == CYGHWR_HAL_A2FXXX_GPIO_NONE) + return; + + if(mode == CYGHWR_HAL_A2FXXX_GPIO_MODE_PERIPH){ + // Set IOMUX default value for peripheral use + io_mux = default_io_mux[mux].val; + HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_IOMUX( mux ), io_mux ); + } else { + // Set GPIO input/ output mode + if (mode == CYGHWR_HAL_A2FXXX_GPIO_MODE_OUT) { + reg = CYGHWR_HAL_A2FXXX_GPIO_CFG_GPOUTEN | + CYGHWR_HAL_A2FXXX_GPIO_CFG_OUTBUFEN; + } + + // Configure IO as interrupt + if (irq != CYGHWR_HAL_A2FXXX_GPIO_IRQ_DISABLE) { + reg |= CYGHWR_HAL_A2FXXX_GPIO_CFG_GPINTEN; + if(irq & CYGHWR_HAL_A2FXXX_GPIO_IRQ_FALLING_EDGE) + reg |= CYGHWR_HAL_A2FXXX_GPIO_CFG_INTYPE(0); + else if(irq & CYGHWR_HAL_A2FXXX_GPIO_IRQ_RISING_EDGE) + reg |= CYGHWR_HAL_A2FXXX_GPIO_CFG_INTYPE(1); + else if(irq & CYGHWR_HAL_A2FXXX_GPIO_IRQ_BOTH_EDGES) + reg |= CYGHWR_HAL_A2FXXX_GPIO_CFG_INTYPE(2); + else if(irq & CYGHWR_HAL_A2FXXX_GPIO_IRQ_LOW_LEVEL) + reg |= CYGHWR_HAL_A2FXXX_GPIO_CFG_INTYPE(3); + else + reg |= CYGHWR_HAL_A2FXXX_GPIO_CFG_INTYPE(4); + } + + // Write down result + HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_MSS_GPIO + + ( CYGHWR_HAL_A2FXXX_MSS_GPIO_CFG( bit ) ), reg ); + + // For GPIO 16 to 31, we must setup the IOMUX + // TODO, this is for output only? + if( bit > 15 ){ + bit = bit - 16; + io_mux = 0x35; + HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + + CYGHWR_HAL_A2FXXX_SC_IOMUX( bit ), io_mux ); + } + + } +} + + +__externC void +hal_a2fxxx_gpio_out( cyg_uint32 pin, int val ) +{ + cyg_uint32 bit = ( CYGHWR_HAL_A2FXXX_GPIO_BIT(pin) << 2 ); + cyg_uint32 port = CYGHWR_HAL_A2FXXX_MSS_GPIO_BB + + ( CYGHWR_HAL_A2FXXX_MSS_GPIO_DOUT << 5 ); + + port += bit; + + HAL_WRITE_UINT32( port, val ); +} + + +__externC void +hal_a2fxxx_gpio_in ( cyg_uint32 pin, int *val ) +{ + cyg_uint32 bit = ( CYGHWR_HAL_A2FXXX_GPIO_BIT(pin) << 2 ); + cyg_uint32 port = CYGHWR_HAL_A2FXXX_MSS_GPIO_BB + + ( CYGHWR_HAL_A2FXXX_MSS_GPIO_DIN << 5 ); + cyg_uint32 pd; + + port += bit; + + HAL_READ_UINT32( port, pd ); + *val = 1 ? (bit & pd) : 0; +} + + +//========================================================================== +// I2C clock rate +// +__externC cyg_uint32 +hal_a2fxxx_i2c_clock( cyg_uint32 base ) +{ + return ( (base == CYGHWR_HAL_A2FXXX_I2C0) ? hal_a2fxxx_pclk0 : hal_a2fxxx_pclk1 ); +} + + +//========================================================================== +// SPI clock rate +// +__externC cyg_uint32 +hal_a2fxxx_spi_clock( cyg_uint32 base ) +{ + return ( (base == CYGHWR_HAL_A2FXXX_SPI0) ? hal_a2fxxx_pclk0 : hal_a2fxxx_pclk1 ); +} + + +//========================================================================== +// UART baud rate +// +// Set the baud rate divider of a UART based on the requested rate and +// the current APB clock settings. + +__externC void +hal_a2fxxx_uart_setbaud(cyg_uint32 base, cyg_uint32 baud) +{ + cyg_uint16 divider = + CYG_HAL_CORTEXM_A2FXXX_BAUD_GENERATOR( ((base == CYGHWR_HAL_A2FXXX_UART0)? 0 : 1) , baud ); + + HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_LCR, + CYGHWR_HAL_A2FXXX_UART16550_LCR_DLAB); + HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_DMR, divider >> 8); + HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_DLR, divider & 0xFF); +} + + +//========================================================================== +// Idle thread +// +#ifdef CYGSEM_HAL_CORTEXM_A2FXXX_DEFINES_IDLE_THREAD_ACTION +__externC void +hal_idle_thread_action( cyg_uint32 count ) +{ + while(1); +} +#endif + +//========================================================================== +// EOF a2fxxx_misc.c
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/var/current/src/hal_diag.c @@ -0,0 +1,399 @@ +/*============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008, 2011 +// Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Original: nickg (STM32 HAL) +// Date: 2011-04-03 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing + +#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_if.h> // interface API +#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED + +#include <cyg/hal/var_io.h> // USART registers + +//----------------------------------------------------------------------------- + +typedef struct { + cyg_uint32 uart; + CYG_ADDRESS base; + cyg_int32 msec_timeout; + int isr_vector; + cyg_uint32 rxpin; + cyg_uint32 txpin; + cyg_uint32 baud_rate; + int irq_state; + +} channel_data_t; + + +static channel_data_t a2fxxx_ser_channels[] = { +#if CYGINT_HAL_A2FXXX_UART0>0 + { 0, + CYGHWR_HAL_A2FXXX_UART0, + 1000, + CYGNUM_HAL_INTERRUPT_UART0, + CYGHWR_HAL_A2FXXX_UART0_RX, + CYGHWR_HAL_A2FXXX_UART0_TX, + CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD}, +#endif +#if CYGINT_HAL_A2FXXX_UART1>0 + { 1, + CYGHWR_HAL_A2FXXX_UART1, + 1000, + CYGNUM_HAL_INTERRUPT_UART1, + CYGHWR_HAL_A2FXXX_UART1_RX, + CYGHWR_HAL_A2FXXX_UART1_TX, + CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD}, +#endif +}; + +//----------------------------------------------------------------------------- + +static void +hal_a2fxxx_serial_init_channel(void* __ch_data) +{ + channel_data_t *chan = (channel_data_t*)__ch_data; + CYG_ADDRESS base = chan->base; + cyg_uint32 lcr = CYGHWR_HAL_A2FXXX_UART16550_LCR_WLS_8BITS | + CYGHWR_HAL_A2FXXX_UART16550_LCR_STOP_1; + + // Enable the PIO lines for the serial channel + CYGHWR_HAL_A2FXXX_GPIO_SET( chan->rxpin ); + CYGHWR_HAL_A2FXXX_GPIO_SET( chan->txpin ); + + // Set baud rate + hal_a2fxxx_uart_setbaud( base, chan->baud_rate ); + + // 8-1-no parity + HAL_WRITE_UINT32( base + CYGHWR_HAL_A2FXXX_UART16550_LCR, lcr ); + + // Reset and clear TX/RX FIFO + HAL_WRITE_UINT32( base + CYGHWR_HAL_A2FXXX_UART16550_FCR, + CYGHWR_HAL_A2FXXX_UART16550_FCR_CLEAR_TX_FIFO | + CYGHWR_HAL_A2FXXX_UART16550_FCR_CLEAR_RX_FIFO ); + +} + +void +hal_a2fxxx_serial_putc(void *__ch_data, char c) +{ + CYG_ADDRESS base = ((channel_data_t*)__ch_data)->base; + cyg_uint32 lsr; + CYGARC_HAL_SAVE_GP(); + + do + { + HAL_READ_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_LSR, lsr ); + } while ((lsr & CYGHWR_HAL_A2FXXX_UART16550_LSR_THRE) == 0); + + HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_THR, c ); + + CYGARC_HAL_RESTORE_GP(); +} + +static cyg_bool +hal_a2fxxx_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) +{ + CYG_ADDRESS base = ((channel_data_t*)__ch_data)->base; + cyg_uint32 lsr; + cyg_uint32 c; + CYGARC_HAL_SAVE_GP(); + + HAL_READ_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_LSR, lsr ); + + if( (lsr & CYGHWR_HAL_A2FXXX_UART16550_LSR_DR) == 0 ) + return false; + + HAL_READ_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_RBR, c ); + + *ch = (cyg_uint8)c; + + CYGARC_HAL_RESTORE_GP(); + + return true; +} + +cyg_uint8 +hal_a2fxxx_serial_getc(void* __ch_data) +{ + cyg_uint8 ch; + CYGARC_HAL_SAVE_GP(); + + while(!hal_a2fxxx_serial_getc_nonblock(__ch_data, &ch)); + + CYGARC_HAL_RESTORE_GP(); + return ch; +} + +//============================================================================= +// Virtual vector HAL diagnostics + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +static void +hal_a2fxxx_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + hal_a2fxxx_serial_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void +hal_a2fxxx_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + *__buf++ = hal_a2fxxx_serial_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + +cyg_bool +hal_a2fxxx_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + int delay_count; + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + delay_count = chan->msec_timeout * 100; // delay in 10 us steps + + for(;;) { + res = hal_a2fxxx_serial_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(10); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static int +hal_a2fxxx_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS base = ((channel_data_t*)__ch_data)->base; + int ret = 0; + cyg_uint32 ier; + + va_list ap; + + CYGARC_HAL_SAVE_GP(); + + va_start(ap, __func); + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + chan->irq_state = 1; + HAL_INTERRUPT_ACKNOWLEDGE( chan->isr_vector ); + HAL_INTERRUPT_UNMASK( chan->isr_vector ); + HAL_READ_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_IER, ier ); + ier |= CYGHWR_HAL_A2FXXX_UART16550_IER_ERBFI; + HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_IER, ier ); + break; + case __COMMCTL_IRQ_DISABLE: + ret = chan->irq_state; + chan->irq_state = 0; + HAL_INTERRUPT_MASK( chan->isr_vector ); + HAL_READ_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_IER, ier ); + ier &= ~CYGHWR_HAL_A2FXXX_UART16550_IER_ERBFI; + HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_IER, ier ); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + + va_start(ap, __func); + + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + case __COMMCTL_GETBAUD: + ret = chan->baud_rate; + break; + case __COMMCTL_SETBAUD: + chan->baud_rate = va_arg(ap, cyg_int32); + // Should we verify this value here? + hal_a2fxxx_uart_setbaud( base, chan->baud_rate ); + ret = 0; + break; + default: + break; + } + va_end(ap); + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +static int +hal_a2fxxx_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_uint8 ch; + + CYGARC_HAL_SAVE_GP(); + + *__ctrlc = 0; + + if( hal_a2fxxx_serial_getc_nonblock(__ch_data, &ch) ) + { + if( cyg_hal_is_break( (char *)&ch , 1 ) ) + *__ctrlc = 1; + } + + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); + + CYGARC_HAL_RESTORE_GP(); + return 1; +} + +static void +hal_a2fxxx_serial_init(void) +{ + hal_virtual_comm_table_t* comm; + int cur; + int i; + + cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + for( i = 0; i < CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS ; i++ ) + { + hal_a2fxxx_serial_init_channel(&a2fxxx_ser_channels[i]); + + CYGACC_CALL_IF_SET_CONSOLE_COMM(i); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &a2fxxx_ser_channels[i]); + CYGACC_COMM_IF_WRITE_SET(*comm, hal_a2fxxx_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, hal_a2fxxx_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, hal_a2fxxx_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, hal_a2fxxx_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, hal_a2fxxx_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, hal_a2fxxx_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, hal_a2fxxx_serial_getc_timeout); + } + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); + + // set debug channel baud rate if different +#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD) + a2fxxx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate = + CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD; + update_baud_rate( &a2fxxx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL] ); +#endif + +} + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + + initialized = 1; + + hal_a2fxxx_serial_init(); +} + +#endif + +//============================================================================= +// Non-Virtual vector HAL diagnostics + +#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +void +hal_a2fxxx_diag_init(void) +{ + hal_a2fxxx_serial_init( + &a2fxxx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] ); +} + +void +hal_a2fxxx_diag_putc(char c) +{ + hal_a2fxxx_serial_putc( + &a2fxxx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL], c); +} + +cyg_uint8 +hal_a2fxxx_diag_getc(void) +{ + return hal_a2fxxx_serial_getc( + &a2fxxx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] ); +} + + +#endif + +//----------------------------------------------------------------------------- +// End of hal_diag.c
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/var/current/src/hal_dma.c @@ -0,0 +1,425 @@ +/*========================================================================== +// +// hal_dma.c +// +// Cortex-M Actel A2F DMA channels configuration +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Contributors: +// Date: 2011-02-03 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_a2fxxx.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header +#include <cyg/hal/hal_if.h> // HAL header +#include <cyg/hal/drv_api.h> + +#ifdef CYGDBG_HAL_CORTEXM_A2FXXX_DMA_TRACE +# define DMA_TRACE(args...) diag_printf(args) +#else +# define DMA_TRACE(args...) +#endif + +//----------------------------------------------------------------------------- +// DMA channel ISR/DSR handling + +typedef struct a2fxxx_dma_ch { + cyg_ISR_t* isr; + cyg_DSR_t* dsr; + cyg_addrword_t data; +} a2fxxx_dma_ch; + +typedef struct a2fxxx_dma_info { + cyg_uint32 init; + cyg_uint32 base; + cyg_handle_t interrupt_handle; + cyg_interrupt interrupt_data; + a2fxxx_dma_ch ch[CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL]; + cyg_uint32 dma_cr[CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL]; + cyg_uint32 dma_sr; +} a2fxxx_dma_info; + +static a2fxxx_dma_info a2fxxx_dma = { + .base = CYGHWR_HAL_A2FXXX_DMA, + .init =0, +}; + + +//----------------------------------------------------------------------------- +// DMA ISR handler + +static cyg_uint32 +a2fxxx_dma_isr (cyg_vector_t vector, cyg_addrword_t data) +{ + a2fxxx_dma_info *dma = (a2fxxx_dma_info *) data; + cyg_uint32 res = 0, sr = 0; + cyg_uint8 i = 0, j = 0; + + HAL_READ_UINT32(dma->base + CYGHWR_HAL_A2FXXX_DMA_BUFFER_STATUS, sr); + dma->dma_sr |= sr; + + DMA_TRACE("DMA interrupt, sr 0x%x\n", dma->dma_sr); + + while(i < 16){ + if( sr & 0x1 ){ + j = i >> 1; + if(dma->ch[j].isr != NULL){ + res = dma->ch[j].isr(i, dma->ch[j].data); + } + } + sr = sr >> 1; i++; + } + cyg_drv_interrupt_acknowledge (CYGNUM_HAL_INTERRUPT_DMA); + cyg_drv_interrupt_mask (CYGNUM_HAL_INTERRUPT_DMA); + return (CYG_ISR_CALL_DSR | CYG_ISR_HANDLED); +} + + +//----------------------------------------------------------------------------- +// DMA DSR handler + +static void +a2fxxx_dma_dsr (cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + a2fxxx_dma_info *dma = (a2fxxx_dma_info *) data; + cyg_uint8 i = 0, j = 0; + cyg_uint32 sr; + + cyg_drv_isr_lock (); + sr = dma->dma_sr; + dma->dma_sr = 0; + cyg_drv_isr_unlock (); + + while(i < 16){ + if( sr & 0x1 ){ + j = i >> 1; + if(dma->ch[j].dsr != NULL){ + dma->ch[j].dsr(i, 0, dma->ch[j].data); + } + } + sr = sr >> 1; i++; + } + + cyg_drv_interrupt_unmask (CYGNUM_HAL_INTERRUPT_DMA); +} + + +//----------------------------------------------------------------------------- +// DMA Initialization + +void +hal_dma_init( void ) +{ + cyg_uint8 i = 0; + + // Avoid multiple initialization + if(a2fxxx_dma.init) + return; + + a2fxxx_dma.init = 1; + + // Reset DMA + CYGHWR_HAL_A2FXXX_PERIPH_RESET( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(PDMA) ); + + // Clear channel ISR / DSR + while( i < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL ) { + a2fxxx_dma.ch[i].isr = NULL; + a2fxxx_dma.ch[i].dsr = NULL; + a2fxxx_dma.dma_cr[i] = 0; + a2fxxx_dma.ch[i++].data = 0; + } + a2fxxx_dma.dma_sr = 0; + + // Register DMA interrupt + cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_DMA, + CYGNUM_HAL_CORTEXM_A2FXXX_DMA_ISR_PRIORITY, + (cyg_addrword_t)&a2fxxx_dma, + &a2fxxx_dma_isr, + &a2fxxx_dma_dsr, + &(a2fxxx_dma.interrupt_handle), + &(a2fxxx_dma.interrupt_data)); + cyg_drv_interrupt_attach(a2fxxx_dma.interrupt_handle); + cyg_drv_interrupt_acknowledge (CYGNUM_HAL_INTERRUPT_DMA); + cyg_drv_interrupt_unmask (CYGNUM_HAL_INTERRUPT_DMA); + + // Release DMA + CYGHWR_HAL_A2FXXX_PERIPH_RELEASE( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(PDMA) ); + + // HW initialization + i=0; + while( i < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL ) { + HAL_WRITE_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(i++), + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_RESET); + } +} + + +//----------------------------------------------------------------------------- +// Register the DMA sub-channel ISR / DSR + +__externC cyg_uint32 +a2fxxx_dma_ch_attach(cyg_uint8 ch, cyg_ISR_t *isr, cyg_DSR_t *dsr, + cyg_addrword_t data) +{ + cyg_uint32 res = 1; + + CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL, + "DMA : Channel number out of range (Attach)."); + +#ifdef CYGPKG_KERNEL + cyg_interrupt_disable(); +#endif + if( a2fxxx_dma.ch[ch].isr != NULL || + a2fxxx_dma.ch[ch].dsr != NULL || a2fxxx_dma.ch[ch].data != 0 ) { + res = 0; + } else { + a2fxxx_dma.ch[ch].isr = isr; + a2fxxx_dma.ch[ch].dsr = dsr; + a2fxxx_dma.ch[ch].data = data; + } +#ifdef CYGPKG_KERNEL + cyg_interrupt_enable(); +#endif + + return res; +} + + +//----------------------------------------------------------------------------- +// Update DMA source / destination address increment + +__externC void +a2fxxx_dma_update_incr(cyg_uint8 ch, cyg_bool dst, cyg_uint8 incr) +{ + CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL, + "DMA : Channel number out of range (Update)."); + + if(dst==false){ + // Clear bits + a2fxxx_dma.dma_cr[ch] &= ~CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR_4B; + a2fxxx_dma.dma_cr[ch] |= CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR(incr); + } + else { + // Clear bits + a2fxxx_dma.dma_cr[ch] &= ~CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR_4B; + a2fxxx_dma.dma_cr[ch] |= CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR(incr); + } +} + + +//----------------------------------------------------------------------------- +// Setup DMA channel +// +// channel select the DMA channel ID. +// type select the transfer type to be performed. For valid +// values, check CYGHWR_HAL_A2FXXX_DMA_XFER(_x) in var_io.h. +// outbound set to true for transfer out of memory, false for transfer to +// memory +// src_incr select the memory address increment step for the source. Valid +// values are 0, 1, 2 and 4 byte(s). 0 can be used for DMA +// transfer from peripheral FIFO for instance. +// dst_incr select the memory address increment step for the destination. +// Valid values are 0, 1, 2 and 4 byte(s). 0 can be used for DMA +// transfer to peripheral FIFO for instance. +// pri select the DMA channel priority (true = high , false = low) +// wr_adj indicates the number of FCLK periods which the PDMA must wait +// after completion of a read or write access to a peripheral before +// evaluating the out-of-band status signals from that peripheral +// for another transfer + +__externC cyg_uint32 +a2fxxx_dma_ch_setup(cyg_uint8 ch, cyg_uint8 type, cyg_bool outbound, + cyg_uint8 src_incr, cyg_uint8 dst_incr, cyg_bool pri, cyg_uint8 wr_adj) +{ + cyg_uint32 res = 1; + cyg_uint32 xfer_type = 0, xfer_dir = 0, xfer_incr = + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_XFER_BYTE; + a2fxxx_dma.dma_cr[ch] = 0; + + CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL, + "DMA : Channel number out of range (Setup)."); + + DMA_TRACE("DMA setup channel %d, direction: %s, type %x, step %d-%d byte(s)\n", ch , + ((outbound==true) ? "outbound" : "inbound"), type, src_incr, dst_incr ); + + if( type != CYGHWR_HAL_A2FXXX_DMA_XFER_MEMORY ){ + xfer_type = CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_PERIPH_SEL(type) | + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_PERIPH; + } + + if( outbound == true ){ + xfer_dir = CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DIR; + } + + a2fxxx_dma_update_incr(ch, true, dst_incr); + a2fxxx_dma_update_incr(ch, false, src_incr); + + a2fxxx_dma.dma_cr[ch] |= ( xfer_type | xfer_dir | + ((pri == true) ? CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_HI_PRI : 0) | + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_COMPA | + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_COMPB | + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_WR_ADJ(wr_adj) | + xfer_incr); + + HAL_WRITE_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(ch), + a2fxxx_dma.dma_cr[ch]); + + return res; +} + + +//----------------------------------------------------------------------------- +// Remove DMA channel handler + +__externC void +a2fxxx_dma_ch_detach (cyg_uint8 ch) +{ + CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL, + "DMA : Channel number out of range (Detach)."); + +#ifdef CYGPKG_KERNEL + cyg_interrupt_disable(); +#endif + a2fxxx_dma.ch[ch].isr = NULL; + a2fxxx_dma.ch[ch].dsr = NULL; + a2fxxx_dma.ch[ch].data = 0; +#ifdef CYGPKG_KERNEL + cyg_interrupt_enable(); +#endif +} + + +//----------------------------------------------------------------------------- +// Start DMA transfer + +__externC cyg_uint32 +a2fxxx_dma_xfer (cyg_uint8 ch, cyg_bool polled, cyg_uint32 len, cyg_uint8 *src, + cyg_uint8 *dst) +{ + cyg_uint32 res = 1; + cyg_uint32 src_reg, dst_reg, cnt_reg; + cyg_uint32 sub = 0; + cyg_haladdress dma_src = (cyg_haladdress) src; + cyg_haladdress dma_dst = (cyg_haladdress) dst; + + CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL, + "DMA : Channel number out of range (Transfer)."); + + if( polled == true ) + a2fxxx_dma.dma_cr[ch] &= ~CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_INTEN; + else + a2fxxx_dma.dma_cr[ch] |= CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_INTEN; + + HAL_WRITE_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(ch), + a2fxxx_dma.dma_cr[ch]); + + HAL_READ_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_STATUS(ch), sub); + sub = CYGHWR_HAL_A2FXXX_DMA_GET_SUB_ID( sub ); + + src_reg = ((sub == 0) ? CYGHWR_HAL_A2FXXX_DMA_CHx_BA_SRC(ch) : + CYGHWR_HAL_A2FXXX_DMA_CHx_BB_SRC(ch)); + dst_reg = ((sub == 0) ? CYGHWR_HAL_A2FXXX_DMA_CHx_BA_DST(ch) : + CYGHWR_HAL_A2FXXX_DMA_CHx_BB_DST(ch)); + cnt_reg = ((sub == 0) ? CYGHWR_HAL_A2FXXX_DMA_CHx_BA_COUNT(ch) : + CYGHWR_HAL_A2FXXX_DMA_CHx_BB_COUNT(ch)); + + DMA_TRACE("DMA transfer of length %d on channel %d(%s) - SRC: 0x%x / DST: 0x%x\n", + len, ch, ((sub==0) ? "A" : "B"), dma_src, dma_dst); + DMA_TRACE("DMA register address 0x%x / 0x%x\n", src_reg , dst_reg); + + HAL_WRITE_UINT32(a2fxxx_dma.base + src_reg, dma_src); + HAL_WRITE_UINT32(a2fxxx_dma.base + dst_reg, dma_dst); + HAL_WRITE_UINT32(a2fxxx_dma.base + cnt_reg, len); + + return res; +} + + +//----------------------------------------------------------------------------- +// Clear DMA interrupt + +void a2fxxx_dma_clear_interrupt (cyg_uint8 ch) +{ + cyg_uint32 reg; + + CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL, + "DMA : Channel number out of range (Clear IRQ)."); + + DMA_TRACE("DMA status register 0x%x\n", + (a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(ch))); + + HAL_READ_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(ch), reg); + reg |= (CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_COMPA | + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_COMPB); + HAL_WRITE_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(ch), reg); +} + + +//----------------------------------------------------------------------------- +// Clear DMA interrupt + +cyg_uint8 a2fxxx_dma_get_comp_flag (cyg_uint8 ch) +{ + cyg_uint32 reg; + + CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL, + "DMA : Channel number out of range (Get)."); + + HAL_READ_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_STATUS(ch), reg); + + return (reg&0x3); +} + +//----------------------------------------------------------------------------- +// End of hal_dma.c
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/var/current/tests/timers.c @@ -0,0 +1,336 @@ +/*============================================================================= +// +// timers.c +// +// Test for Cortex-M3 Actel Smartfusion Timers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg for STM32 +// ccoutand updated for Cortex-M3 Actel Smartfusion Devices +// Date: 2011-03-06 +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#if defined(CYGPKG_KERNEL) +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/testcase.h> + +//============================================================================= +// Check all required packages and components are present + +#if !defined(CYGPKG_KERNEL) || !defined(CYGPKG_KERNEL_API) + +#define NA_MSG "Configuration insufficient" + +#endif + +//============================================================================= +// If everything is present, compile the full test. + +#ifndef NA_MSG + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_if.h> + +#include <cyg/kernel/kapi.h> +#include <cyg/infra/diag.h> +#include <string.h> + +//============================================================================= + +#define LOOPS 24 // == 2 minutes + +#define STACK_SIZE 8000 + +static int test_stack[(STACK_SIZE/sizeof(int))]; +static cyg_thread test_thread; +static cyg_handle_t main_thread; + +//============================================================================= + +struct timer +{ + cyg_uint32 timer; + cyg_uint32 base; + cyg_uint32 vector; + cyg_uint32 priority; + cyg_uint32 interval; + + cyg_uint32 ticks; + + cyg_uint32 preempt[10]; + + cyg_uint32 preempt_dsr[10]; + cyg_uint32 dsr_count[10]; + + cyg_interrupt interrupt_object; + cyg_handle_t interrupt_handle; +}; + +struct timer timers[] = +{ + { 1, CYGHWR_HAL_A2FXXX_TIMER1, CYGNUM_HAL_INTERRUPT_TIM0_1, 0x20, 127 }, + { 2, CYGHWR_HAL_A2FXXX_TIMER2, CYGNUM_HAL_INTERRUPT_TIM0_2, 0x30, 355 }, + { 0, 0, 0, 0 } +}; + +//============================================================================= + +volatile cyg_uint32 ticks = 0; +volatile cyg_uint32 nesting = 0; +volatile cyg_uint32 max_nesting = 0; +volatile cyg_uint32 max_nesting_seen = 0; +volatile cyg_uint32 current = 0; +volatile cyg_uint32 in_dsr = 0; + +//============================================================================= + +__externC cyg_uint32 hal_a2fxxx_pclk0; + +void init_timer( cyg_uint32 base, cyg_uint32 interval ) +{ + cyg_uint32 period = hal_a2fxxx_pclk0; + + period = period / 1000000; + period = period * interval; + + HAL_WRITE_UINT32(base+CYGHWR_HAL_A2FXXX_TIMER_TIMx_BGLOADVAL, period-1 ); + + HAL_WRITE_UINT32(base+CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL, \ + CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL_EN | CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL_INTEN); +} + +//============================================================================= + +cyg_uint32 timer_isr( cyg_uint32 vector, CYG_ADDRWORD data ) +{ + struct timer *t = (struct timer *)data; + cyg_uint32 preempt = current; + CYG_ADDRWORD base = t->base; + cyg_uint32 cnt; + + current = t->timer; + t->ticks++; + ticks++; + t->preempt[preempt]++; + nesting++; + + // Count only first ISR to preempt a DSR + if( preempt == 0 ) + t->preempt_dsr[in_dsr]++; + + HAL_WRITE_UINT32(t->base+CYGHWR_HAL_A2FXXX_TIMER_TIMx_RIS, 1 ); + + if( nesting > max_nesting ) + max_nesting = nesting; + + // Loiter here for a proportion of the timer interval to give + // other timers the chance to preempt us. + do + { + HAL_READ_UINT32( base+CYGHWR_HAL_A2FXXX_TIMER_TIMx_VAL, cnt ); + } while( cnt < t->interval/10 ); + + nesting--; + current = preempt; + + if( (t->ticks % 10) == 0 ) + return 3; + else + return 1; +} + +//============================================================================= + +void timer_dsr( cyg_uint32 vector, cyg_uint32 count, CYG_ADDRWORD data ) +{ + struct timer *t = (struct timer *)data; + int i; + + in_dsr = t->timer; + + if( count >= 8 ) + count = 8; + + t->dsr_count[count]++; + + // Loiter for a while + for( i = 0; i < t->interval/10; i++) + continue; + + in_dsr = 0; +} + +//============================================================================= + +void +timers_test(cyg_addrword_t data) +{ + int loops = LOOPS; + int i; + CYG_INTERRUPT_STATE istate; + + CYG_TEST_INIT(); + + CYG_TEST_INFO("Start Timers test"); + + CYGHWR_HAL_A2FXXX_PERIPH_RELEASE( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(TIMER) ); + + for( i = 0; timers[i].timer != 0; i++ ) + { + struct timer *t = &timers[i]; + + init_timer( t->base, t->interval ); + + cyg_interrupt_create( t->vector, + t->priority, + (cyg_addrword_t)t, + timer_isr, + timer_dsr, + &t->interrupt_handle, + &t->interrupt_object + ); + + cyg_interrupt_attach( t->interrupt_handle ); + cyg_interrupt_unmask( t->vector ); + + } + + while( loops-- ) + { + int j; + + // 5 second delay + cyg_thread_delay( 5*100 ); + + // Disable interrupts while we print details, otherwise it + // comes out very slowly. + HAL_DISABLE_INTERRUPTS( istate ); + + if( max_nesting > max_nesting_seen ) + max_nesting_seen = max_nesting; + + diag_printf("\nISRs max_nesting %d max_nesting_seen %d\n", max_nesting, max_nesting_seen ); + max_nesting = 0; + + diag_printf(" T Ticks "); + + for( j = 0; j < 9; j++ ) + diag_printf("%9d ", j ); + diag_printf("\n"); + + for( i = 0; timers[i].timer != 0; i++ ) + { + struct timer *t = &timers[i]; + + diag_printf("%2d: %9d ", t->timer, t->ticks ); + + for( j = 0; j < 9; j++ ) + diag_printf("%9d ", t->preempt[j] ); + diag_printf("\n"); + + } + + diag_printf("DSRs\n"); + + diag_printf(" T: "); + + for( j = 0; j < 9; j++ ) + diag_printf("%9d ", j ); + diag_printf("\n"); + + for( i = 0; timers[i].timer != 0; i++ ) + { + struct timer *t = &timers[i]; + + diag_printf("%2d: preempt: ", t->timer); + + for( j = 0; j < 9; j++ ) + diag_printf("%9d ", t->preempt_dsr[j] ); + diag_printf("\n"); + + diag_printf(" count: "); + + for( j = 0; j < 9; j++ ) + diag_printf("%9d ", t->dsr_count[j] ); + diag_printf("\n"); + } + + HAL_RESTORE_INTERRUPTS( istate ); + } + + CYG_TEST_PASS_FINISH("Timers test"); +} + +//============================================================================= + +void cyg_user_start(void) +{ + cyg_thread_create(0, // Priority + timers_test, + 0, + "timers test", // Name + test_stack, // Stack + STACK_SIZE, // Size + &main_thread, // Handle + &test_thread // Thread data structure + ); + cyg_thread_resume( main_thread); +} + +//============================================================================= +// Print a message if we cannot run + +#else // NA_MSG + +void cyg_user_start(void) +{ + CYG_TEST_NA(NA_MSG); +} + +#endif // NA_MSG + +//============================================================================= +/* EOF timers.c */