Mercurial > ecos
changeset 18:7253dcc42a09 ecos-sw-1999-06-25
Merge from eCos master repository on 1999-06-25-15:31:50-BST
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--- a/packages/hal/common/current/ChangeLog +++ b/packages/hal/common/current/ChangeLog @@ -1,3 +1,9 @@ +1999-06-24 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/hal.h: Clarify descriptions of + CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT and + CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT. + 1999-06-17 Nick Garnett <nickg@cygnus.co.uk> * include/pkgconf/hal.h: Added CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
--- a/packages/hal/common/current/include/pkgconf/hal.h +++ b/packages/hal/common/current/include/pkgconf/hal.h @@ -326,8 +326,8 @@ } cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT { - display "Include GDB external break support" - parent CYGPKG_HAL_DEBUG + display "Include GDB external break support for stubs" + parent CYGDBG_HAL_DEBUG requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS requires !CYGPKG_HAL_MIPS_TX39_JMR3904 requires !CYGPKG_HAL_POWERPC_FADS @@ -336,11 +336,13 @@ This option causes the GDB stub to add a serial interrupt handler which will listen for GDB break packets. This lets you stop the target asynchronously when using GDB, usually by hitting Control+C - or pressing the STOP button." + or pressing the STOP button. This option differs from + CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT in that it is used when + GDB stubs are present." } cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { - display "Include GDB external break support" + display "Include GDB external break support when no stubs" parent CYGPKG_HAL_DEBUG requires !CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT description "
--- a/packages/hal/mips/arch/current/ChangeLog +++ b/packages/hal/mips/arch/current/ChangeLog @@ -1,3 +1,26 @@ +1999-06-25 Nick Garnett <nickg@cygnus.co.uk> + + * include/arch.inc: + * include/hal_arch.h: + Added initializer for FPU FSR register. + +1999-06-22 Nick Garnett <nickg@cygnus.co.uk> + + * src/hal_misc.c (hal_default_isr): When chaining, always try the + ctrlc ISR, the passed-in vector number can be bogus. + +1999-06-18 Nick Garnett <nickg@cygnus.co.uk> + + * src/hal_misc.c: + Added cyg_hal_clock_period variable. + + * include/hal_intr.h: + Modified HAL_CLOCK_LATENCY() macro to do the right thing. + Added cyg_hal_clock_period variable. + + * include/hal_cache.h: Modified implementations of cache macros to + only do anything if the appropriate cache is enabled. + 1999-06-17 Nick Garnett <nickg@cygnus.co.uk> * src/vectors.S: Added code to discriminate different entry
--- a/packages/hal/mips/arch/current/include/arch.inc +++ b/packages/hal/mips/arch/current/include/arch.inc @@ -340,7 +340,11 @@ hal_intc_translation_table: #else #error MIPS FPU register size not defined #endif - + +#ifndef CYG_HAL_MIPS_FSR_INIT +#define CYG_HAL_MIPS_FSR_INIT 0 +#endif + .macro hal_fpu_init mfc0 v0,status # Get sr la v1,0xDBFFFFFF # Clear bits to be changed @@ -351,7 +355,8 @@ hal_intc_translation_table: nop nop nop - ctc1 zero,$31 # clear Fp control reg + la v0,CYG_HAL_MIPS_FSR_INIT # Get initial value for FSR + ctc1 v0,$31 # set Fp control reg nop .endm
--- a/packages/hal/mips/arch/current/include/hal_arch.h +++ b/packages/hal/mips/arch/current/include/hal_arch.h @@ -119,7 +119,7 @@ externC cyg_uint32 hal_msbit_index(cyg_u #define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ ) \ { \ for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->f[_i_] = (_id_)|0xFF00|_i_; \ - (_regs_)->fcr31 = 0; \ + (_regs_)->fcr31 = 0x01000000; \ } #else #define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ )
--- a/packages/hal/mips/arch/current/include/hal_cache.h +++ b/packages/hal/mips/arch/current/include/hal_cache.h @@ -108,19 +108,16 @@ // Synchronize the contents of the cache with memory. // This uses the index-writeback-invalidate operation. #ifndef HAL_DCACHE_SYNC_DEFINED -#define HAL_DCACHE_SYNC() \ -{ \ - register CYG_ADDRESS _baddr_ = 0x80000000; \ - register CYG_ADDRESS _addr_ = 0x80000000; \ - register CYG_WORD _size_ = HAL_DCACHE_SIZE; \ - register CYG_WORD _state_; \ - HAL_DCACHE_IS_ENABLED(_state_); \ - HAL_DCACHE_DISABLE(); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ - { \ - asm volatile ("cache 0x01,0(%0)" : : "r"(_addr_) ); \ - } \ - if( _state_ ) HAL_DCACHE_ENABLE(); \ +#define HAL_DCACHE_SYNC() \ +{ \ + register CYG_ADDRESS _baddr_ = 0x80000000; \ + register CYG_ADDRESS _addr_ = 0x80000000; \ + register CYG_WORD _size_ = HAL_DCACHE_SIZE; \ + register CYG_WORD _state_; \ + HAL_DCACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { asm volatile ("cache 0x01,0(%0)" : : "r"(_addr_) ); } \ } #endif @@ -137,19 +134,16 @@ // and then lock the cache so that it stays there. // This uses the fetch-and-lock cache operation. #ifndef HAL_DCACHE_LOCK_DEFINED -#define HAL_DCACHE_LOCK(_base_, _asize_) \ -CYG_MACRO_START \ - register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - register CYG_WORD _state_; \ - HAL_DCACHE_IS_ENABLED(_state_); \ - HAL_DCACHE_DISABLE(); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ - { \ - asm volatile ("cache 0x1d,0(%0)" : : "r"(_addr_) ); \ - } \ - if( _state_ ) HAL_DCACHE_ENABLE(); \ +#define HAL_DCACHE_LOCK(_base_, _asize_) \ +CYG_MACRO_START \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_DCACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { asm volatile ("cache 0x1d,0(%0)" : : "r"(_addr_) ); } \ CYG_MACRO_END #endif @@ -177,57 +171,48 @@ CYG_MACRO_END // for the given address range. // This uses the hit-writeback-invalidate cache operation. #ifndef HAL_DCACHE_FLUSH_DEFINED -#define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \ -{ \ - register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - register CYG_WORD _state_; \ - HAL_DCACHE_IS_ENABLED(_state_); \ - HAL_DCACHE_DISABLE(); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ - { \ - asm volatile ("cache 0x15,0(%0)" : : "r"(_addr_) ); \ - } \ - if( _state_ ) HAL_DCACHE_ENABLE(); \ +#define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \ +{ \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_DCACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { asm volatile ("cache 0x15,0(%0)" : : "r"(_addr_) ); } \ } #endif // Invalidate cache lines in the given range without writing to memory. // This uses the hit-invalidate cache operation. #ifndef HAL_DCACHE_INVALIDATE_DEFINED -#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \ -{ \ - register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - register CYG_WORD _state_; \ - HAL_DCACHE_IS_ENABLED(_state_); \ - HAL_DCACHE_DISABLE(); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ - { \ - asm volatile ("cache 0x11,0(%0)" : : "r"(_addr_) ); \ - } \ - if( _state_ ) HAL_DCACHE_ENABLE(); \ +#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \ +{ \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_DCACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { asm volatile ("cache 0x11,0(%0)" : : "r"(_addr_) ); } \ } #endif // Write dirty cache lines to memory for the given address range. // This uses the hit-writeback cache operation. #ifndef HAL_DCACHE_STORE_DEFINED -#define HAL_DCACHE_STORE( _base_ , _asize_ ) \ -{ \ - register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - register CYG_WORD _state_; \ - HAL_DCACHE_IS_ENABLED(_state_); \ - HAL_DCACHE_DISABLE(); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ - { \ - asm volatile ("cache 0x19,0(%0)" : : "r"(_addr_) ); \ - } \ - if( _state_ ) HAL_DCACHE_ENABLE(); \ +#define HAL_DCACHE_STORE( _base_ , _asize_ ) \ +{ \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_DCACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { asm volatile ("cache 0x19,0(%0)" : : "r"(_addr_) ); } \ } #endif @@ -263,18 +248,15 @@ CYG_MACRO_END // Invalidate the entire cache // This uses the index-invalidate cache operation. #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED -#define HAL_ICACHE_INVALIDATE_ALL() \ -{ \ - register CYG_ADDRESS _baddr_ = 0x80000000; \ - register CYG_ADDRESS _addr_ = 0x80000000; \ - register CYG_WORD _state_; \ - HAL_ICACHE_IS_ENABLED(_state_); \ - HAL_ICACHE_DISABLE(); \ - for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \ - { \ - asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); \ - } \ - if( _state_ ) HAL_ICACHE_ENABLE(); \ +#define HAL_ICACHE_INVALIDATE_ALL() \ +{ \ + register CYG_ADDRESS _baddr_ = 0x80000000; \ + register CYG_ADDRESS _addr_ = 0x80000000; \ + register CYG_WORD _state_; \ + HAL_ICACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) \ + for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \ + { asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); } \ } #endif @@ -291,19 +273,16 @@ CYG_MACRO_END // and then lock the cache so that it stays there. // This uses the fetch-and-lock cache operation. #ifndef HAL_ICACHE_LOCK_DEFINED -#define HAL_ICACHE_LOCK(_base_, _asize_) \ -CYG_MACRO_START \ - register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - register CYG_WORD _state_; \ - HAL_ICACHE_IS_ENABLED(_state_); \ - HAL_ICACHE_DISABLE(); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ - { \ - asm volatile ("cache 0x1c,0(%0)" : : "r"(_addr_) ); \ - } \ - if( _state_ ) HAL_ICACHE_ENABLE(); \ +#define HAL_ICACHE_LOCK(_base_, _asize_) \ +CYG_MACRO_START \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_ICACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { asm volatile ("cache 0x1c,0(%0)" : : "r"(_addr_) ); } \ CYG_MACRO_END #endif @@ -323,19 +302,16 @@ CYG_MACRO_END // Invalidate cache lines in the given range without writing to memory. // This uses the hit-invalidate cache operation. #ifndef HAL_ICACHE_INVALIDATE_DEFINED -#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \ -{ \ - register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - register CYG_WORD _state_; \ - HAL_ICACHE_IS_ENABLED(_state_); \ - HAL_ICACHE_DISABLE(); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ - { \ - asm volatile ("cache 0x10,0(%0)" : : "r"(_addr_) ); \ - } \ - HAL_ICACHE_ENABLE(); \ +#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \ +{ \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_ICACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ + { asm volatile ("cache 0x10,0(%0)" : : "r"(_addr_) ); } \ } #endif
--- a/packages/hal/mips/arch/current/include/hal_intr.h +++ b/packages/hal/mips/arch/current/include/hal_intr.h @@ -417,6 +417,9 @@ CYG_MACRO_END #ifndef CYGHWR_HAL_CLOCK_CONTROL_DEFINED +externC CYG_WORD32 cyg_hal_clock_period; +#define CYGHWR_HAL_CLOCK_PERIOD_DEFINED + #define HAL_CLOCK_INITIALIZE( _period_ ) \ CYG_MACRO_START \ asm volatile ( \ @@ -427,6 +430,7 @@ CYG_MACRO_START : \ : "r"(_period_) \ ); \ + cyg_hal_clock_period = _period_; \ CYG_MACRO_END #define HAL_CLOCK_RESET( _vector_, _period_ ) \ @@ -457,7 +461,12 @@ CYG_MACRO_END #if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && \ !defined(HAL_CLOCK_LATENCY) -#define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ(_pvalue_) +#define HAL_CLOCK_LATENCY( _pvalue_ ) \ +CYG_MACRO_START \ + register CYG_WORD32 _cval_; \ + HAL_CLOCK_READ(&_cval_); \ + *(_pvalue_) = _cval_ - cyg_hal_clock_period; \ +CYG_MACRO_END #endif //--------------------------------------------------------------------------
--- a/packages/hal/mips/arch/current/src/hal_misc.c +++ b/packages/hal/mips/arch/current/src/hal_misc.c @@ -53,6 +53,15 @@ #include <cyg/hal/hal_cache.h> // Cache handling /*------------------------------------------------------------------------*/ +/* If required, define a variable to store the clock period. */ + +#ifdef CYGHWR_HAL_CLOCK_PERIOD_DEFINED + +CYG_WORD32 cyg_hal_clock_period; + +#endif + +/*------------------------------------------------------------------------*/ /* First level C exception handler. */ externC void __handle_exception (void); @@ -95,7 +104,9 @@ externC cyg_uint32 hal_default_isr(CYG_A defined(CYGHWR_HAL_GDB_PORT_VECTOR) && \ defined(HAL_CTRLC_ISR) +#ifndef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN if( vector == CYGHWR_HAL_GDB_PORT_VECTOR ) +#endif { cyg_uint32 result = HAL_CTRLC_ISR( vector, data ); if( result != 0 ) return result;
--- a/packages/hal/mips/jmr3904/current/ChangeLog +++ b/packages/hal/mips/jmr3904/current/ChangeLog @@ -1,3 +1,8 @@ +1999-06-21 Nick Garnett <nickg@cygnus.co.uk> + + * src/plf_misc.c (hal_ctrlc_isr): Changed return value from 0 to 2 + to indicate that the interrupt has been handled. + 1999-06-02 Jonathan Larmour <jlarmour@cygnus.co.uk> * include/pkgconf/mlt_mips_tx39_jmr3904_rom.mlt:
--- a/packages/hal/mips/jmr3904/current/src/plf_misc.c +++ b/packages/hal/mips/jmr3904/current/src/plf_misc.c @@ -211,7 +211,7 @@ cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD ve cyg_hal_user_break( (CYG_ADDRWORD *)hal_saved_interrupt_state ); } - return 0; + return 2; } #endif
--- a/packages/hal/mips/sim/current/ChangeLog +++ b/packages/hal/mips/sim/current/ChangeLog @@ -1,3 +1,8 @@ +1999-06-21 Nick Garnett <nickg@cygnus.co.uk> + + * src/plf_misc.c: Added hal_saved_interrupt_state variable to + allow code to link. + 1999-06-02 Jonathan Larmour <jlarmour@cygnus.co.uk> * include/pkgconf/mlt_mips_tx39_sim_ram.ldi:
--- a/packages/hal/mips/sim/current/src/plf_misc.c +++ b/packages/hal/mips/sim/current/src/plf_misc.c @@ -53,4 +53,13 @@ void hal_platform_init(void) } /*------------------------------------------------------------------------*/ +/* Location to save interrupt state in for debug purposes. */ + +#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) + +struct Hal_SavedRegisters *hal_saved_interrupt_state; + +#endif + +/*------------------------------------------------------------------------*/ /* End of plf_misc.c */
--- a/packages/hal/mips/tx39/current/ChangeLog +++ b/packages/hal/mips/tx39/current/ChangeLog @@ -1,3 +1,11 @@ +1999-06-18 Nick Garnett <nickg@cygnus.co.uk> + + * include/var_intr.h: Added TX39 specific variant of + HAL_CLOCK_LATENCY(). + + * include/var_cache.h: Added TX39 specific implementation of + HAL_ICACHE_INVALIDATE_ALL(). + 1999-06-16 Jesper Skov <jskov@cygnus.co.uk> CR 100804 workaround * src/mips_tx39.ld: Suppress .mdebug in the final output.
--- a/packages/hal/mips/tx39/current/include/var_cache.h +++ b/packages/hal/mips/tx39/current/include/var_cache.h @@ -255,6 +255,25 @@ //----------------------------------------------------------------------------- // Instruction cache line control +// On the TX39, the instruction cache must be disabled to use the index-invalidate +// cache operation. + +// Invalidate the entire cache +// This uses the index-invalidate cache operation. +#define HAL_ICACHE_INVALIDATE_ALL_DEFINED +#define HAL_ICACHE_INVALIDATE_ALL() \ +{ \ + register CYG_ADDRESS _baddr_ = 0x80000000; \ + register CYG_ADDRESS _addr_ = 0x80000000; \ + register CYG_WORD _state_; \ + HAL_ICACHE_IS_ENABLED(_state_); \ + HAL_ICACHE_DISABLE(); \ + for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \ + { \ + asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); \ + } \ + if( _state_ ) HAL_ICACHE_ENABLE(); \ +} // Invalidate cache lines in the given range without writing to memory. // This uses the index-invalidate cache operation since the TX39 does not @@ -264,15 +283,17 @@ { \ register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_ICACHE_IS_ENABLED(_state_); \ HAL_ICACHE_DISABLE(); \ for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ { \ asm volatile ("cache 0,0(%0)" : : "r"(_addr_) ); \ } \ - HAL_ICACHE_ENABLE(); \ + if( _state_ ) HAL_ICACHE_ENABLE(); \ } -#endif +#endif // CYGPKG_HAL_MIPS_TX3904 //----------------------------------------------------------------------------- #endif // ifndef CYGONCE_IMP_CACHE_H
--- a/packages/hal/mips/tx39/current/include/var_intr.h +++ b/packages/hal/mips/tx39/current/include/var_intr.h @@ -230,6 +230,11 @@ CYG_MACRO_END #endif +#if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && \ + !defined(HAL_CLOCK_LATENCY) +#define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ(_pvalue_) +#endif + #define CYGHWR_HAL_CLOCK_CONTROL_DEFINED #else
--- a/packages/hal/powerpc/arch/current/ChangeLog +++ b/packages/hal/powerpc/arch/current/ChangeLog @@ -1,3 +1,22 @@ +1999-06-24 Jesper Skov <jskov@cygnus.co.uk> + + * misc/CPUMask8xx.c: Added. + +1999-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * src/vectors.S (_start): Support breaking back into the stub ROM + when we see a breakpoint, if RAM start and RAM-based vectors for + the stub. Rather than using a direct jump, instead skip copying + the program exception vectors - leave the stub's vec in place. + Controlled by CYGPRI_STUBROM_HAS_RAM_VECTORS, which varies from + platform to platform. + +1999-06-18 Hugo Tyson <hmt@cygnus.co.uk> + + * src/hal_misc.c (hal_enable_caches): Change the configuration, + the better to accommodate differing platform requirements viz a + viz cache enabling and so on. + 1999-06-17 Hugo Tyson <hmt@cygnus.co.uk> * src/vectors.S (CYG_MSR): define correctly for copying vectors,
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/arch/current/misc/CPUMask8xx.c @@ -0,0 +1,60 @@ +//========================================================================== +// +// CPUMask8xx.c +// +// Print PowerPC 8xx CPU Mask revision +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 1999-06-24 +// Description: Prints the CPU Part and Mask numbers. +// See http://www.mot.com/SPS/RISC/netcomm/aesop/mpc8XX/860/860revs.htm +//####DESCRIPTIONEND#### + +#include <cyg/infra/diag.h> +#include <cyg/hal/ppc_regs.h> +#include <cyg/hal/hal_io.h> + +#define DPRAM_BASE 0x2000 +#define CPM_MISC_BASE (DPRAM_BASE + 0x1cb0) + +externC void +cyg_start( void ) +{ + cyg_uint32 immr, part_no, mcrev_no; + + asm volatile ("mfspr %0, %1;": "=r" (immr): "I" (CYGARC_REG_IMMR)); + + part_no = (immr & (CYGARC_REG_IMMR_PARTNUM|CYGARC_REG_IMMR_MASKNUM)); + + HAL_READ_UINT16((immr&CYGARC_REG_IMMR_BASEMASK)+CPM_MISC_BASE, mcrev_no); + + diag_printf("MPC8xx IMMR[16:31]/Part# %04x, " + "Microcode Rev No# %04x\n", part_no, mcrev_no); +} +// EOF CPUMask8xx.c
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/arch/current/misc/PKGconf.mak @@ -0,0 +1,38 @@ +#=============================================================================== +# +# makefile +# +# hal/powerpc/arch/misc +# +#=============================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +#=============================================================================== + +PACKAGE := hal_powerpc +include ../../../../../pkgconf/pkgconf.mak + +PROGS := CPUMask8xx +OTHER_PROGS := +WHEREAMI := misc + +include $(COMPONENT_REPOSITORY)/pkgconf/makrules.prv
--- a/packages/hal/powerpc/arch/current/src/hal_misc.c +++ b/packages/hal/powerpc/arch/current/src/hal_misc.c @@ -42,7 +42,10 @@ // //=========================================================================== +#include <pkgconf/system.h> #include <pkgconf/hal.h> +#include CYGBLD_HAL_TARGET_H +#include CYGBLD_HAL_PLATFORM_H #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS #include <cyg/hal/ppc_regs.h> // SPR definitions @@ -115,6 +118,7 @@ cyg_hal_exception_handler(HAL_SavedRegis __handle_exception(); + #elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ defined(CYGPKG_HAL_EXCEPTIONS) int vector = regs->vector>>8; @@ -407,10 +411,27 @@ externC void hal_MMU_init (void) //--------------------------------------------------------------------------- // Initial cache enabling + +// These are "indirected" to make it easier to support other platform +// variants in the future: + +#ifdef CYGPKG_HAL_POWERPC_COGENT +# define CYGPRI_INIT_CACHES 1 +# ifdef CYG_HAL_STARTUP_RAM +# define CYGPRI_ENABLE_CACHES 1 +# endif +#endif + + +// Do not enable caches for the FADS port pro tem; the memory mapping is +// not set up. + +// Do not enable caches for the simulator, it just slows it down. + externC void hal_enable_caches(void) { -#ifdef CYGPKG_HAL_POWERPC_COGENT +#ifdef CYGPRI_INIT_CACHES // Initialize caches. HAL_ICACHE_UNLOCK_ALL(); HAL_DCACHE_UNLOCK_ALL(); @@ -418,7 +439,7 @@ hal_enable_caches(void) HAL_DCACHE_INVALIDATE_ALL(); // Enable caches. -#if defined(CYG_HAL_STARTUP_RAM) +#ifdef CYGPRI_ENABLE_CACHES // Cogent board doesn't support burst access to the ROM and on the // MPC8xx caches require burst. HAL_ICACHE_ENABLE();
--- a/packages/hal/powerpc/arch/current/src/vectors.S +++ b/packages/hal/powerpc/arch/current/src/vectors.S @@ -183,6 +183,11 @@ reset_vector: # the GDB stub. # It is _not_ a generic solution to the problem; in particular it # is not possible to continue after a breakpoint is hit. + # + # Note that for platforms where StubROM vectors are copied into RAM + # at 0x00000000, simply skipping the copy of vector 0x700 is a + # better solution. See CYGPRI_STUBROM_HAS_RAM_VECTORS below. + .p2align 8 .globl __exception_program __exception_program: @@ -289,11 +294,25 @@ 2: #endif -#ifdef CYG_HAL_POWERPC_COPY_VECTORS // only for CygMon-supported startup +#ifdef CYG_HAL_POWERPC_COPY_VECTORS // only for StubRom-supported startup + + +#ifdef CYGPRI_STUBROM_HAS_RAM_VECTORS +# ifdef CYG_HAL_STARTUP_RAM +# ifndef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +# define CYGPRI_SKIP_BREAKPOINT_VECTOR +# endif // no stubs +# endif // RAM startup +#endif // Stubrom vectors are in RAM + # Copy RAM exception vectors from ROM (or load place) to RAM lwi r3,rom_vectors # r3 = rom start lwi r4,0 # r4 = ram start +#ifdef CYGPRI_SKIP_BREAKPOINT_VECTOR + lwi r5,__exception_program # r5 = end of first leg of copy +#else lwi r5,rom_vectors_end # r5 = rom end +#endif cmplw r3,r5 # skip if no vectors beq 2f @@ -306,6 +325,15 @@ 1: cmplw r3,r5 # compare blt 1b # loop if not yet done 2: +#ifdef CYGPRI_SKIP_BREAKPOINT_VECTOR + cmplwi r4,__exception_program@L + bne 3f # is it the breakpoint vector? + addi r4,r4,0x100 # if so, leave it well alone + addi r3,r3,0x100 + lwi r5,rom_vectors_end # r5 = rom end + b 1b # and do the rest of the copy +3: +#endif // Skip copying the breakpoint vector #endif # clear BSS
--- a/packages/io/serial/current/ChangeLog +++ b/packages/io/serial/current/ChangeLog @@ -1,3 +1,12 @@ +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Some clean up (removed commented + obsolete CDL parenting structure). + + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + 1999-05-27 Jesper Skov <jskov@cygnus.co.uk> * tests/ser_test_protocol.inl: Added ability to change options in
--- a/packages/io/serial/current/include/pkgconf/io_serial.h +++ b/packages/io/serial/current/include/pkgconf/io_serial.h @@ -189,7 +189,6 @@ display "ARM PID serial device drivers" type bool requires CYGPKG_IO_SERIAL -# parent CYGPKG_IO_SERIAL parent CYGPKG_HAL_ARM_PID description " This option enables the serial device drivers for the ARM PID." @@ -290,7 +289,6 @@ display "ARM AEB-1 serial device drivers" type bool requires CYGPKG_IO_SERIAL -# parent CYGPKG_IO_SERIAL parent CYGPKG_HAL_ARM_AEB description " This option enables the serial device drivers for the ARM AEB-1." @@ -392,7 +390,6 @@ display "Cogent PowerPC serial device drivers" type bool requires CYGPKG_IO_SERIAL -# parent CYGPKG_IO_SERIAL parent CYGPKG_HAL_POWERPC_COGENT description " This option enables the serial device drivers for the Cogent PowerPC." @@ -491,13 +488,13 @@ #define CYGNUM_IO_SERIAL_POWERPC_COGENT_SERIAL_B_BAUD 38400 #define CYGNUM_IO_SERIAL_POWERPC_COGENT_SERIAL_B_BUFSIZE 128 + /* ---------------------------------------------------------------------------- {{CFG_DATA cdl_component CYGPKG_IO_SERIAL_SPARCLITE_SLEB { display "SPARClite SLEB serial device drivers" type bool requires CYGPKG_IO_SERIAL -# parent CYGPKG_IO_SERIAL parent CYGPKG_HAL_SPARCLITE_SLEB description " This option enables the serial device drivers for the SPARClite SLEB." @@ -601,7 +598,6 @@ display "TX39 JMR3904 serial device drivers" type bool requires CYGPKG_IO_SERIAL -# parent CYGPKG_IO_SERIAL parent CYGPKG_HAL_MIPS_TX39_JMR3904 description " This option enables the serial device drivers for the TX39 JMR3904." @@ -720,7 +716,6 @@ display "MN10300 serial device drivers" type bool requires CYGPKG_IO_SERIAL -# parent CYGPKG_IO_SERIAL parent CYGPKG_HAL_MN10300 description " This option enables the serial device drivers for the MN10300."
--- a/packages/io/serial/current/src/arm/aeb_serial.c +++ b/packages/io/serial/current/src/arm/aeb_serial.c @@ -46,13 +46,12 @@ #include <cyg/hal/hal_intr.h> #include <cyg/io/devtab.h> #include <cyg/io/serial.h> +#include <cyg/infra/diag.h> #ifdef CYGPKG_IO_SERIAL_ARM_AEB #include "aeb_serial.h" -extern void diag_printf(const char *fmt, ...); - typedef struct aeb_serial_info { CYG_ADDRWORD base; CYG_WORD int_num;
--- a/packages/io/serial/current/src/arm/pid_serial_with_ints.c +++ b/packages/io/serial/current/src/arm/pid_serial_with_ints.c @@ -29,10 +29,10 @@ //========================================================================== //#####DESCRIPTIONBEGIN#### // -// Author(s): gthomas -// Contributors: gthomas -// Date: 1999-02-04 -// Purpose: PID Serial I/O module (interrupt driven version) +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-02-04 +// Purpose: PID Serial I/O module (interrupt driven version) // Description: // //####DESCRIPTIONEND#### @@ -46,13 +46,11 @@ #include <cyg/hal/hal_intr.h> #include <cyg/io/devtab.h> #include <cyg/io/serial.h> +#include <cyg/infra/diag.h> #ifdef CYGPKG_IO_SERIAL_ARM_PID - #include "pid_serial.h" -extern void diag_printf(const char *fmt, ...); - typedef struct pid_serial_info { CYG_ADDRWORD base; CYG_WORD int_num;
--- a/packages/kernel/current/ChangeLog +++ b/packages/kernel/current/ChangeLog @@ -1,3 +1,21 @@ +1999-06-23 Jesper Skov <jskov@cygnus.co.uk> + PR 20209 + * tests/dhrystone.c: Use fewer loops on ARM targets - they don't + have a cache. + +1999-06-22 Nick Garnett <nickg@cygnus.co.uk> + + * src/intr/intr.cxx (Cyg_Interrupt::chain_isr): Was testing the wrong + macro for the default ISR. Fixed. + + * src/common/clock.cxx (Cyg_RealTimeClock::isr): Add HANDLED bit + to returned value. + +1999-06-21 Jesper Skov <jskov@cygnus.co.uk> + PR 20209 + * tests/dhrystone.c: Don't run test on sims or synthetic target. + Only run test when compiled with optimization. + 1999-06-18 Jesper Skov <jskov@cygnus.co.uk> * tests/dhrystone.c: Added unsupported header.
--- a/packages/kernel/current/src/common/clock.cxx +++ b/packages/kernel/current/src/common/clock.cxx @@ -694,7 +694,7 @@ cyg_uint32 Cyg_RealTimeClock::isr(cyg_ve Cyg_Interrupt::acknowledge_interrupt(CYGNUM_HAL_INTERRUPT_RTC); - return Cyg_Interrupt::CALL_DSR; + return Cyg_Interrupt::CALL_DSR|Cyg_Interrupt::HANDLED; } // -------------------------------------------------------------------------
--- a/packages/kernel/current/src/intr/intr.cxx +++ b/packages/kernel/current/src/intr/intr.cxx @@ -340,7 +340,7 @@ Cyg_Interrupt::chain_isr(cyg_vector vect p = p->next; } -#ifdef CYG_HAL_DEFAULT_ISR +#ifdef HAL_DEFAULT_ISR if( (isr_ret & Cyg_Interrupt::HANDLED) == 0 ) { // If we finished the loop for some reason other than that an @@ -348,7 +348,7 @@ Cyg_Interrupt::chain_isr(cyg_vector vect // report the spurious interrupt, or do some other HAL level processing // such as GDB interrupt detection etc. - CYG_HAL_DEFAULT_ISR( vector, NULL ); + HAL_DEFAULT_ISR( vector, NULL ); } #endif return 0;
--- a/packages/kernel/current/tests/dhrystone.c +++ b/packages/kernel/current/tests/dhrystone.c @@ -18,12 +18,6 @@ // should be directed to the 'ecos-discuss' mailing list (see // http://sourceware.cygnus.com/ecos/intouch.html for details). // -// Contributed by: Kevin Hester <khester@opticworks.com> -// Maintained by: <Unmaintained> -// See also: -// Motorola's "Example Software Initializing the SMC as a UART" package -// (smc2.zip) at: -// http://www.mot.com/SPS/RISC/netcomm/tools/index.html#MPC860_table // ------------------------------------------- // //####UNSUPPORTEDEND#### @@ -46,6 +40,8 @@ #if defined(CYGFUN_KERNEL_API_C) \ && defined(CYGSEM_LIBC_STDIO_PRINTF_FLOATING_POINT) +#ifdef __OPTIMIZE__ + #include <cyg/hal/hal_cache.h> #include <cyg/kernel/kapi.h> #include <stdlib.h> @@ -58,7 +54,11 @@ dtime(void) } // Number of loops to run. -#define PASSES 500000 +#if defined(CYGPKG_HAL_ARM_AEB) || defined(CYGPKG_HAL_ARM_PID) +#define PASSES 100000 +#else +#define PASSES 400000 +#endif // Used in the code below to mark changes to the code. #define __ECOS__ @@ -584,7 +584,19 @@ int main (void) REG int Run_Index; REG int Number_Of_Runs; -#ifndef __ECOS__ + +#ifdef __ECOS__ + + CYG_TEST_INIT(); + +#ifdef CYG_HAL_I386_LINUX + CYG_TEST_NA("Only runs on hardware..."); +#else + if (cyg_test_is_simulator) + CYG_TEST_NA("Only runs on hardware..."); +#endif + +#else // __ECOS__ FILE *Ap; /* Initializations */ @@ -1138,11 +1150,15 @@ Enumeration Enum_Par_Val; } /* Func_3 */ #else -#define NA_MSG "CYGFUN_KERNEL_API_C && CYGSEM_LIBC_STDIO_PRINTF_FLOATING_POINT" +#define NA_MSG "Only makes sense to run with optimized code" +#endif // __OPTIMIZE__ + +#else +#define NA_MSG "Requires CYGFUN_KERNEL_API_C && CYGSEM_LIBC_STDIO_PRINTF_FLOATING_POINT" #endif // CYGFUN_KERNEL_API_C && CYGSEM_LIBC_STDIO_PRINTF_FLOATING_POINT #else -#define NA_MSG "CYGPKG_KERNEL && CYGPKG_LIBC" +#define NA_MSG "Requires CYGPKG_KERNEL && CYGPKG_LIBC" #endif // CYGPKG_KERNEL && CYGPKG_LIBC #ifdef NA_MSG @@ -1150,6 +1166,6 @@ externC void cyg_start( void ) { CYG_TEST_INIT(); - CYG_TEST_NA("Requires " NA_MSG); + CYG_TEST_NA(NA_MSG); } #endif