Mercurial > ecos
changeset 70:c5536bad4c24 ecos-sw-2000-02-11
Merge from eCos master repository on 2000-02-11-15:46:40-GMT
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--- a/packages/ChangeLog +++ b/packages/ChangeLog @@ -1,3 +1,19 @@ +2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> + + * targets: Fix up some accidental reversions + +2000-02-10 Nick Garnett <nickg@cygnus.co.uk> + + * targets: + * packages: + Added appropriate entries for i386 PC target. + +2000-02-07 Jesper Skov <jskov@redhat.com> + + * targets: + * packages: + Added PPC variants. + 1999-12-02 Mark Salter <msalter@cygnus.com> * targets: Added cma222 platform.
--- a/packages/NEWS +++ b/packages/NEWS @@ -90,6 +90,12 @@ The eCos idle loop will not load the host system anymore (except in special configurations, see linux_misc.c). +*** PowerPC + Major revamp of exception handling - _not_ backwards + compatible (see vectors.S for the reasoning behind the + change). + Introduced variant hierarchies. + *** Sparclite Where supported by the targetted platform, it is now possible to use
--- a/packages/hal/arm/aeb/current/ChangeLog +++ b/packages/hal/arm/aeb/current/ChangeLog @@ -1,3 +1,12 @@ +2000-02-10 Jesper Skov <jskov@redhat.com> + + * include/plf_stub.h: + HAL_STUB_PLATFORM_STUBS_INIT->HAL_STUB_PLATFORM_INIT + + * misc/STUBS_config: + * include/pkgconf/hal_arm_aeb.h: + Removed stubs as a legal startup type. + 2000-01-27 John Dallaway <jld@cygnus.co.uk> * include/pkgconf/mlt_arm_aeb_rom.ldi,
--- a/packages/hal/arm/aeb/current/include/pkgconf/hal_arm_aeb.h +++ b/packages/hal/arm/aeb/current/include/pkgconf/hal_arm_aeb.h @@ -82,7 +82,7 @@ parent CYGPKG_HAL_ARM_AEB #type count type enum - legal_values ram rom stubs + legal_values ram rom startup description " When targetting the AEB-1 eval board it is possible to build @@ -90,8 +90,7 @@ 'ram' when building programs to load into RAM using onboard debug software such as Angel or eCos GDB stubs. Select 'rom' when building a stand-alone application which will be put - into ROM. Selection of 'stubs' is for the special case of - building the eCos GDB stubs themselves." + into ROM." } }}CFG_DATA */
--- a/packages/hal/arm/aeb/current/include/plf_stub.h +++ b/packages/hal/arm/aeb/current/include/plf_stub.h @@ -70,7 +70,7 @@ extern int hal_aeb_interruptible(int); //---------------------------------------------------------------------------- // Stub initializer. -#define HAL_STUB_PLATFORM_STUBS_INIT() CYG_EMPTY_STATEMENT +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT //---------------------------------------------------------------------------- // Reset.
--- a/packages/hal/arm/aeb/current/misc/STUBS_config +++ b/packages/hal/arm/aeb/current/misc/STUBS_config @@ -26,8 +26,8 @@ else exit 1 fi -$TCL $1/pkgconf.tcl \ - --target=arm --platform=${AEB} --startup=stubs \ +$TCL $1/pkgconf.tcl \ + --target=arm --platform=${AEB} --startup=rom \ --disable CYGPKG_KERNEL --disable CYGPKG_UITRON \ --disable CYGPKG_LIBC --disable CYGPKG_LIBM \ --disable CYGPKG_ERROR --disable CYGPKG_IO \ @@ -35,18 +35,36 @@ fi --disable CYGPKG_DEVICES_WATCHDOG patch <<END_OF_PATCH -p0 ---- pkgconf/hal.h.orig Fri Oct 22 09:32:14 1999 -+++ pkgconf/hal.h Wed Oct 27 11:15:09 1999 -@@ -110,7 +110,7 @@ +--- pkgconf/hal.h.orig Thu Feb 10 09:05:07 2000 ++++ pkgconf/hal.h Thu Feb 10 09:04:56 2000 +@@ -122,7 +122,7 @@ } }}CFG_DATA */ -#define CYGFUN_HAL_COMMON_KERNEL_SUPPORT -+#undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT ++#undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT + #undef CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL + + #ifdef CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL +@@ -243,7 +243,7 @@ + #define CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096 + #undef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING +-#define CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT ++#undef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + #undef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN + #undef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS + +@@ -272,7 +272,7 @@ + } + + }}CFG_DATA */ +-#define CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM ++#undef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM /* {{CFG_DATA - -@@ -382,10 +382,10 @@ + +@@ -423,10 +423,10 @@ }}CFG_DATA */ @@ -60,6 +78,15 @@ patch <<END_OF_PATCH -p0 /* * NOTE: +@@ -522,7 +522,7 @@ + + + /* Enable this when configuring as a ROM monitor (i.e., stub) */ +-#undef CYGSEM_HAL_ROM_MONITOR ++#define CYGSEM_HAL_ROM_MONITOR + + #include CYGBLD_HAL_TARGET_H + #include CYGBLD_HAL_PLATFORM_H END_OF_PATCH make
--- a/packages/hal/arm/arch/current/ChangeLog +++ b/packages/hal/arm/arch/current/ChangeLog @@ -1,3 +1,8 @@ +2000-02-10 Jesper Skov <jskov@redhat.com> + + * src/vectors.S (reset_platform): + Removed handling of stubs startup type. + 2000-02-01 Jesper Skov <jskov@redhat.com> * src/vectors.S: Treat ROM startup+ROM monitor as STUBS startup.
--- a/packages/hal/arm/arch/current/src/vectors.S +++ b/packages/hal/arm/arch/current/src/vectors.S @@ -229,7 +229,7 @@ 10: LED 4 -#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) +#if defined(CYG_HAL_STARTUP_ROM) // Set up reset vector ldr r2,[r1,#0x00] // reset vector intstruction str r2,[r0,#0x00] @@ -324,7 +324,7 @@ 2: .global reset_platform .type reset_platform,function reset_platform: -#if defined(CYG_HAL_STARTUP_STUBS) || defined(CYGSEM_HAL_ROM_MONITOR) +#ifdef CYGSEM_HAL_ROM_MONITOR // initialize CPSR (machine state register) mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) msr cpsr,r0
--- a/packages/hal/arm/cma230/current/ChangeLog +++ b/packages/hal/arm/cma230/current/ChangeLog @@ -1,3 +1,12 @@ +2000-02-10 Jesper Skov <jskov@redhat.com> + + * include/plf_stub.h: + HAL_STUB_PLATFORM_STUBS_INIT->HAL_STUB_PLATFORM_INIT + + * misc/STUBS_config: + * include/pkgconf/hal_arm_cma230.h: + Removed stubs as a legal startup type. + 1999-12-02 Mark Salter <msalter@cygnus.com> * include/hal_platform_setup.h: Add support for CMA222 (ARM710T).
--- a/packages/hal/arm/cma230/current/include/pkgconf/hal_arm_cma230.h +++ b/packages/hal/arm/cma230/current/include/pkgconf/hal_arm_cma230.h @@ -62,7 +62,7 @@ parent CYGPKG_HAL_ARM_CMA230 #type count type enum - legal_values ram rom stubs + legal_values ram rom startup description " When targetting the CMA230 board it is possible to build @@ -70,8 +70,7 @@ 'ram' when building programs to load into RAM using onboard debug software such as Angel or eCos GDB stubs. Select 'rom' when building a stand-alone application which will be put - into ROM. Selection of 'stubs' is for the special case of - building the eCos GDB stubs themselves." + into ROM." } }}CFG_DATA */
--- a/packages/hal/arm/cma230/current/include/plf_stub.h +++ b/packages/hal/arm/cma230/current/include/plf_stub.h @@ -70,7 +70,7 @@ extern int hal_cma230_interruptible(int //---------------------------------------------------------------------------- // Stub initializer. -#define HAL_STUB_PLATFORM_STUBS_INIT() CYG_EMPTY_STATEMENT +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT //---------------------------------------------------------------------------- // Reset.
--- a/packages/hal/arm/cma230/current/misc/STUBS_config +++ b/packages/hal/arm/cma230/current/misc/STUBS_config @@ -26,18 +26,36 @@ fi --disable CYGPKG_DEVICES_WATCHDOG patch <<END_OF_PATCH -p0 ---- pkgconf/hal.h.orig Fri Oct 22 09:32:14 1999 -+++ pkgconf/hal.h Wed Oct 27 11:15:09 1999 -@@ -110,7 +110,7 @@ +--- pkgconf/hal.h.orig Thu Feb 10 09:05:07 2000 ++++ pkgconf/hal.h Thu Feb 10 09:04:56 2000 +@@ -122,7 +122,7 @@ } }}CFG_DATA */ -#define CYGFUN_HAL_COMMON_KERNEL_SUPPORT -+#undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT ++#undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT + #undef CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL + + #ifdef CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL +@@ -243,7 +243,7 @@ + #define CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096 + #undef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING +-#define CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT ++#undef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + #undef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN + #undef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS + +@@ -272,7 +272,7 @@ + } + + }}CFG_DATA */ +-#define CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM ++#undef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM /* {{CFG_DATA - -@@ -382,10 +382,10 @@ + +@@ -423,10 +423,10 @@ }}CFG_DATA */ @@ -51,6 +69,15 @@ patch <<END_OF_PATCH -p0 /* * NOTE: +@@ -522,7 +522,7 @@ + + + /* Enable this when configuring as a ROM monitor (i.e., stub) */ +-#undef CYGSEM_HAL_ROM_MONITOR ++#define CYGSEM_HAL_ROM_MONITOR + + #include CYGBLD_HAL_TARGET_H + #include CYGBLD_HAL_PLATFORM_H END_OF_PATCH make
--- a/packages/hal/arm/edb7xxx/current/ChangeLog +++ b/packages/hal/arm/edb7xxx/current/ChangeLog @@ -1,3 +1,18 @@ +2000-02-10 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/dram_test.c: Include proper testing infrastructure to + make farm happy. + +2000-02-10 Jesper Skov <jskov@redhat.com> + + * include/plf_stub.h: + HAL_STUB_PLATFORM_STUBS_INIT->HAL_STUB_PLATFORM_INIT + + * misc/STUBS_config: + * src/hal_diag.c: + * include/pkgconf/hal_arm_edb7xxx.h: + Removed stubs as a legal startup type. + 2000-02-02 Jesper Skov <jskov@redhat.com> * misc/prog_flash.c (program_flash): Added expected argument.
--- a/packages/hal/arm/edb7xxx/current/include/pkgconf/hal_arm_edb7xxx.h +++ b/packages/hal/arm/edb7xxx/current/include/pkgconf/hal_arm_edb7xxx.h @@ -78,7 +78,7 @@ display "Startup type" parent CYGPKG_HAL_ARM_EDB7XXX type enum - legal_values ram rom stubs + legal_values ram rom startup description " When targetting the EDB7XXX eval boards it is possible to build @@ -86,8 +86,7 @@ 'ram' when building programs to load into RAM using onboard debug software such as Angel or eCos GDB stubs. Select 'rom' when building a stand-alone application which will be put - into ROM. Selection of 'stubs' is for the special case of - building the eCos GDB stubs themselves." + into ROM." } }}CFG_DATA */
--- a/packages/hal/arm/edb7xxx/current/include/plf_stub.h +++ b/packages/hal/arm/edb7xxx/current/include/plf_stub.h @@ -70,7 +70,7 @@ extern int hal_edb7xxx_interruptible(in //---------------------------------------------------------------------------- // Stub initializer. -#define HAL_STUB_PLATFORM_STUBS_INIT() CYG_EMPTY_STATEMENT +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT //---------------------------------------------------------------------------- // Reset.
--- a/packages/hal/arm/edb7xxx/current/misc/STUBS_config +++ b/packages/hal/arm/edb7xxx/current/misc/STUBS_config @@ -20,8 +20,8 @@ else exit 1 fi -$TCL $1/pkgconf.tcl \ - --target=arm --platform=${EDB7xxx} --startup=stubs \ +$TCL $1/pkgconf.tcl \ + --target=arm --platform=${EDB7xxx} --startup=rom \ --disable CYGPKG_KERNEL --disable CYGPKG_UITRON \ --disable CYGPKG_LIBC --disable CYGPKG_LIBM \ --disable CYGPKG_ERROR --disable CYGPKG_IO \ @@ -29,12 +29,36 @@ fi --disable CYGPKG_DEVICES_WATCHDOG --disable-cygmon patch <<END_OF_PATCHES -p0 - -// This patch enables GDB stub support - ---- pkgconf/hal.h~ Thu Jul 8 08:26:44 1999 -+++ pkgconf/hal.h Wed Jul 28 10:51:07 1999 -@@ -369,10 +369,10 @@ +--- pkgconf/hal.h.orig Thu Feb 10 09:05:07 2000 ++++ pkgconf/hal.h Thu Feb 10 09:04:56 2000 +@@ -122,7 +122,7 @@ + } + + }}CFG_DATA */ +-#define CYGFUN_HAL_COMMON_KERNEL_SUPPORT ++#undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT + #undef CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL + + #ifdef CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL +@@ -243,7 +243,7 @@ + #define CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096 + #undef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING +-#define CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT ++#undef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + #undef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN + #undef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS + +@@ -272,7 +272,7 @@ + } + + }}CFG_DATA */ +-#define CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM ++#undef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + + /* {{CFG_DATA + +@@ -423,10 +423,10 @@ }}CFG_DATA */ @@ -48,19 +72,17 @@ patch <<END_OF_PATCHES -p0 /* * NOTE: - -// This patch selects statis MMU tables, in ROM +@@ -522,7 +522,7 @@ ---- pkgconf/hal.h~ Mon Nov 22 07:42:33 1999 -+++ pkgconf/hal.h Mon Nov 22 08:33:32 1999 -@@ -348,7 +348,7 @@ - }}CFG_DATA */ + + /* Enable this when configuring as a ROM monitor (i.e., stub) */ +-#undef CYGSEM_HAL_ROM_MONITOR ++#define CYGSEM_HAL_ROM_MONITOR - #define CYGSEM_HAL_INSTALL_MMU_TABLES --#undef CYGSEM_HAL_STATIC_MMU_TABLES -+#define CYGSEM_HAL_STATIC_MMU_TABLES - - /* --------------------------------------------------------------------- - * Options related to source-level debugging and diagnostics. + #include CYGBLD_HAL_TARGET_H + #include CYGBLD_HAL_PLATFORM_H +END_OF_PATCHES -END_OF_PATCHES +make +make -C hal/common/current/src/stubrom +arm-elf-objcopy -O binary hal/common/current/src/stubrom/stubrom stubrom.bin
--- a/packages/hal/arm/edb7xxx/current/src/hal_diag.c +++ b/packages/hal/arm/edb7xxx/current/src/hal_diag.c @@ -76,7 +76,7 @@ // Assumption: all diagnostic output must be GDB packetized unless this is a ROM (i.e. // totally stand-alone) system. -#ifdef CYG_HAL_STARTUP_STUBS +#ifdef CYGSEM_HAL_ROM_MONITOR #define CYG_HAL_STARTUP_ROM #undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS #endif
--- a/packages/hal/arm/edb7xxx/current/tests/dram_test.c +++ b/packages/hal/arm/edb7xxx/current/tests/dram_test.c @@ -40,6 +40,7 @@ #include <pkgconf/kernel.h> // Configuration header #include <cyg/kernel/kapi.h> #include <cyg/infra/diag.h> +#include <cyg/infra/testcase.h> #include <cyg/hal/hal_arch.h> #include CYGHWR_MEMORY_LAYOUT_H // Memory layout @@ -54,12 +55,13 @@ static char stack[STACK_SIZE]; static cyg_thread thread_data; static cyg_handle_t thread_handle; -extern char _end; +extern char __bss_end; int total_errors; int run_errors; int error_count; + #define MAX_ERRORS 5 -#define NUM_RUNS 12 +#define NUM_RUNS 4 #define REFRESH_TIME 5 int decay_time[] = { 50, 100, 200, 500, 1000 }; @@ -68,12 +70,6 @@ int decay_time[] = { 50, 100, 200, 500, // FUNCTIONS static void -cyg_test_exit(void) -{ - while (TRUE) ; -} - -static void new_test(void) { error_count = 0; @@ -278,8 +274,10 @@ dram_exercise(cyg_addrword_t p) cyg_uint32 start_DRAM, end_DRAM; int i; + CYG_TEST_INIT(); + end_DRAM = CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE; - start_DRAM = ((cyg_uint32)&_end + 0x00000FFF) & 0xFFFFF000; + start_DRAM = ((cyg_uint32)&__bss_end + 0x00000FFF) & 0xFFFFF000; diag_printf("DRAM test - start: 0x%08x, end: 0x%08x\n", start_DRAM, end_DRAM); for (i = 0; i < NUM_RUNS; i++) { @@ -295,8 +293,7 @@ dram_exercise(cyg_addrword_t p) diag_printf("\n*** End run, %d errors, %d total errors\n", run_errors, total_errors); } - diag_printf("All done!\n"); - cyg_test_exit(); + CYG_TEST_PASS_FINISH("DRAM testing complete"); } externC void
--- a/packages/hal/arm/pid/current/ChangeLog +++ b/packages/hal/arm/pid/current/ChangeLog @@ -1,3 +1,12 @@ +2000-02-10 Jesper Skov <jskov@redhat.com> + + * include/plf_stub.h: + HAL_STUB_PLATFORM_STUBS_INIT->HAL_STUB_PLATFORM_INIT + + * misc/STUBS_config: + * include/pkgconf/hal_arm_pid.h: + Removed stubs as a legal startup type. + 2000-02-01 Jesper Skov <jskov@redhat.com> * include/plf_stub.h: Changes due to STUBS startup removal.
--- a/packages/hal/arm/pid/current/include/pkgconf/hal_arm_pid.h +++ b/packages/hal/arm/pid/current/include/pkgconf/hal_arm_pid.h @@ -91,7 +91,7 @@ display "Startup type" parent CYGPKG_HAL_ARM_PID type enum - legal_values ram rom stubs + legal_values ram rom startup description " When targetting the PID eval board it is possible to build @@ -99,8 +99,7 @@ 'ram' when building programs to load into RAM using onboard debug software such as Angel or eCos GDB stubs. Select 'rom' when building a stand-alone application which will be put - into ROM. Selection of 'stubs' is for the special case of - building the eCos GDB stubs themselves." + into ROM." } }}CFG_DATA */
--- a/packages/hal/arm/pid/current/include/plf_stub.h +++ b/packages/hal/arm/pid/current/include/plf_stub.h @@ -70,7 +70,7 @@ extern int hal_pid_interruptible(int); //---------------------------------------------------------------------------- // Stub initializer. -#define HAL_STUB_PLATFORM_STUBS_INIT() CYG_EMPTY_STATEMENT +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT //---------------------------------------------------------------------------- // Reset.
--- a/packages/hal/arm/pid/current/misc/STUBS_config +++ b/packages/hal/arm/pid/current/misc/STUBS_config @@ -28,8 +28,8 @@ else exit 1 fi -$TCL $1/pkgconf.tcl \ - --target=arm --platform=${PID} --startup=stubs \ +$TCL $1/pkgconf.tcl \ + --target=arm --platform=${PID} --startup=rom \ --disable CYGPKG_KERNEL --disable CYGPKG_UITRON \ --disable CYGPKG_LIBC --disable CYGPKG_LIBM \ --disable CYGPKG_ERROR --disable CYGPKG_IO \ @@ -37,24 +37,36 @@ fi --disable CYGPKG_DEVICES_WATCHDOG patch <<END_OF_PATCH -p0 ---- pkgconf/hal.h 1999/11/21 14:48:03 1.66 -+++ pkgconf/hal.h 1999/12/15 21:48:53 -@@ -118,11 +118,11 @@ - diagnostic I/O because of the environment. This option - allows for an explicit override in these cases." +--- pkgconf/hal.h.orig Thu Feb 10 09:05:07 2000 ++++ pkgconf/hal.h Thu Feb 10 09:04:56 2000 +@@ -122,7 +122,7 @@ } }}CFG_DATA */ -#define CYGFUN_HAL_COMMON_KERNEL_SUPPORT -+#undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT ++#undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT #undef CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL #ifdef CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL - #if !defined(CYGPKG_HAL_ARM) - #err GDB protocol cannot be explicitly disabled for this platform. -@@ -424,14 +424,14 @@ - to support multi-threaded source level debugging." +@@ -243,7 +243,7 @@ + #define CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096 + #undef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING +-#define CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT ++#undef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + #undef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN + #undef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS + +@@ -272,7 +272,7 @@ } + + }}CFG_DATA */ +-#define CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM ++#undef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + + /* {{CFG_DATA + +@@ -423,10 +423,10 @@ }}CFG_DATA */ @@ -68,9 +80,17 @@ patch <<END_OF_PATCH -p0 /* * NOTE: - * - * Right now there is no easy way to express the ROM monitor options +@@ -522,7 +522,7 @@ + + + /* Enable this when configuring as a ROM monitor (i.e., stub) */ +-#undef CYGSEM_HAL_ROM_MONITOR ++#define CYGSEM_HAL_ROM_MONITOR + + #include CYGBLD_HAL_TARGET_H + #include CYGBLD_HAL_PLATFORM_H END_OF_PATCH make -make misc +make -C hal/common/current/src/stubrom +arm-elf-objcopy -O binary hal/common/current/src/stubrom/stubrom stubrom.bin
--- a/packages/hal/common/current/ChangeLog +++ b/packages/hal/common/current/ChangeLog @@ -1,3 +1,10 @@ +2000-02-10 Jesper Skov <jskov@redhat.com> + + * include/pkgconf/hal.h: Added CYGSEM_HAL_ROM_MONITOR + * src/hal_stub.c (initHardware): CYG_HAL_STARTUP_STUBS -> + CYGSEM_HAL_ROM_MONITOR. + Removed HAL_STUB_PLATFORM_STUBS_INIT. + 2000-02-03 Jesper Skov <jskov@redhat.com> * include/pkgconf/hal.h: CYG_HAL_POWERPC_x->CYGPKG_...
--- a/packages/hal/common/current/include/pkgconf/hal.h +++ b/packages/hal/common/current/include/pkgconf/hal.h @@ -518,6 +518,11 @@ # define CYGPKG_HAL_POWERPC_MPC603 #endif + + +/* Enable this when configuring as a ROM monitor (i.e., stub) */ +#undef CYGSEM_HAL_ROM_MONITOR + #include CYGBLD_HAL_TARGET_H #include CYGBLD_HAL_PLATFORM_H
--- a/packages/hal/common/current/src/hal_stub.c +++ b/packages/hal/common/current/src/hal_stub.c @@ -335,12 +335,6 @@ initHardware (void) // Get interrupt handler initialized. HAL_STUB_PLATFORM_INIT_BREAK_IRQ(); #endif - -#ifdef CYG_HAL_STARTUP_STUBS - // There may be extra initialization required when configured - // for stubs startup. - HAL_STUB_PLATFORM_STUBS_INIT(); -#endif } }
--- a/packages/hal/mn10300/stdeval1/current/ChangeLog +++ b/packages/hal/mn10300/stdeval1/current/ChangeLog @@ -1,3 +1,8 @@ +2000-02-10 Jesper Skov <jskov@redhat.com> + + * include/plf_stub.h: + HAL_STUB_PLATFORM_STUBS_INIT->HAL_STUB_PLATFORM_INIT + 1999-12-21 Jonathan Larmour <jlarmour@cygnus.co.uk> * src/plf_misc.c (hal_platform_init): Rename
--- a/packages/hal/mn10300/stdeval1/current/include/plf_stub.h +++ b/packages/hal/mn10300/stdeval1/current/include/plf_stub.h @@ -70,7 +70,7 @@ extern void hal_stdeval1_init_break_irq( //---------------------------------------------------------------------------- // Stub initializer. -#define HAL_STUB_PLATFORM_STUBS_INIT() CYG_EMPTY_STATEMENT +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT //---------------------------------------------------------------------------- // Reset.
--- a/packages/hal/powerpc/arch/current/ChangeLog +++ b/packages/hal/powerpc/arch/current/ChangeLog @@ -1,3 +1,41 @@ +2000-02-11 Jesper Skov <jskov@redhat.com> + + + * src/hal_intr.c (hal_IRQ_init): Moved code to MPC8xx variant + directory. + + * include/hal_intr.h: Added hal_variant_IRQ_init declaration. + + * tests/PKGconf.mak: + * tests/intr0.c: + Moved intr0 test to MPC8xx variant directory. + +2000-02-10 Jesper Skov <jskov@redhat.com> + + * include/hal_intr.h: Added HAL_VSR_SET_TO_ECOS_HANDLER + + * src/vectors.S: Renamed default VSR handlers. + +2000-02-07 Jesper Skov <jskov@redhat.com> + + * src/vectors.S: Cleaned up vector code a bit. Leave vector + initialization to variant code. + Add a bit of text explaining why exception code was changed. + Get rid of STARTUP_STUBS conditions. + + * src/powerpc.ld: VSR table resides at fixed address. + + * src/hal_misc.c: Fixed compiler warning. + + * include/pkgconf/hal_powerpc.h: Add variant option. + Include variant headers. + + * include/ppc_regs.h: + * include/hal_intr.h: + * include/hal_cache.h: + Moved variant definitions into new variant header files. + + 2000-02-03 Jesper Skov <jskov@redhat.com> * tests/intr0.c:
--- a/packages/hal/powerpc/arch/current/include/hal_cache.h +++ b/packages/hal/powerpc/arch/current/include/hal_cache.h @@ -35,7 +35,7 @@ //#####DESCRIPTIONBEGIN#### // // Author(s): nickg -// Contributors: nickg +// Contributors:nickg, jskov, hmt // Date: 1998-02-17 // Purpose: Cache control API // Description: The macros defined here provide the HAL APIs for handling @@ -54,7 +54,7 @@ #include <cyg/hal/ppc_regs.h> -#include <cyg/hal/plf_cache.h> +#include <cyg/hal/var_cache.h> //============================================================================= @@ -221,326 +221,6 @@ externC cyg_memdesc_t cyg_hal_mem_map[]; //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) -//============================================================================= -// Motorola MPC8xx - -#elif defined(CYGPKG_HAL_POWERPC_MPC8xx) - -//----------------------------------------------------------------------------- -// Cache dimensions - -#if defined(CYGPKG_HAL_POWERPC_MPC860) -// Data cache -#define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes -#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line -#define HAL_DCACHE_WAYS 2 // Associativity of the cache - -// Instruction cache -#define HAL_ICACHE_SIZE 4096 // Size of cache in bytes -#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line -#define HAL_ICACHE_WAYS 2 // Associativity of the cache -#endif // defined(CYGPKG_HAL_POWERPC_MPC860) - -#if defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850) -// Data cache -#define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes -#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line -#define HAL_DCACHE_WAYS 2 // Associativity of the cache - -// Instruction cache -#define HAL_ICACHE_SIZE 2048 // Size of cache in bytes -#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line -#define HAL_ICACHE_WAYS 2 // Associativity of the cache -#endif // defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850) - -#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) -#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) - -//----------------------------------------------------------------------------- -// Global control of data cache - -// Enable the data cache -#define HAL_DCACHE_ENABLE() \ - asm volatile ("sync;" \ - "mtspr %0, %1;" \ - : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CE)) - -// Disable the data cache -#define HAL_DCACHE_DISABLE() \ - asm volatile ("sync;" \ - "mtspr %0, %1;" \ - : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CD)) - -// Invalidate the entire cache -// Note: Any locked lines will not be invalidated. -#define HAL_DCACHE_INVALIDATE_ALL() \ - asm volatile ("sync;" \ - "mtspr %0, %1;" \ - : : "I" (CYGARC_REG_DC_CST), \ - "r" (CYGARC_REG_DC_CMD_IA)) - -// Synchronize the contents of the cache with memory. -#define HAL_DCACHE_SYNC() \ - CYG_MACRO_START \ - cyg_int32 i; \ - for (i = 0; i < HAL_DCACHE_SETS; i++){ \ - asm volatile ("sync;" \ - "mtspr %0, %2;" \ - "mtspr %1, %4;" \ - "mtspr %0, %3;" \ - "mtspr %1, %4;" \ - : /* no output */ \ - : /* %0 */ "I" (CYGARC_REG_DC_ADR), \ - /* %1 */ "I" (CYGARC_REG_DC_CST), \ - /* %2 */ "r" (CYGARC_REG_DC_ADR_WAY0 \ - |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \ - /* %3 */ "r" (CYGARC_REG_DC_ADR_WAY1 \ - |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \ - /* %4 */ "r" (CYGARC_REG_DC_CMD_FL)); \ - } \ - CYG_MACRO_END - -// Query the state of the data cache -#define HAL_DCACHE_IS_ENABLED(_state_) \ - asm volatile ("mfspr %0, %1;" \ - "rlwinm %0,%0,1,31,31;" \ - : "=r" (_state_) : "I" (CYGARC_REG_DC_CST)) - -// Set the data cache refill burst size -//#define HAL_DCACHE_BURST_SIZE(_size_) - -// Set the data cache write mode -//#define HAL_DCACHE_WRITE_MODE( _mode_ ) - -//#define HAL_DCACHE_WRITETHRU_MODE 0 -//#define HAL_DCACHE_WRITEBACK_MODE 1 - - -// Load the contents of the given address range into the data cache -// and then lock the cache so that it stays there. - -// Restrictions: This implementation only allows a single area to be -// locked at any one time. This area must be 2kB or less in size. - -// Implementation: Flush entire cache, then invalidate it. This -// ensures that the fetched data go into way0. - -#define HAL_DCACHE_LOCK(_base_, _size_) \ - CYG_MACRO_START \ - cyg_int32 __scratch; \ - cyg_uint32 __base = (cyg_uint32)(_base_); \ - cyg_int32 __l = ((__base / HAL_DCACHE_LINE_SIZE) % HAL_DCACHE_SETS); \ - cyg_int32 __count = ((_size_) / HAL_DCACHE_LINE_SIZE); \ - HAL_DCACHE_DISABLE(); \ - HAL_DCACHE_SYNC (); \ - HAL_DCACHE_INVALIDATE_ALL (); \ - HAL_DCACHE_ENABLE(); \ - do { \ - asm volatile ("lbz %0,0(%1);" \ - "sync;" \ - "mtspr %2, %4;" \ - "mtspr %3, %5;" \ - : /* %0 */ "=&r" (__scratch) \ - : /* %1 */ "b" (__base), \ - /* %2 */ "I" (CYGARC_REG_DC_ADR), \ - /* %3 */ "I" (CYGARC_REG_DC_CST), \ - /* %4 */ "r" (CYGARC_REG_DC_ADR_WAY0 \ - |(__l<<CYGARC_REG_DC_ADR_SETID_SHIFT)), \ - /* %5 */ "r" (CYGARC_REG_DC_CMD_LL)); \ - __l++; \ - __base += HAL_DCACHE_LINE_SIZE; \ - } while (__count--); \ - CYG_MACRO_END - - -// Undo a previous lock operation - -// Implementation: Unlocks entire cache. - -#define HAL_DCACHE_UNLOCK(_base_, _size_) \ - HAL_DCACHE_UNLOCK_ALL() - - -// Unlock entire cache -#define HAL_DCACHE_UNLOCK_ALL() \ - CYG_MACRO_START \ - asm volatile ("sync;" \ - "mtspr %0, %1;" \ - : : "I" (CYGARC_REG_DC_CST), \ - "r" (CYGARC_REG_DC_CMD_UA)); \ - CYG_MACRO_END - - - -//----------------------------------------------------------------------------- -// Data cache line control - -// Allocate cache lines for the given address range without reading its -// contents from memory. -//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) - -// Write dirty cache lines to memory and invalidate the cache entries -// for the given address range. -#define HAL_DCACHE_FLUSH( _base_ , _size_ ) \ - CYG_MACRO_START \ - cyg_uint32 __base = (cyg_uint32) (_base_); \ - cyg_int32 __size = (cyg_int32) (_size_); \ - while (__size > 0) { \ - asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \ - __base += HAL_DCACHE_LINE_SIZE; \ - __size -= HAL_DCACHE_LINE_SIZE; \ - } \ - CYG_MACRO_END - -// Invalidate cache lines in the given range without writing to memory. -#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \ - CYG_MACRO_START \ - cyg_uint32 __base = (cyg_uint32) (_base_); \ - cyg_int32 __size = (cyg_int32) (_size_); \ - while (__size > 0) { \ - asm volatile ("dcbi 0,%0;sync;" : : "r" (__base)); \ - __base += HAL_DCACHE_LINE_SIZE; \ - __size -= HAL_DCACHE_LINE_SIZE; \ - } \ - CYG_MACRO_END - -// Write dirty cache lines to memory for the given address range. -#define HAL_DCACHE_STORE( _base_ , _size_ ) \ - CYG_MACRO_START \ - cyg_uint32 __base = (cyg_uint32) (_base_); \ - cyg_int32 __size = (cyg_int32) (_size_); \ - while (__size > 0) { \ - asm volatile ("dcbst 0,%0;sync;" : : "r" (__base)); \ - __base += HAL_DCACHE_LINE_SIZE; \ - __size -= HAL_DCACHE_LINE_SIZE; \ - } \ - CYG_MACRO_END - -// Preread the given range into the cache with the intention of reading -// from it later. -#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) \ - CYG_MACRO_START \ - cyg_uint32 __base = (cyg_uint32) (_base_); \ - cyg_int32 __size = (cyg_int32) (_size_); \ - while (__size > 0) { \ - asm volatile ("dcbt 0,%0;" : : "r" (__base)); \ - __base += HAL_DCACHE_LINE_SIZE; \ - __size -= HAL_DCACHE_LINE_SIZE; \ - } \ - CYG_MACRO_END - -// Preread the given range into the cache with the intention of writing -// to it later. -#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) \ - CYG_MACRO_START \ - cyg_uint32 __base = (cyg_uint32) (_base_); \ - cyg_int32 __size = (cyg_int32) (_size_); \ - while (__size > 0) { \ - asm volatile ("dcbtst 0,%0;" : : "r" (__base)); \ - __base += HAL_DCACHE_LINE_SIZE; \ - __size -= HAL_DCACHE_LINE_SIZE; \ - } \ - CYG_MACRO_END - -// Allocate and zero the cache lines associated with the given range. -#define HAL_DCACHE_ZERO( _base_ , _size_ ) \ - CYG_MACRO_START \ - cyg_uint32 __base = (cyg_uint32) (_base_); \ - cyg_int32 __size = (cyg_int32) (_size_); \ - while (__size > 0) { \ - asm volatile ("dcbz 0,%0;" : : "r" (__base)); \ - __base += HAL_DCACHE_LINE_SIZE; \ - __size -= HAL_DCACHE_LINE_SIZE; \ - } \ - CYG_MACRO_END - -//----------------------------------------------------------------------------- -// Global control of Instruction cache - -// Enable the instruction cache -#define HAL_ICACHE_ENABLE() \ - asm volatile ("isync;" \ - "mtspr %0, %1;" \ - "isync" \ - : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CE)) - -// Disable the instruction cache -#define HAL_ICACHE_DISABLE() \ - asm volatile ("isync;" \ - "mtspr %0, %1;" \ - "isync" \ - : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CD)) - -// Invalidate the entire cache -#define HAL_ICACHE_INVALIDATE_ALL() \ - asm volatile ("isync;" \ - "mtspr %0, %1;" \ - "isync" \ - : : "I" (CYGARC_REG_IC_CST), \ - "r" (CYGARC_REG_IC_CMD_IA)) - -// Synchronize the contents of the cache with memory. -#define HAL_ICACHE_SYNC() \ - HAL_ICACHE_INVALIDATE_ALL() - -// Query the state of the instruction cache -#define HAL_ICACHE_IS_ENABLED(_state_) \ - asm volatile ("mfspr %0, %1;" \ - "rlwinm %0,%0,1,31,31;" \ - : "=r" (_state_) : "I" (CYGARC_REG_IC_CST)) - -// Set the instruction cache refill burst size -//#define HAL_ICACHE_BURST_SIZE(_size_) - - -// Load the contents of the given address range into the instruction cache -// and then lock the cache so that it stays there. - -// Restrictions: This implementation only allows a single area to be -// locked at any one time. This area must be 2kB or less in size. - -// Implementation: Flush entire cache, then invalidate it. This -// ensures that the fetched data go into way0. - -#define HAL_ICACHE_LOCK(_base_, _size_) \ - CYG_MACRO_START \ - unsigned long __base = \ - ((unsigned long) (_base_)) & ~(HAL_ICACHE_LINE_SIZE-1); \ - int __count = ((_size_) / HAL_ICACHE_LINE_SIZE); \ - do { \ - asm volatile ("mtspr %0, %2;" \ - "mtspr %1, %3;" \ - "isync;" \ - : /* no output */ \ - : /* %0 */ "I" (CYGARC_REG_IC_ADR), \ - /* %1 */ "I" (CYGARC_REG_IC_CST), \ - /* %2 */ "r" (__base), \ - /* %3 */ "r" (CYGARC_REG_IC_CMD_LL)); \ - __base += HAL_ICACHE_LINE_SIZE; \ - } while (__count--); \ - CYG_MACRO_END - -// Undo a previous lock operation - -// Implementation: Unlocks entire cache. -#define HAL_ICACHE_UNLOCK(_base_, _size_) \ - HAL_ICACHE_UNLOCK_ALL() - -// Unlock entire cache -#define HAL_ICACHE_UNLOCK_ALL() \ - CYG_MACRO_START \ - asm volatile ("sync;" \ - "mtspr %0, %1;" \ - : : "I" (CYGARC_REG_IC_CST), \ - "r" (CYGARC_REG_IC_CMD_UA)); \ - CYG_MACRO_END - -//----------------------------------------------------------------------------- -// Instruction cache line control - -// Invalidate cache lines in the given range without writing to memory. -//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) - #endif //-----------------------------------------------------------------------------
--- a/packages/hal/powerpc/arch/current/include/hal_intr.h +++ b/packages/hal/powerpc/arch/current/include/hal_intr.h @@ -53,11 +53,11 @@ #include <pkgconf/hal.h> -#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_type.h> // types #include <cyg/hal/ppc_regs.h> // register definitions -#include <cyg/hal/hal_io.h> // io macros -#include <cyg/infra/cyg_ass.h> // CYG_FAIL + +#include <cyg/hal/var_intr.h> // variant extensions //-------------------------------------------------------------------------- // PowerPC exception vectors. These correspond to VSRs and are the values @@ -80,9 +80,17 @@ #define CYGNUM_HAL_VECTOR_FP_ASSIST 14 #define CYGNUM_HAL_VSR_MIN CYGNUM_HAL_VECTOR_RESERVED_0 -#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_FP_ASSIST +#ifndef CYGNUM_HAL_VSR_MAX +# define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_FP_ASSIST +#endif #define CYGNUM_HAL_VSR_COUNT ( CYGNUM_HAL_VSR_MAX + 1 ) +#ifndef CYG_VECTOR_IS_INTERRUPT +# define CYG_VECTOR_IS_INTERRUPT(v) \ + (CYGNUM_HAL_VECTOR_INTERRUPT == (v) \ + || CYGNUM_HAL_VECTOR_DECREMENTER == (v)) +#endif + // The decoded interrupts. // Define decrementer as the first interrupt since it is guaranteed to // be defined on all PowerPCs. External may expand into several interrupts @@ -92,31 +100,19 @@ // CYGNUM_HAL_ISR_COUNT must match CYG_ISR_TABLE_SIZE defined in vectors.S. #define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_DECREMENTER -#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_EXTERNAL +#ifndef CYGNUM_HAL_ISR_MAX +# define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_EXTERNAL +#endif #define CYGNUM_HAL_ISR_COUNT ( CYGNUM_HAL_ISR_MAX + 1 ) +#ifndef CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED // Exception vectors. These are the values used when passed out to an // external exception handler using cyg_hal_deliver_exception() #define CYGNUM_HAL_EXCEPTION_RESERVED_0 CYGNUM_HAL_VECTOR_RESERVED_0 - -#ifdef CYGPKG_HAL_POWERPC_MPC860 -// The MPC860 does not generate DSI and ISI: instead it goes to machine -// check, so that a software VM system can then call into vectors 0x300 or -// 0x400 if the address is truly invalid rather than merely not in the TLB -// right now. Shades of IBM wanting to port OS/MVS here! -// See pp 7-9/10 in "PowerQUICC - MPC860 User's Manual" -#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_MACHINE_CHECK -// do not define catchers for DSI and ISI - should never happen. -#else -// Sensible PowerPCs that do what the architecture suggests. See 6-25...29 -// in "PowerPC Microprocessor Family: the Programming Environments" -// (Note: eCos libc does not catch CYGNUM_HAL_EXCEPTION_MACHINE_CHECK) #define CYGNUM_HAL_EXCEPTION_MACHINE_CHECK CYGNUM_HAL_VECTOR_MACHINE_CHECK #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_DSI #define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_ISI -#endif // !CYGPKG_HAL_POWERPC_MPC860 : DSI and ISI exceptions generated - #define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS \ CYGNUM_HAL_VECTOR_ALIGNMENT #define CYGNUM_HAL_EXCEPTION_FPU_NOT_AVAIL CYGNUM_HAL_VECTOR_FP_UNAVAILABLE @@ -126,131 +122,27 @@ #define CYGNUM_HAL_EXCEPTION_TRACE CYGNUM_HAL_VECTOR_TRACE #define CYGNUM_HAL_EXCEPTION_FP_ASSIST CYGNUM_HAL_VECTOR_FP_ASSIST +#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_RESERVED_0 +#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VECTOR_FP_ASSIST + +#define CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED + +#endif // CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED + +// FIXME: This is still rather ugly. Should probably be made variant +// specific using a decode_hal_exception macro or somesuch. // decoded exception vectors #define CYGNUM_HAL_EXCEPTION_TRAP (-1) #define CYGNUM_HAL_EXCEPTION_PRIVILEGED_INSTRUCTION (-2) #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION (-3) #define CYGNUM_HAL_EXCEPTION_FPU (-4) +#undef CYGNUM_HAL_EXCEPTION_MIN #define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_FPU -#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VECTOR_FP_ASSIST -#define CYGNUM_HAL_EXCEPTION_COUNT \ - ( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 ) -#ifdef CYGPKG_HAL_POWERPC_MPC8xx -// Additional exceptions on the MPC8xx -#define CYGNUM_HAL_VECTOR_RESERVED_F 15 -#define CYGNUM_HAL_VECTOR_SW_EMUL 16 -#define CYGNUM_HAL_VECTOR_ITLB_MISS 17 -#define CYGNUM_HAL_VECTOR_DTLB_MISS 18 -#define CYGNUM_HAL_VECTOR_ITLB_ERROR 19 -#define CYGNUM_HAL_VECTOR_DTLB_ERROR 20 -#define CYGNUM_HAL_VECTOR_RESERVED_15 21 -#define CYGNUM_HAL_VECTOR_RESERVED_16 22 -#define CYGNUM_HAL_VECTOR_RESERVED_17 23 -#define CYGNUM_HAL_VECTOR_RESERVED_18 24 -#define CYGNUM_HAL_VECTOR_RESERVED_19 25 -#define CYGNUM_HAL_VECTOR_RESERVED_1A 26 -#define CYGNUM_HAL_VECTOR_RESERVED_1B 27 -#define CYGNUM_HAL_VECTOR_DATA_BP 28 -#define CYGNUM_HAL_VECTOR_INSTRUCTION_BP 29 -#define CYGNUM_HAL_VECTOR_PERIPHERAL_BP 30 -#define CYGNUM_HAL_VECTOR_NMI 31 - -#define CYGNUM_HAL_EXCEPTION_RESERVED_F CYGNUM_HAL_VECTOR_RESERVED_F -#define CYGNUM_HAL_EXCEPTION_SW_EMUL CYGNUM_HAL_VECTOR_SW_EMUL -#define CYGNUM_HAL_EXCEPTION_CODE_TLBMISS_ACCESS CYGNUM_HAL_VECTOR_ITLB_MISS -#define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS CYGNUM_HAL_VECTOR_DTLB_MISS -#define CYGNUM_HAL_EXCEPTION_CODE_TLBERROR_ACCESS \ - CYGNUM_HAL_VECTOR_ITLB_ERROR -#define CYGNUM_HAL_EXCEPTION_DATA_TLBERROR_ACCESS \ - CYGNUM_HAL_VECTOR_DTLB_ERROR -#define CYGNUM_HAL_EXCEPTION_RESERVED_15 CYGNUM_HAL_VECTOR_RESERVED_15 -#define CYGNUM_HAL_EXCEPTION_RESERVED_16 CYGNUM_HAL_VECTOR_RESERVED_16 -#define CYGNUM_HAL_EXCEPTION_RESERVED_17 CYGNUM_HAL_VECTOR_RESERVED_17 -#define CYGNUM_HAL_EXCEPTION_RESERVED_18 CYGNUM_HAL_VECTOR_RESERVED_18 -#define CYGNUM_HAL_EXCEPTION_RESERVED_19 CYGNUM_HAL_VECTOR_RESERVED_19 -#define CYGNUM_HAL_EXCEPTION_RESERVED_1A CYGNUM_HAL_VECTOR_RESERVED_1A -#define CYGNUM_HAL_EXCEPTION_RESERVED_1B CYGNUM_HAL_VECTOR_RESERVED_1B -#define CYGNUM_HAL_EXCEPTION_DATA_BP CYGNUM_HAL_VECTOR_DATA_BP -#define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP CYGNUM_HAL_VECTOR_INSTRUCTION_BP -#define CYGNUM_HAL_EXCEPTION_PERIPHERAL_BP CYGNUM_HAL_VECTOR_PERIPHERAL_BP -#define CYGNUM_HAL_EXCEPTION_NMI CYGNUM_HAL_VECTOR_NMI - -#undef CYGNUM_HAL_EXCEPTION_MAX -#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_NMI - -// The first level of external interrupts -#define CYGNUM_HAL_INTERRUPT_SIU_IRQ0 1 -#define CYGNUM_HAL_INTERRUPT_SIU_LVL0 2 -#define CYGNUM_HAL_INTERRUPT_SIU_IRQ1 3 -#define CYGNUM_HAL_INTERRUPT_SIU_LVL1 4 -#define CYGNUM_HAL_INTERRUPT_SIU_IRQ2 5 -#define CYGNUM_HAL_INTERRUPT_SIU_LVL2 6 -#define CYGNUM_HAL_INTERRUPT_SIU_IRQ3 7 -#define CYGNUM_HAL_INTERRUPT_SIU_LVL3 8 -#define CYGNUM_HAL_INTERRUPT_SIU_IRQ4 9 -#define CYGNUM_HAL_INTERRUPT_SIU_LVL4 10 -#define CYGNUM_HAL_INTERRUPT_SIU_IRQ5 11 -#define CYGNUM_HAL_INTERRUPT_SIU_LVL5 12 -#define CYGNUM_HAL_INTERRUPT_SIU_IRQ6 13 -#define CYGNUM_HAL_INTERRUPT_SIU_LVL6 14 -#define CYGNUM_HAL_INTERRUPT_SIU_IRQ7 15 -#define CYGNUM_HAL_INTERRUPT_SIU_LVL7 16 - -// Further decoded interrups -#define CYGNUM_HAL_INTERRUPT_SIU_TB_A 17 -#define CYGNUM_HAL_INTERRUPT_SIU_TB_B 18 -#define CYGNUM_HAL_INTERRUPT_SIU_PIT 19 -#define CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC 20 -#define CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR 21 -#define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_A_IRQ 22 -#define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_A_CHLVL 23 -#define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_B_IRQ 24 -#define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_B_CHLVL 25 -#define CYGNUM_HAL_INTERRUPT_SIU_CPM 26 - -// Even further... -#define CYGNUM_HAL_INTERRUPT_CPM_PC15 27 -#define CYGNUM_HAL_INTERRUPT_CPM_SCC1 28 -#define CYGNUM_HAL_INTERRUPT_CPM_SCC2 29 -#define CYGNUM_HAL_INTERRUPT_CPM_SCC3 30 -#define CYGNUM_HAL_INTERRUPT_CPM_SCC4 31 -#define CYGNUM_HAL_INTERRUPT_CPM_PC14 32 -#define CYGNUM_HAL_INTERRUPT_CPM_TIMER1 33 -#define CYGNUM_HAL_INTERRUPT_CPM_PC13 34 -#define CYGNUM_HAL_INTERRUPT_CPM_PC12 35 -#define CYGNUM_HAL_INTERRUPT_CPM_SDMA 36 -#define CYGNUM_HAL_INTERRUPT_CPM_IDMA1 37 -#define CYGNUM_HAL_INTERRUPT_CPM_IDMA2 38 -#define CYGNUM_HAL_INTERRUPT_CPM_RESERVED_13 39 -#define CYGNUM_HAL_INTERRUPT_CPM_TIMER2 40 -#define CYGNUM_HAL_INTERRUPT_CPM_RISCTT 41 -#define CYGNUM_HAL_INTERRUPT_CPM_I2C 42 -#define CYGNUM_HAL_INTERRUPT_CPM_PC11 43 -#define CYGNUM_HAL_INTERRUPT_CPM_PC10 44 -#define CYGNUM_HAL_INTERRUPT_CPM_RESERVED_0D 45 -#define CYGNUM_HAL_INTERRUPT_CPM_TIMER3 46 -#define CYGNUM_HAL_INTERRUPT_CPM_PC9 47 -#define CYGNUM_HAL_INTERRUPT_CPM_PC8 48 -#define CYGNUM_HAL_INTERRUPT_CPM_PC7 49 -#define CYGNUM_HAL_INTERRUPT_CPM_RESERVED_08 50 -#define CYGNUM_HAL_INTERRUPT_CPM_TIMER4 51 -#define CYGNUM_HAL_INTERRUPT_CPM_PC6 52 -#define CYGNUM_HAL_INTERRUPT_CPM_SPI 53 -#define CYGNUM_HAL_INTERRUPT_CPM_SMC1 54 -#define CYGNUM_HAL_INTERRUPT_CPM_SMC2_PIP 55 -#define CYGNUM_HAL_INTERRUPT_CPM_PC5 56 -#define CYGNUM_HAL_INTERRUPT_CPM_PC4 57 -#define CYGNUM_HAL_INTERRUPT_CPM_ERROR 58 - -#define CYGNUM_HAL_INTERRUPT_CPM_FIRST CYGNUM_HAL_INTERRUPT_CPM_PC15 -#define CYGNUM_HAL_INTERRUPT_CPM_LAST CYGNUM_HAL_INTERRUPT_CPM_ERROR - -#undef CYGNUM_HAL_ISR_MAX -#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_CPM_LAST -#endif +#define CYGNUM_HAL_EXCEPTION_COUNT \ + ( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 ) // The vector used by the Real time clock #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_DECREMENTER @@ -418,465 +310,24 @@ externC void hal_interrupt_stack_call_pe hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \ CYG_MACRO_END -//-------------------------------------------------------------------------- -// Interrupt controller access - -#ifdef CYGPKG_HAL_POWERPC_MPC860 - -// FIXME: Should probably be put in a separate .inl file?!? - -static __inline__ void -cyg_hal_interrupt_mask ( cyg_uint32 vector ) -{ - switch (vector) { - case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7: - { - // SIU interrupt vectors - cyg_uint32 simask; - - HAL_READ_UINT32 (CYGARC_REG_IMM_SIMASK, simask); - simask &= ~(((cyg_uint32) CYGARC_REG_IMM_SIMASK_IRQ0) - >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0)); - HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIMASK, simask); - break; - } - case CYGNUM_HAL_INTERRUPT_SIU_TB_A: - { - // TimeBase A interrupt - cyg_uint16 tbscr; - - HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFAE); - HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - break; - } - case CYGNUM_HAL_INTERRUPT_SIU_TB_B: - { - // TimeBase B interrupt - cyg_uint16 tbscr; - - HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFBE); - HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - break; - } - case CYGNUM_HAL_INTERRUPT_SIU_PIT: - { - // Periodic Interrupt - cyg_uint16 piscr; - - HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); - piscr &= ~(CYGARC_REG_IMM_PISCR_PIE); - HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr); - break; - } - case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC: - { - // Real Time Clock Second - cyg_uint16 rtcsc; - - HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); - rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SIE); - HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); - break; - } - case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR: - { - // Real Time Clock Alarm - cyg_uint16 rtcsc; - - HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); - rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALE); - HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); - break; - } - // PCMCIA_A_IRQ - // PCMCIA_A_CHLVL - // PCMCIA_B_IRQ - // PCMCIA_B_CHLVL - case CYGNUM_HAL_INTERRUPT_SIU_CPM: - { - // Communications Processor Module - cyg_uint32 cicr; - - HAL_READ_UINT32 (CYGARC_REG_IMM_CICR, cicr); - cicr &= ~(CYGARC_REG_IMM_CICR_IEN); - HAL_WRITE_UINT32 (CYGARC_REG_IMM_CICR, cicr); - break; - } - case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST: - { - // CPM interrupts - cyg_uint32 cimr; - - HAL_READ_UINT32 (CYGARC_REG_IMM_CIMR, cimr); - cimr &= ~(((cyg_uint32) 0x80000000) - >> (vector - CYGNUM_HAL_INTERRUPT_CPM_FIRST)); - HAL_WRITE_UINT32 (CYGARC_REG_IMM_CIMR, cimr); - break; - } - default: - CYG_FAIL("Unknown Interrupt!!!"); - break; - } -} - -static __inline__ void -cyg_hal_interrupt_unmask ( cyg_uint32 vector ) -{ - switch (vector) { - case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7: - { - // SIU interrupt vectors - cyg_uint32 simask; - - HAL_READ_UINT32 (CYGARC_REG_IMM_SIMASK, simask); - simask |= (((cyg_uint32) CYGARC_REG_IMM_SIMASK_IRQ0) - >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0)); - HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIMASK, simask); - break; - } - case CYGNUM_HAL_INTERRUPT_SIU_TB_A: - { - // TimeBase A interrupt - cyg_uint16 tbscr; - - HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - tbscr |= CYGARC_REG_IMM_TBSCR_REFAE; - HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - break; - } - case CYGNUM_HAL_INTERRUPT_SIU_TB_B: - { - // TimeBase B interrupt - cyg_uint16 tbscr; - - HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - tbscr |= CYGARC_REG_IMM_TBSCR_REFBE; - HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - break; - } - case CYGNUM_HAL_INTERRUPT_SIU_PIT: - { - // Periodic Interrupt - cyg_uint16 piscr; - - HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); - piscr |= CYGARC_REG_IMM_PISCR_PIE; - HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr); - break; - } - case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC: - { - // Real Time Clock Second - cyg_uint16 rtcsc; - - HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); - rtcsc |= CYGARC_REG_IMM_RTCSC_SIE; - HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); - break; - } - case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR: - { - // Real Time Clock Alarm - cyg_uint16 rtcsc; - - HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); - rtcsc |= CYGARC_REG_IMM_RTCSC_ALE; - HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); - break; - } - // PCMCIA_A_IRQ - // PCMCIA_A_CHLVL - // PCMCIA_B_IRQ - // PCMCIA_B_CHLVL - case CYGNUM_HAL_INTERRUPT_SIU_CPM: - { - // Communications Processor Module - cyg_uint32 cicr; - - HAL_READ_UINT32 (CYGARC_REG_IMM_CICR, cicr); - cicr |= CYGARC_REG_IMM_CICR_IEN; - HAL_WRITE_UINT32 (CYGARC_REG_IMM_CICR, cicr); - break; - } - case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST: - { - // CPM interrupts - cyg_uint32 cimr; - - HAL_READ_UINT32 (CYGARC_REG_IMM_CIMR, cimr); - cimr |= (((cyg_uint32) 0x80000000) - >> (vector - CYGNUM_HAL_INTERRUPT_CPM_FIRST)); - HAL_WRITE_UINT32 (CYGARC_REG_IMM_CIMR, cimr); - break; - } - default: - CYG_FAIL("Unknown Interrupt!!!"); - break; - } -} - -static __inline__ void -cyg_hal_interrupt_acknowledge ( cyg_uint32 vector ) -{ - switch (vector) { - case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7: - { - // SIU interrupt vectors - cyg_uint32 sipend; - - // When IRQx is configured as an edge interrupt it needs to be - // cleared. Write to INTx and IRQ/level bits are ignore so - // it's safe to do always. - HAL_READ_UINT32 (CYGARC_REG_IMM_SIPEND, sipend); - sipend |= (((cyg_uint32) CYGARC_REG_IMM_SIPEND_IRQ0) - >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0)); - HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIPEND, sipend); - break; - } - case CYGNUM_HAL_INTERRUPT_SIU_TB_A: - { - // TimeBase A interrupt - cyg_uint16 tbscr; - - HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - tbscr |= CYGARC_REG_IMM_TBSCR_REFA; - HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - break; - } - case CYGNUM_HAL_INTERRUPT_SIU_TB_B: - { - // TimeBase B interrupt - cyg_uint16 tbscr; - - HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - tbscr |= CYGARC_REG_IMM_TBSCR_REFB; - HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - break; - } - case CYGNUM_HAL_INTERRUPT_SIU_PIT: - { - // Periodic Interrupt - cyg_uint16 piscr; - - HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); - piscr |= CYGARC_REG_IMM_PISCR_PS; - HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr); - break; - } - case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC: - { - // Real Time Clock Second - cyg_uint16 rtcsc; - - HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); - rtcsc |= CYGARC_REG_IMM_RTCSC_SEC; - HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); - break; - } - case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR: - { - // Real Time Clock Alarm - cyg_uint16 rtcsc; - - HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); - rtcsc |= CYGARC_REG_IMM_RTCSC_ALR; - HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); - break; - } - // PCMCIA_A_IRQ - // PCMCIA_A_CHLVL - // PCMCIA_B_IRQ - // PCMCIA_B_CHLVL - case CYGNUM_HAL_INTERRUPT_SIU_CPM: - // Communications Processor Module - // The CPM interrupts must be acknowledged individually. - break; - case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST: - { - // CPM interrupts - cyg_uint32 cisr; - - HAL_READ_UINT32 (CYGARC_REG_IMM_CISR, cisr); - cisr |= (((cyg_uint32) 0x80000000) - >> (vector - CYGNUM_HAL_INTERRUPT_CPM_FIRST)); - HAL_WRITE_UINT32 (CYGARC_REG_IMM_CISR, cisr); - break; - } - default: - CYG_FAIL("Unknown Interrupt!!!"); - break; - } -} - -static __inline__ void -cyg_hal_interrupt_configure ( cyg_uint32 vector, - cyg_bool level, - cyg_bool up ) -{ - switch (vector) { - case CYGNUM_HAL_INTERRUPT_SIU_IRQ0: - case CYGNUM_HAL_INTERRUPT_SIU_IRQ1: - case CYGNUM_HAL_INTERRUPT_SIU_IRQ2: - case CYGNUM_HAL_INTERRUPT_SIU_IRQ3: - case CYGNUM_HAL_INTERRUPT_SIU_IRQ4: - case CYGNUM_HAL_INTERRUPT_SIU_IRQ5: - case CYGNUM_HAL_INTERRUPT_SIU_IRQ6: - case CYGNUM_HAL_INTERRUPT_SIU_IRQ7: - { - // External interrupts - cyg_uint32 siel, bit; - - CYG_ASSERT( level || !up, "Only falling edge is supported"); - - bit = (((cyg_uint32) CYGARC_REG_IMM_SIEL_IRQ0) - >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0)); - - HAL_READ_UINT32 (CYGARC_REG_IMM_SIEL, siel); - siel &= ~bit; - if (!level) { - // Set edge detect bit. - siel |= bit; - } - HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIEL, siel); - break; - } - case CYGNUM_HAL_INTERRUPT_SIU_LVL0: - case CYGNUM_HAL_INTERRUPT_SIU_LVL1: - case CYGNUM_HAL_INTERRUPT_SIU_LVL2: - case CYGNUM_HAL_INTERRUPT_SIU_LVL3: - case CYGNUM_HAL_INTERRUPT_SIU_LVL4: - case CYGNUM_HAL_INTERRUPT_SIU_LVL5: - case CYGNUM_HAL_INTERRUPT_SIU_LVL6: - case CYGNUM_HAL_INTERRUPT_SIU_LVL7: - case CYGNUM_HAL_INTERRUPT_SIU_TB_A: - case CYGNUM_HAL_INTERRUPT_SIU_TB_B: - case CYGNUM_HAL_INTERRUPT_SIU_PIT: - case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC: - case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR: - // PCMCIA_A_IRQ - // PCMCIA_A_CHLVL - // PCMCIA_B_IRQ - // PCMCIA_B_CHLVL - case CYGNUM_HAL_INTERRUPT_SIU_CPM: - case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST: - // These cannot be configured. - break; - - default: - CYG_FAIL("Unknown Interrupt!!!"); - break; - } -} - -static __inline__ void -cyg_hal_interrupt_set_level ( cyg_uint32 vector, cyg_uint32 level ) -{ - // Note: highest priority has the lowest numerical value. - CYG_ASSERT( level >= CYGARC_SIU_PRIORITY_HIGH, "Invalid priority"); - CYG_ASSERT( level <= CYGARC_SIU_PRIORITY_LOW, "Invalid priority"); - - switch (vector) { - case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7: - // These cannot be configured. - break; - case CYGNUM_HAL_INTERRUPT_SIU_TB_A: - case CYGNUM_HAL_INTERRUPT_SIU_TB_B: - { - // TimeBase A+B interrupt - cyg_uint16 tbscr; - - HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - tbscr &= ~(CYGARC_REG_IMM_TBSCR_IRQMASK); - tbscr |= CYGARC_REG_IMM_TBSCR_IRQ0 >> level; - HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - break; - } - case CYGNUM_HAL_INTERRUPT_SIU_PIT: - { - // Periodic Interrupt - cyg_uint16 piscr; - - HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); - piscr &= ~(CYGARC_REG_IMM_PISCR_IRQMASK); - piscr |= CYGARC_REG_IMM_PISCR_IRQ0 >> level; - HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr); - break; - } - case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC: - case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR: - { - // Real Time Clock Second & Real Time Clock Alarm - cyg_uint16 rtcsc; - - HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); - rtcsc &= ~(CYGARC_REG_IMM_RTCSC_IRQMASK); - rtcsc |= CYGARC_REG_IMM_RTCSC_IRQ0 >> level; - HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); - break; - } - // PCMCIA_A_IRQ - // PCMCIA_A_CHLVL - // PCMCIA_B_IRQ - // PCMCIA_B_CHLVL - case CYGNUM_HAL_INTERRUPT_SIU_CPM: - { - // Communications Processor Module - cyg_uint32 cicr; - - HAL_READ_UINT32 (CYGARC_REG_IMM_CICR, cicr); - cicr &= ~(CYGARC_REG_IMM_CICR_IRQMASK); - cicr |= level << CYGARC_REG_IMM_CICR_IRQ_SHIFT; - HAL_WRITE_UINT32 (CYGARC_REG_IMM_CICR, cicr); - break; - } - case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST: - // CPM interrupt levels are for internal priority. All interrupts - // fed to the CPU use the CPM level set above. - // FIXME: Control of SCdP ordering. - break; - default: - CYG_FAIL("Unknown Interrupt!!!"); - break; - } -} - -// The decrementer interrupt cannnot be masked, configured or acknowledged. - -#define HAL_INTERRUPT_MASK( _vector_ ) \ - CYG_MACRO_START \ - if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ - cyg_hal_interrupt_mask ( (_vector_) ); \ +// This is an ugly name, but what it means is: grab the VSR back to eCos +// internal handling, or if you like, the default handler. But if +// cooperating with GDB and CygMon, the default behaviour is to pass most +// exceptions to CygMon. This macro undoes that so that eCos handles the +// exception. So use it with care. +externC void cyg_hal_default_interrupt_vsr( void ); +externC void cyg_hal_default_exception_vsr( void ); +#define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) \ + CYG_MACRO_START \ + if( (void*)_poldvsr_ != (void*)NULL ) \ + *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \ + hal_vsr_table[_vector_] = ( CYG_VECTOR_IS_INTERRUPT( _vector_ ) \ + ? (CYG_ADDRESS)cyg_hal_default_interrupt_vsr \ + : (CYG_ADDRESS)cyg_hal_default_exception_vsr ); \ CYG_MACRO_END -#define HAL_INTERRUPT_UNMASK( _vector_ ) \ - CYG_MACRO_START \ - if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ - cyg_hal_interrupt_unmask ( (_vector_) ); \ - CYG_MACRO_END -#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ - CYG_MACRO_START \ - if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ - cyg_hal_interrupt_acknowledge ( (_vector_) ); \ - CYG_MACRO_END - -#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \ - CYG_MACRO_START \ - if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ - cyg_hal_interrupt_configure ( (_vector_), (_level_), (_up_) ); \ - CYG_MACRO_END - -#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \ - CYG_MACRO_START \ - if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ - cyg_hal_interrupt_set_level ( (_vector_) , (_level_) ); \ - CYG_MACRO_END - -#else - -// No interrupt configuration possible without interrupt controller. +#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED #define HAL_INTERRUPT_MASK( _vector_ ) @@ -891,22 +342,6 @@ cyg_hal_interrupt_set_level ( cyg_uint32 #endif //-------------------------------------------------------------------------- -// Interrupt arbiters - -#ifdef CYGPKG_HAL_POWERPC_MPC860 - -externC cyg_uint32 hal_arbitration_isr_tb (CYG_ADDRWORD vector, - CYG_ADDRWORD data); -externC cyg_uint32 hal_arbitration_isr_pit (CYG_ADDRWORD vector, - CYG_ADDRWORD data); -externC cyg_uint32 hal_arbitration_isr_rtc (CYG_ADDRWORD vector, - CYG_ADDRWORD data); -externC cyg_uint32 hal_arbitration_isr_cpm (CYG_ADDRWORD vector, - CYG_ADDRWORD data); - -#endif // ifdef CYGPKG_HAL_POWERPC_MPC860 - -//-------------------------------------------------------------------------- // Clock control #define HAL_CLOCK_INITIALIZE( _period_ ) \ @@ -952,5 +387,9 @@ externC cyg_uint32 hal_arbitration_isr_c #endif //-------------------------------------------------------------------------- +// Variant functions +externC void hal_variant_IRQ_init(void); + +//-------------------------------------------------------------------------- #endif // ifndef CYGONCE_HAL_INTR_H // End of hal_intr.h
--- a/packages/hal/powerpc/arch/current/include/pkgconf/hal_powerpc.h +++ b/packages/hal/powerpc/arch/current/include/pkgconf/hal_powerpc.h @@ -54,13 +54,28 @@ target powerpc description " The PowerPC architecture HAL package provides generic - support for this processor architecture. It is also - necessary to select a specific target platform HAL + support for this processor architecture. It is also necessary to + select a CPU variant and a specific target platform HAL package." } + cdl_component CYGFUN_HAL_POWERPC_VARIANTS { + display "PowerPC variants" + type dummy + parent CYGPKG_HAL_POWERPC + description " + A number PowerPC variants are supported." + } + }}CFG_DATA */ +#ifdef CYGPKG_HAL_POWERPC_MPC8xx +# include <pkgconf/hal_powerpc_mpc8xx.h> +#endif +#ifdef CYGPKG_HAL_POWERPC_PPC60x +# include <pkgconf/hal_powerpc_ppc60x.h> +#endif + /* -------------------------------------------------------------------*/ #endif /* CYGONCE_PKGCONF_HAL_POWERPC_H */ /* EOF hal_powerpc.h */
--- a/packages/hal/powerpc/arch/current/include/ppc_regs.h +++ b/packages/hal/powerpc/arch/current/include/ppc_regs.h @@ -52,6 +52,9 @@ #include <pkgconf/hal.h> +#include <cyg/hal/var_regs.h> + + //-------------------------------------------------------------------------- // SPR access macros. #define CYGARC_MTSPR(_spr_, _v_) \ @@ -67,7 +70,7 @@ asm volatile ("mftb %0, %1;" : "=r" (_v_) : "I" (_tbr_)); //-------------------------------------------------------------------------- -// Generic Definitions +// Generic PowerPC Family Definitions //-------------------------------------------------------------------------- //-------------------------------------------------------------------------- @@ -131,350 +134,6 @@ #define TBU_R CYGARC_REG_TBU_R #endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS -//-------------------------------------------------------------------------- -// MPC603 Specific Definitions -//-------------------------------------------------------------------------- -#ifdef CYGPKG_HAL_POWERPC_MPC603 - -//-------------------------------------------------------------------------- -// Cache -#define CYGARC_REG_HID0 1008 - -#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS -#define HID0 CYGARC_REG_HID0 -#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS - - -//-------------------------------------------------------------------------- -// BATs -#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS -#define IBAT0U 528 -#define IBAT0L 529 -#define IBAT1U 530 -#define IBAT1L 531 -#define IBAT2U 532 -#define IBAT2L 533 -#define IBAT3U 534 -#define IBAT3L 535 - -#define DBAT0U 536 -#define DBAT0L 537 -#define DBAT1U 538 -#define DBAT1L 539 -#define DBAT2U 540 -#define DBAT2L 541 -#define DBAT3U 542 -#define DBAT3L 543 - -#define UBAT_BEPIMASK 0xfffe0000 // effective address mask -#define UBAT_BLMASK 0x00001ffc // block length mask -#define UBAT_VS 0x00000002 // supervisor mode valid bit -#define UBAT_VP 0x00000001 // problem mode valid bit - -#define LBAT_BRPNMASK 0xfffe0000 // real address mask -#define LBAT_W 0x00000040 // write-through -#define LBAT_I 0x00000020 // caching-inhibited -#define LBAT_M 0x00000010 // memory coherence -#define LBAT_G 0x00000008 // guarded - -#define LBAT_PP_NA 0x00000000 // no access -#define LBAT_PP_RO 0x00000001 // read-only -#define LBAT_PP_RW 0x00000002 // read/write -#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS - -#endif // ifdef CYGPKG_HAL_POWERPC_MPC603 - -//-------------------------------------------------------------------------- -// MPC8xx Generic Definitions -//-------------------------------------------------------------------------- -#ifdef CYGPKG_HAL_POWERPC_MPC8xx - -//-------------------------------------------------------------------------- -// Instruction cache control. -#define CYGARC_REG_IC_CST 560 -#define CYGARC_REG_IC_ADR 561 -#define CYGARC_REG_IC_DAT 562 - -#define CYGARC_REG_IC_CMD_CE 0x02000000 // cache enable -#define CYGARC_REG_IC_CMD_CD 0x04000000 // cache disable -#define CYGARC_REG_IC_CMD_LL 0x06000000 // load & lock -#define CYGARC_REG_IC_CMD_UL 0x08000000 // unlock line -#define CYGARC_REG_IC_CMD_UA 0x0a000000 // unlock all -#define CYGARC_REG_IC_CMD_IA 0x0c000000 // invalidate all - -#define CYGARC_REG_IC_ADR_SETID_SHIFT 4 // set id is bits 21-27 -#define CYGARC_REG_IC_ADR_WAY0 0x00000000 // select way0 -#define CYGARC_REG_IC_ADR_WAY1 0x00001000 // select way1 - -#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS -#define IC_CST CYGARC_REG_IC_CST -#define IC_ADR CYGARC_REG_IC_ADR -#define IC_DAT CYGARC_REG_IC_DAT - -#define IC_CMD_CE CYGARC_REG_IC_CMD_CE -#define IC_CMD_CD CYGARC_REG_IC_CMD_CD -#define IC_CMD_LL CYGARC_REG_IC_CMD_LL -#define IC_CMD_UL CYGARC_REG_IC_CMD_UL -#define IC_CMD_UA CYGARC_REG_IC_CMD_UA -#define IC_CMD_IA CYGARC_REG_IC_CMD_IA - -#define IC_ADR_SETID_SHIFT CYGARC_REG_IC_ADR_SETID_SHIFT -#define IC_ADR_WAY0 CYGARC_REG_IC_ADR_WAY0 -#define IC_ADR_WAY1 CYGARC_REG_IC_ADR_WAY1 -#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS - -//-------------------------------------------------------------------------- -// Data cache control. -#define CYGARC_REG_DC_CST 568 -#define CYGARC_REG_DC_ADR 569 -#define CYGARC_REG_DC_DAT 570 - -#define CYGARC_REG_DC_CMD_CE 0x02000000 // cache enable -#define CYGARC_REG_DC_CMD_CD 0x04000000 // cache disable -#define CYGARC_REG_DC_CMD_LL 0x06000000 // lock line -#define CYGARC_REG_DC_CMD_UL 0x08000000 // unlock line -#define CYGARC_REG_DC_CMD_UA 0x0a000000 // unlock all -#define CYGARC_REG_DC_CMD_IA 0x0c000000 // invalidate all -#define CYGARC_REG_DC_CMD_FL 0x0e000000 // flush line -#define CYGARC_REG_DC_CMD_SW 0x01000000 // set writethrough -#define CYGARC_REG_DC_CMD_CW 0x03000000 // clear writethrough -#define CYGARC_REG_DC_CMD_SS 0x05000000 // set little endian swap -#define CYGARC_REG_DC_CMD_CS 0x07000000 // clear little endian swap - -#define CYGARC_REG_DC_ADR_SETID_SHIFT 4 // set id is bits 21-27 -#define CYGARC_REG_DC_ADR_WAY0 0x00000000 // select way0 -#define CYGARC_REG_DC_ADR_WAY1 0x00001000 // select way1 - -#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS -#define DC_CST CYGARC_REG_DC_CST -#define DC_ADR CYGARC_REG_DC_ADR -#define DC_DAT CYGARC_REG_DC_DAT - -#define DC_CMD_CE CYGARC_REG_DC_CMD_CE -#define DC_CMD_CD CYGARC_REG_DC_CMD_CD -#define DC_CMD_LL CYGARC_REG_DC_CMD_LL -#define DC_CMD_UL CYGARC_REG_DC_CMD_UL -#define DC_CMD_UA CYGARC_REG_DC_CMD_UA -#define DC_CMD_IA CYGARC_REG_DC_CMD_IA -#define DC_CMD_FL CYGARC_REG_DC_CMD_FL -#define DC_CMD_SW CYGARC_REG_DC_CMD_SW -#define DC_CMD_CW CYGARC_REG_DC_CMD_CW -#define DC_CMD_SS CYGARC_REG_DC_CMD_SS -#define DC_CMD_CS CYGARC_REG_DC_CMD_CS - -#define DC_ADR_SETID_SHIFT CYGARC_REG_DC_ADR_SETID_SHIFT -#define DC_ADR_WAY0 CYGARC_REG_DC_ADR_WAY0 -#define DC_ADR_WAY1 CYGARC_REG_DC_ADR_WAY1 -#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS - -//-------------------------------------------------------------------------- -// MMU control. -#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS -#define M_CASID 793 // current address space id register - -#define MI_CTR 784 // instruction MMU control -#define MI_EPN 787 // instruction MMU effective page num -#define MI_TWC 789 // instruction MMU tablewalk count -#define MI_RPN 790 // instruction MMU real page num -#define MI_DCAM 816 // instruction MMU CAM read -#define MI_DRAM0 817 // instruction MMU RAM read 0 -#define MI_DRAM1 818 // instruction MMU RAM read 1 - -#define MI_EPN_EPNMASK 0xfffff000 // effective page no mask -#define MI_EPN_EV 0x00000200 // entry valid - -#define MI_RPN_RPNMASK 0xfffff000 // real page no mask -#define MI_RPN_PPRWRW 0x000008f0 // page protection (rw/rw, page valid) -#define MI_RPN_LPS 0x00000008 // large page size -#define MI_RPN_SH 0x00000004 // shared page (1 = no ASID cmp) -#define MI_RPN_CI 0x00000002 // cache inhibited -#define MI_RPN_V 0x00000001 // entry valid - -#define MI_TWC_PS8MB 0x0000000c // page size = 8MB -#define MI_TWC_G 0x00000010 // guarded -#define MI_TWC_WT 0x00000002 // writethrough -#define MI_TWC_V 0x00000001 // entry valid - -#define MI_CTR_INDX_SHIFT 8 // the ITLB_INDX starts at bit 23 - -#define MD_CTR 792 // data MMU control -#define MD_EPN 795 // data MMU effective page num -#define MD_TWC 797 // data MMU tablewalk count -#define MD_RPN 798 // data MMU real page num -#define MD_DCAM 824 // data MMU CAM read -#define MD_DRAM0 825 // data MMU RAM read 0 -#define MD_DRAM1 826 // data MMU RAM read 1 - -#define MD_RPN_CHANGED 0x00000100 // page changed -#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS - -//-------------------------------------------------------------------------- -// Internal Memory Map. -#define CYGARC_REG_IMMR 638 // internal memory map base register -#define CYGARC_REG_IMMR_BASEMASK 0xffff0000 // imm base location mask (rw) -#define CYGARC_REG_IMMR_PARTNUM 0x0000ff00 // part number mask (ro) -#define CYGARC_REG_IMMR_MASKNUM 0x000000ff // mask number mask (ro) - -#define CYGARC_REG_IMM_BASE 0xff000000 // the internal memory map base - -// system protection control -#define CYGARC_REG_IMM_SYPCR (CYGARC_REG_IMM_BASE + 0x004) -#define CYGARC_REG_IMM_SYPCR_SWTC_MASK 0xffff0000 -#define CYGARC_REG_IMM_SYPCR_BMT_MASK 0x0000ff00 -#define CYGARC_REG_IMM_SYPCR_BME 0x00000080 -#define CYGARC_REG_IMM_SYPCR_SWF 0x00000008 -#define CYGARC_REG_IMM_SYPCR_SWE 0x00000004 -#define CYGARC_REG_IMM_SYPCR_SWRI 0x00000002 -#define CYGARC_REG_IMM_SYPCR_SWP 0x00000001 - -// interrupt pend register -#define CYGARC_REG_IMM_SIPEND (CYGARC_REG_IMM_BASE + 0x010) -#define CYGARC_REG_IMM_SIPEND_IRQ0 0x80000000 // irq0 is bit 0... - -// interrupt mask -#define CYGARC_REG_IMM_SIMASK (CYGARC_REG_IMM_BASE + 0x014) -#define CYGARC_REG_IMM_SIMASK_IRQ0 0x80000000 // ... irq n is bit n*2 - -// interrupt edge level mask -#define CYGARC_REG_IMM_SIEL (CYGARC_REG_IMM_BASE + 0x018) -#define CYGARC_REG_IMM_SIEL_IRQ0 0x80000000 - -// interrupt vector -#define CYGARC_REG_IMM_SIVEC (CYGARC_REG_IMM_BASE + 0x01c) - -// memory controller -#define CYGARC_REG_IMM_BR0 (CYGARC_REG_IMM_BASE + 0x100) -#define CYGARC_REG_IMM_OR0 (CYGARC_REG_IMM_BASE + 0x104) -#define CYGARC_REG_IMM_BR1 (CYGARC_REG_IMM_BASE + 0x108) -#define CYGARC_REG_IMM_OR1 (CYGARC_REG_IMM_BASE + 0x10c) -#define CYGARC_REG_IMM_BR2 (CYGARC_REG_IMM_BASE + 0x110) -#define CYGARC_REG_IMM_OR2 (CYGARC_REG_IMM_BASE + 0x114) -#define CYGARC_REG_IMM_BR3 (CYGARC_REG_IMM_BASE + 0x118) -#define CYGARC_REG_IMM_OR3 (CYGARC_REG_IMM_BASE + 0x11c) -#define CYGARC_REG_IMM_BR4 (CYGARC_REG_IMM_BASE + 0x120) -#define CYGARC_REG_IMM_OR4 (CYGARC_REG_IMM_BASE + 0x124) -#define CYGARC_REG_IMM_BR5 (CYGARC_REG_IMM_BASE + 0x128) -#define CYGARC_REG_IMM_OR5 (CYGARC_REG_IMM_BASE + 0x12c) -#define CYGARC_REG_IMM_BR6 (CYGARC_REG_IMM_BASE + 0x130) -#define CYGARC_REG_IMM_OR6 (CYGARC_REG_IMM_BASE + 0x134) -#define CYGARC_REG_IMM_BR7 (CYGARC_REG_IMM_BASE + 0x138) -#define CYGARC_REG_IMM_OR7 (CYGARC_REG_IMM_BASE + 0x13c) - -#define CYGARC_REG_IMM_BR_BA_MASK 0xffff8000 // base address -#define CYGARC_REG_IMM_BR_AT_MASK 0x00007000 // address type -#define CYGARC_REG_IMM_BR_PS_8 0x00000400 // port size 8 bits -#define CYGARC_REG_IMM_BR_PS_16 0x00000800 // port size 16 bits -#define CYGARC_REG_IMM_BR_PS_32 0x00000000 // port size 32 bits -#define CYGARC_REG_IMM_BR_PARE 0x00000200 // parity enable -#define CYGARC_REG_IMM_BR_WP 0x00000100 // write protect -#define CYGARC_REG_IMM_BR_MS_GPCM 0x00000000 // machine select G.P.C.M -#define CYGARC_REG_IMM_BR_MS_UPMA 0x00000080 // machine select U.P.M.A -#define CYGARC_REG_IMM_BR_MS_UPMB 0x000000c0 // machine select U.P.M.B -#define CYGARC_REG_IMM_BR_V 0x00000001 // valid bit - -#define CYGARC_REG_IMM_OR_AM 0xffff8000 // address mask -#define CYGARC_REG_IMM_OR_ATM 0x00007000 // address type mask -#define CYGARC_REG_IMM_OR_CSNT 0x00000800 // GPCM:chip select negation time -#define CYGARC_REG_IMM_OR_SAM 0x00000800 // UPMx:start address multiplex -#define CYGARC_REG_IMM_OR_ACS_0 0x00000000 // GPCM:CS output immediately -#define CYGARC_REG_IMM_OR_ACS_4 0x00000400 // GPCM:CS output 1/4 clock later -#define CYGARC_REG_IMM_OR_ACS_2 0x00000600 // GPCM:CS output 1/2 clock later -#define CYGARC_REG_IMM_OR_G5LA 0x00000400 // UPMx:general-purpose line 5 A -#define CYGARC_REG_IMM_OR_G5LS 0x00000200 // UPMx:general-purpose line 5 S -#define CYGARC_REG_IMM_OR_BI 0x00000100 // burst inhibit -#define CYGARC_REG_IMM_OR_SCY_MASK 0x000000f0 // cycle length in clocks -#define CYGARC_REG_IMM_OR_SCY_SHIFT 4 -#define CYGARC_REG_IMM_OR_SETA 0x00000008 // external transfer ack -#define CYGARC_REG_IMM_OR_TRLX 0x00000004 // timing relaxed -#define CYGARC_REG_IMM_OR_EHTR 0x00000002 // extended hold time on read - -// timebase status and control -#define CYGARC_REG_IMM_TBSCR (CYGARC_REG_IMM_BASE + 0x200) -#define CYGARC_REG_IMM_TBSCR_REFA 0x0080 // reference interrupt status A -#define CYGARC_REG_IMM_TBSCR_REFB 0x0040 // reference interrupt status B -#define CYGARC_REG_IMM_TBSCR_REFAE 0x0008 // reference interrupt enable A -#define CYGARC_REG_IMM_TBSCR_REFBE 0x0004 // reference interrupt enable B -#define CYGARC_REG_IMM_TBSCR_TBF 0x0002 // timebase freeze -#define CYGARC_REG_IMM_TBSCR_TBE 0x0001 // timebase enable -#define CYGARC_REG_IMM_TBSCR_IRQ0 0x8000 // highest interrupt level -#define CYGARC_REG_IMM_TBSCR_IRQMASK 0xff00 // irq priority mask - -// timebase reference register 0 -#define CYGARC_REG_IMM_TBREF0 (CYGARC_REG_IMM_BASE + 0x204) -// timebase reference register 1 -#define CYGARC_REG_IMM_TBREF1 (CYGARC_REG_IMM_BASE + 0x208) - -// real time clock -#define CYGARC_REG_IMM_RTCSC (CYGARC_REG_IMM_BASE + 0x220) -#define CYGARC_REG_IMM_RTCSC_SEC 0x0080 // once per second interrupt -#define CYGARC_REG_IMM_RTCSC_ALR 0x0040 // alarm interrupt -#define CYGARC_REG_IMM_RTCSC_38K 0x0010 // source select -#define CYGARC_REG_IMM_RTCSC_SIE 0x0008 // second interrupt enable -#define CYGARC_REG_IMM_RTCSC_ALE 0x0004 // alarm interrupt enable -#define CYGARC_REG_IMM_RTCSC_RTF 0x0002 // real time clock freeze -#define CYGARC_REG_IMM_RTCSC_RTE 0x0001 // real time clock enable -#define CYGARC_REG_IMM_RTCSC_IRQ0 0x8000 // highest interrupt level -#define CYGARC_REG_IMM_RTCSC_IRQMASK 0xff00 // irq priority mask - -// periodic interrupt status & ctrl -#define CYGARC_REG_IMM_PISCR (CYGARC_REG_IMM_BASE + 0x240) -#define CYGARC_REG_IMM_PISCR_PS 0x0080 // periodic interrupt status -#define CYGARC_REG_IMM_PISCR_PIE 0x0004 // periodic interrupt enable -#define CYGARC_REG_IMM_PISCR_PITF 0x0002 // periodic interrupt timer freeze -#define CYGARC_REG_IMM_PISCR_PTE 0x0001 // periodic timer enable -#define CYGARC_REG_IMM_PISCR_IRQ0 0x8000 // highest interrupt level -#define CYGARC_REG_IMM_PISCR_IRQMASK 0xff00 // irq priority mask - -// periodic interrupt timer count -#define CYGARC_REG_IMM_PITC (CYGARC_REG_IMM_BASE + 0x244) -#define CYGARC_REG_IMM_PITC_COUNT_SHIFT 16 // count is stored in bits 0-15 - -// system clock control -#define CYGARC_REG_IMM_SCCR (CYGARC_REG_IMM_BASE + 0x280) -#define CYGARC_REG_IMM_SCCR_TBS 0x02000000 // timebase source -#define CYGARC_REG_IMM_SCCR_RTDIV 0x01000000 // rtc clock divide -#define CYGARC_REG_IMM_SCCR_RTSEL 0x00800000 // rtc clock select - -// CPM interrupt vector register -#define CYGARC_REG_IMM_CIVR (CYGARC_REG_IMM_BASE + 0x930) -#define CYGARC_REG_IMM_CIVR_IACK 0x0001 // set this to update register -#define CYGARC_REG_IMM_CIVR_VECTOR_SHIFT 11 // vector is at bits 0-4 - -// CPM interrupt configuration reg -#define CYGARC_REG_IMM_CICR (CYGARC_REG_IMM_BASE + 0x940) -#define CYGARC_REG_IMM_CICR_IEN 0x00000080 // interrupt enable -#define CYGARC_REG_IMM_CICR_IRQMASK 0x0000e000 // irq priority mask -#define CYGARC_REG_IMM_CICR_IRQ_SHIFT 13 - -// CPM interrupt mask register -#define CYGARC_REG_IMM_CIMR (CYGARC_REG_IMM_BASE + 0x948) -// CPM interrupt in-service register -#define CYGARC_REG_IMM_CISR (CYGARC_REG_IMM_BASE + 0x94C) - - -#define CYGARC_SIU_PRIORITY_LOW 7 // the lowest irq priority -#define CYGARC_SIU_PRIORITY_HIGH 0 // the highest irq priority - -#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS - -#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS - //----------------------------------------------------------------------------- -// Development Support. -#define CYGARC_REG_DER 149 - -#define CYGARC_REG_ICTRL 158 // instruction support control reg -#define CYGARC_REG_ICTRL_SERSHOW 0x00000000 // serialized, show cycles -#define CYGARC_REG_ICTRL_NOSERSHOW 0x00000007 //non-serialized&no show cycles - -#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS -#define DER CYGARC_REG_DER - -#define ICTRL CYGARC_REG_ICTRL -#define ICTRL_SERSHOW CYGARC_REG_ICTRL_SERSHOW -#define ICTRL_NOSERSHOW CYGARC_REG_ICTRL_NOSERSHOW -#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS - -#endif // ifdef CYGPKG_HAL_POWERPC_MPC8xx - #endif // ifdef CYGONCE_HAL_PPC_REGS_H +// End of ppc_regs.h
--- a/packages/hal/powerpc/arch/current/src/hal_intr.c +++ b/packages/hal/powerpc/arch/current/src/hal_intr.c @@ -44,207 +44,15 @@ #include <pkgconf/hal.h> -#include <cyg/hal/ppc_regs.h> - -// REMINDER: Full CDL required to enforce this -#ifndef CYGPKG_KERNEL -#undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT -#endif - -// These are the Cyg_Interrupt::HANDLED/CALL_DSR values. -#define Cyg_InterruptHANDLED 1 -#define Cyg_InterruptCALL_DSR 2 - -//#include <cyg/hal/hal_intr.inl> // hal_call_isr -//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -// FIXME: This function should be in hal/common/.../include/hal_intr.inl -// or similar. -#include <cyg/hal/hal_intr.h> // hal_interrupt_x tables - -typedef cyg_uint32 cyg_ISR(cyg_uint32 vector, CYG_ADDRWORD data); - -extern void cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj ); - -static inline cyg_uint32 -hal_call_isr (cyg_uint32 vector) -{ - cyg_ISR *isr; - CYG_ADDRWORD data; - cyg_uint32 isr_ret; - - isr = (cyg_ISR*) hal_interrupt_handlers[vector]; - data = hal_interrupt_data[vector]; - - isr_ret = (*isr) (vector, data); - -#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT - if (isr_ret & Cyg_InterruptCALL_DSR) { - cyg_interrupt_post_dsr (hal_interrupt_objects[vector]); - } -#endif - - return isr_ret & Cyg_InterruptHANDLED; -} - -//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -#ifdef CYGPKG_HAL_POWERPC_MPC860 - -// Since the interrupt sources do not have fixed vectors on the 860 -// SIU, some arbitration is required. - -// More than one interrupt source can be programmed to use the same -// vector, so all sources on the same vector have to be queried to -// find the one raising the interrupt. This functionality has not been -// implemented, but the arbiter functions for each of the SIU -// interrupt sources can be called in sequence without change. - - - -// Timebase interrupt can be caused by match on either reference A -// or B. -// Note: If only one interrupt source is assigned per vector, and only -// reference interrupt A or B is used, this ISR is not -// necessary. Attach the timerbase reference A or B ISR directly to -// the LVLx vector instead. -externC cyg_uint32 -hal_arbitration_isr_tb (CYG_ADDRWORD vector, CYG_ADDRWORD data) -{ - cyg_uint32 isr_ret; - cyg_uint16 tbscr; - - HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - if (tbscr & CYGARC_REG_IMM_TBSCR_REFA) { - isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_TB_A); - - CYG_ASSERT (isr_ret & Cyg_InterruptHANDLED, - "Interrupt not handled"); - -#ifndef CYGSEM_HAL_COMMON_INTERRUPTS_CHECK_ALL_SOURCES - return isr_ret; -#endif - } - - if (tbscr & CYGARC_REG_IMM_TBSCR_REFB) { - isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_TB_B); - - CYG_ASSERT (isr_ret & Cyg_InterruptHANDLED, - "Interrupt not handled"); - -#ifndef CYGSEM_HAL_COMMON_INTERRUPTS_CHECK_ALL_SOURCES - return isr_ret; -#endif - } - - return 0; -} - -// Periodic interrupt. -// Note: If only one interrupt source is assigned per vector, this ISR -// is not necessary. Attach the periodic interrupt ISR directly to the -// LVLx vector instead. -externC cyg_uint32 -hal_arbitration_isr_pit (CYG_ADDRWORD vector, CYG_ADDRWORD data) -{ - cyg_uint32 isr_ret; - cyg_uint16 piscr; - - HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); - if (piscr & CYGARC_REG_IMM_PISCR_PS) { - isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_PIT); - - CYG_ASSERT (isr_ret & Cyg_InterruptHANDLED, - "Interrupt not handled"); - -#ifndef CYGSEM_HAL_COMMON_INTERRUPTS_CHECK_ALL_SOURCES - return isr_ret; -#endif - } - - return 0; -} - -// Real time clock interrupts can be caused by the alarm or -// once-per-second. -// Note: If only one interrupt source is assigned per vector, and only -// the alarm or once-per-second interrupt is used, this ISR is not -// necessary. Attach the alarm or once-per-second ISR directly to the -// LVLx vector instead. -externC cyg_uint32 -hal_arbitration_isr_rtc (CYG_ADDRWORD vector, CYG_ADDRWORD data) -{ - cyg_uint32 isr_ret; - cyg_uint16 rtcsc; - - HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); - if (rtcsc & CYGARC_REG_IMM_RTCSC_SEC) { - isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC); - - CYG_ASSERT (isr_ret & Cyg_InterruptHANDLED, - "Interrupt not handled"); - -#ifndef CYGSEM_HAL_COMMON_INTERRUPTS_CHECK_ALL_SOURCES - return isr_ret; -#endif - } - - if (rtcsc & CYGARC_REG_IMM_RTCSC_ALR) { - isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR); - - CYG_ASSERT (isr_ret & Cyg_InterruptHANDLED, - "Interrupt not handled"); - -#ifndef CYGSEM_HAL_COMMON_INTERRUPTS_CHECK_ALL_SOURCES - return isr_ret; -#endif - } - - return 0; -} - -// Communication Processor Module interrupt can be caused by any of -// the CPM sources. -externC cyg_uint32 -hal_arbitration_isr_cpm (CYG_ADDRWORD vector, CYG_ADDRWORD data) -{ - cyg_uint32 isr_ret; - cyg_uint16 civr; - - HAL_WRITE_UINT16 (CYGARC_REG_IMM_CIVR, CYGARC_REG_IMM_CIVR_IACK); - HAL_READ_UINT16 (CYGARC_REG_IMM_CIVR, civr); - civr >>= CYGARC_REG_IMM_CIVR_VECTOR_SHIFT; - if (civr) { - isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_CPM_LAST - civr); - - CYG_ASSERT (isr_ret & Cyg_InterruptHANDLED, - "Interrupt not handled"); - -#ifndef CYGSEM_HAL_COMMON_INTERRUPTS_CHECK_ALL_SOURCES - return isr_ret; -#endif - } - - return 0; -} +#include <cyg/hal/hal_intr.h> externC void hal_IRQ_init(void) { -#define ID_CPM 0xDEAD - HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_LVL7, - &hal_arbitration_isr_cpm, ID_CPM, 0); - HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_LVL7); - HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_CPM, 7); - HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_CPM); + // No architecture general initialization, but the variant may have + // provided some. + hal_variant_IRQ_init(); } -#else // ifdef CYGPKG_HAL_POWERPC_MPC860 - -externC void -hal_IRQ_init(void) -{ - // Nothing special -} - -#endif // ifdef CYGPKG_HAL_POWERPC_MPC860 // ------------------------------------------------------------------------- // EOF hal_intr.c
--- a/packages/hal/powerpc/arch/current/src/hal_misc.c +++ b/packages/hal/powerpc/arch/current/src/hal_misc.c @@ -481,8 +481,6 @@ hal_enable_caches(void) // Enable caches. #ifdef CYGPRI_ENABLE_CACHES - // Cogent board doesn't support burst access to the ROM and on the - // MPC8xx caches require burst. HAL_ICACHE_ENABLE(); HAL_DCACHE_ENABLE(); #endif @@ -502,7 +500,7 @@ hal_enable_caches(void) //--------------------------------------------------------------------------- //A jump via a null pointer causes the CPU to end up here. externC void -hal_null_call() +hal_null_call(void) { CYG_FAIL("Call via NULL-pointer!");
--- a/packages/hal/powerpc/arch/current/src/powerpc.ld +++ b/packages/hal/powerpc/arch/current/src/powerpc.ld @@ -40,7 +40,7 @@ // //========================================================================*/ STARTUP(vectors.o) -ENTRY(reset_vector) +ENTRY(__exception_reset) #ifdef EXTRAS INPUT(extras.o) #endif @@ -138,3 +138,8 @@ GROUP(libtarget.a libgcc.a) #include <pkgconf/system.h> #include CYGHWR_MEMORY_LAYOUT_LDI + +// Define VSR table to reside at fixed address. This address will +// probably have to be variant specific for optimal memory usage, but +// for now just put it above the PPC family reserved exception space. +hal_vsr_table = 0x3000;
--- a/packages/hal/powerpc/arch/current/src/vectors.S +++ b/packages/hal/powerpc/arch/current/src/vectors.S @@ -44,6 +44,47 @@ ## ##========================================================================== +#=========================================================================== +# +# The PowerPC exception handling has changed as of version 1.3.1. +# The primary motivation for rewriting the code was to bring it more +# in line with the other HALs, in particular to allow a RAM application +# to cleanly take over only a subset of vectors from a running ROM +# monitor. +# +# GDB stubs (and CygMon, should it be ported to PPC) copies +# exception vector entry handler code to address 0. These vector entry +# handlers (defined by the exception_vector macro below) compute +# a vector index into the hal_vsr_table, fetch the pointer, and +# jump to the HAL vector service routine (VSR). +# +# The hal_vsr_table is located immediately after the vector +# handlers (at address 0x3000), allowing RAM applications to +# change VSRs as necessary, while still keeping desired ROM +# monitor functionality available for debugging. +# +# ROM applications can still be configured to leave the vector entry +# handlers at 0xff000000, but there is at the moment no +# provision for reclaiming the reserved vector space in RAM to +# application usage. +# +# RAM applications can also be configured to provide exception +# handlers which are copied to address 0 on startup, thus taking +# full control of the target. +# +# +# Default configuration is for RAM applications to rely on an +# existing ROM monitor to provide debugging functionality, and +# for ROM applications to copy vectors to address 0. +# +# +# Unfortunately the new exception scheme is not compatible with the +# old scheme. Stubs and applications must be compiled using the same +# scheme (i.e., old binaries will not run with new stubs, and new +# binaries will not run with old stubs). +# +#=========================================================================== + #include <pkgconf/hal.h> #ifdef CYGPKG_KERNEL @@ -53,18 +94,29 @@ #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS #include "cyg/hal/ppc_regs.h" #include "cyg/hal/ppc.inc" - + #=========================================================================== .file "vectors.S" + .extern hal_interrupt_data .extern hal_interrupt_handlers - .extern hal_interrupt_data .extern hal_interrupt_objects + .extern hal_vsr_table + .extern cyg_hal_invoke_constructors .extern cyg_instrument + .extern cyg_start + .extern hal_IRQ_init + .extern hal_MMU_init + .extern hal_enable_caches + .extern hal_hardware_init + .extern initialize_stub - .extern hal_hardware_init + .extern __bss_start + .extern __bss_end + .extern __sbss_start + .extern __sbss_end #=========================================================================== # MSR initialization value @@ -77,16 +129,16 @@ # RI = recoverable interrupt #define CYG_MSR_COMMON (MSR_FP | MSR_ME | MSR_IR | MSR_DR | MSR_RI) -#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) +#if defined(CYG_HAL_STARTUP_ROM) # ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS # define CYG_MSR CYG_MSR_COMMON # else # define CYG_MSR (CYG_MSR_COMMON | MSR_IP) # endif +#elif defined(CYG_HAL_STARTUP_RAM) +# define CYG_MSR CYG_MSR_COMMON #endif -#ifdef CYG_HAL_STARTUP_RAM -#define CYG_MSR CYG_MSR_COMMON -#endif + #ifdef CYGPKG_HAL_POWERPC_SIM # When building for SIM, don~t enable MMU -- it~s not needed since caches # are disabled, and there is a runtime simulation overhead. @@ -96,52 +148,46 @@ #define CYG_MSR_NO_INTS (CYG_MSR & ~MSR_ME) +# Include variant macros after MSR definition. +#include "cyg/hal/variant.inc" + + #=========================================================================== # If the following option is enabled, we only save registers up to R12. # The PowerPC ABI defines registers 13..31 as callee saved and thus we do # not need to save them when calling C functions. #ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT - -#define MAX_SAVE_REG 12 - +# define MAX_SAVE_REG 12 #else - -#define MAX_SAVE_REG 31 - +# define MAX_SAVE_REG 31 #endif #=========================================================================== # Start by defining the exceptions vectors that must be placed at -# locations 0xFFF00000 and 0x00000000. The following code will normally +# locations 0xFFF00000 or 0x00000000. The following code will normally # be located at 0xFFF00000 in the ROM. It may optionally be copied out # to 0x00000000 if we want to use the RAM vectors. For this reason this code -# MUST BE POSITION INDEPENDENT. In RAM loaded configurations, this code may -# be placed at 0x00000000 during loading. +# MUST BE POSITION INDEPENDENT. .section ".vectors","ax" #--------------------------------------------------------------------------- -# Unused first vector. Jump to special handler, trapping null-pointer calls. +# Macros for generating an exception vector service routine + +# Reset vector macro -rom_vectors: - .extern hal_null_call - b hal_null_call - -#--------------------------------------------------------------------------- -# Reset vector. - + .macro reset_vector name .p2align 8 - .globl reset_vector - -reset_vector: + .globl __exception_\name +__exception_\name: lwi r3,_start mtlr r3 blr + .endm -#--------------------------------------------------------------------------- -# Macro for generating an exception vector service routine - +# Generic vector macro + .macro exception_vector name .p2align 8 .globl __exception_\name @@ -163,38 +209,17 @@ reset_vector: #--------------------------------------------------------------------------- # Define the exception vectors. +rom_vectors: # These are the architecture defined vectors that # are always present. - + exception_vector reserved_00000 + reset_vector reset exception_vector machine_check exception_vector data_storage exception_vector instruction_storage exception_vector external exception_vector alignment -#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) \ - || defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) exception_vector program -#else - # Provide a crude hook to the GDB exception handler in ROM. - # This allows the testing infrastructure to rely on breakpoints - # to terminate tests, even when the tests are compiled without - # the GDB stub. - # It is _not_ a generic solution to the problem; in particular it - # is not possible to continue after a breakpoint is hit. - # - # Note that for platforms where StubROM vectors are copied into RAM - # at 0x00000000, simply skipping the copy of vector 0x700 is a - # better solution. See CYGPRI_STUBROM_HAS_RAM_VECTORS below. - - .p2align 8 - .globl __exception_program -__exception_program: - bl _init_CPU # disable caches. - lwi r3,0xfff00700 # address of trap handler - mtlr r3 # in ROM. - blr # jump to it. - -#endif exception_vector floatingpoint_unavailable exception_vector decrementer exception_vector reserved_00a00 @@ -204,31 +229,10 @@ reset_vector: exception_vector floatingpoint_assist exception_vector reserved_00f00 - # There are some additional vectors defined - # on various implementations. - -#ifdef CYGPKG_HAL_POWERPC_MPC8xx - # MPC8xx vectors + # Variants may define extra vectors. + hal_extra_vectors - exception_vector software_emu - exception_vector instruction_tlb_miss - exception_vector data_tlb_miss - exception_vector instruction_tlb_error - exception_vector data_tlb_error - exception_vector reserved_01500 - exception_vector reserved_01600 - exception_vector reserved_01700 - exception_vector reserved_01800 - exception_vector reserved_01900 - exception_vector reserved_01A00 - exception_vector reserved_01B00 - exception_vector data_breakpoint - exception_vector instruction_breakpoint - exception_vector peripheral_breakpoint - exception_vector NMI_port - -#endif -rom_vectors_end: +rom_vectors_end: #=========================================================================== # Real startup code. We jump here from the various reset vectors to set up @@ -236,22 +240,10 @@ rom_vectors_end: .text .globl _start - _start: - # Initialize CPU - bl _init_CPU - -#ifdef CYGPKG_HAL_POWERPC_MPC8xx - # Disable special MPC8xx "development support" which - # suppresses trace exceptions. The CPU seems to hang, not - # executing from offset 0x1e00(?) as expected. - - lwi r3,0x00000007 - mtspr ICTRL,r3 - - li r3,0 - mtspr DER, r3 -#endif + # Initialize CPU to a post-reset state, ensuring the ground doesn''t + # shift under us while we try to set things up. + hal_cpu_init # Set up global offset table lwi r2,_GLOBAL_OFFSET_TABLE_ @@ -271,7 +263,11 @@ rom_vectors_end: lwi sp,__interrupt_stack mtspr SPRG0,sp # save in sprg0 for later use -#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) + # Set up exception handlers and VSR table, taking care not to + # step on any ROM monitor''s toes. + hal_mon_init + +#if defined(CYG_HAL_STARTUP_ROM) # Copy data from ROM to ram lwi r3,__rom_data_start # r3 = rom start @@ -290,56 +286,8 @@ 1: blt 1b # loop if not yet done 2: #endif - - -#ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS // only for StubRom-supported startup - -#ifdef CYGPKG_HAL_POWERPC_MBX -# define CYGPRI_STUBROM_HAS_RAM_VECTORS -#endif - -#ifdef CYGPRI_STUBROM_HAS_RAM_VECTORS -# ifdef CYG_HAL_STARTUP_RAM -# ifndef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS -# define CYGPRI_SKIP_BREAKPOINT_VECTOR -# endif // no stubs -# endif // RAM startup -#endif // Stubrom vectors are in RAM - - # Copy RAM exception vectors from ROM (or load place) to RAM - lwi r3,rom_vectors # r3 = rom start - lwi r4,0 # r4 = ram start -#ifdef CYGPRI_SKIP_BREAKPOINT_VECTOR - lwi r5,__exception_program # r5 = end of first leg of copy -#else - lwi r5,rom_vectors_end # r5 = rom end -#endif - - cmplw r3,r5 # skip if no vectors - beq 2f - -1: - lwz r0,0(r3) # get word from ROM - stw r0,0(r4) # store in RAM - addi r3,r3,4 # increment by 1 word - addi r4,r4,4 # increment by 1 word - cmplw r3,r5 # compare - blt 1b # loop if not yet done -2: -#ifdef CYGPRI_SKIP_BREAKPOINT_VECTOR - cmplwi r4,__exception_program@L - bne 3f # is it the breakpoint vector? - addi r4,r4,0x100 # if so, leave it well alone - addi r3,r3,0x100 - lwi r5,rom_vectors_end # r5 = rom end - b 1b # and do the rest of the copy -3: -#endif // Skip copying the breakpoint vector -#endif # clear BSS - .extern __bss_start - .extern __bss_end lwi r3,__bss_start # r3 = start lwi r4,__bss_end # r4 = end li r0,0 # r0 = 0 @@ -353,8 +301,6 @@ 1: stw r0,0(r3) # store 2: # clear SBSS - .extern __sbss_start - .extern __sbss_end lwi r3,__sbss_start # r3 = start lwi r4,__sbss_end # r4 = end cmplw r3,r4 # skip if no sbss @@ -377,7 +323,6 @@ 2: stwu sp,-ppc_stack_frame_size(sp) # create new stack frame # Initialize MMU. - .extern hal_MMU_init bl hal_MMU_init # Enable MMU so we can safely enable caches. @@ -387,23 +332,18 @@ 2: sync # Enable caches - .extern hal_enable_caches bl hal_enable_caches # call c++ constructors - .extern cyg_hal_invoke_constructors bl cyg_hal_invoke_constructors # set up platform specific interrupt environment - .extern hal_IRQ_init bl hal_IRQ_init #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS - .extern initialize_stub bl initialize_stub #endif - .extern cyg_start bl cyg_start # call cyg_start 9: b 9b # if we return, loop @@ -417,8 +357,8 @@ 9: .text - .extern __default_exception_vsr -__default_exception_vsr: + .globl cyg_hal_default_exception_vsr +cyg_hal_default_exception_vsr: # We come here with all register containing their # pre-exception values except: @@ -520,26 +460,7 @@ 9: ## Note: CYG_ISR_TABLE_SIZE must match CYG_ISR_COUNT defined in hal_intr.h. -#ifdef CYGPKG_HAL_POWERPC_MPC8xx - -## First level decoding of MPC8xx SIU interrupt controller. - -#define CYG_ISR_TABLE_SIZE 59 - - # decode the interrupt - .macro decode_interrupt dreg,state - lwz \dreg,ppcreg_vector(\state) # retrieve vector number, - rlwinm. \dreg,\dreg,22,31,31 # isolate bit 21 - beq 0f # done if decrementer (vec 0) - lwi \dreg,CYGARC_REG_IMM_SIVEC # if external, get SIU - lbz \dreg,0(\dreg) # vector. - srwi \dreg,\dreg,2 - addi \dreg,\dreg,1 # Skip decrementer vector -0: stw \dreg,ppcreg_vector(\state) # update vector in state frame. - slwi \dreg,\dreg,2 # convert to byte offset. - .endm - -#else +#ifndef CYGPKG_HAL_POWERPC_INTC_DEFINED ## This is the simple version. No interrupt controller, ppcreg_vector ## is updated with the decoded interrupt vector. Isr tables/chaining @@ -549,20 +470,20 @@ 0: stw \dreg,ppcreg_vector(\sta #define CYG_ISR_TABLE_SIZE 2 # decode the interrupt - .macro decode_interrupt dreg,state + .macro hal_intc_decode dreg,state lwz \dreg,ppcreg_vector(\state) # retrieve vector number, rlwinm \dreg,\dreg,22,31,31 # isolate bit 21 and update stw \dreg,ppcreg_vector(\state) # vector in state frame. slwi \dreg,\dreg,2 # convert to word offset. .endm -#endif +#endif // CYGPKG_HAL_POWERPC_MPC8xx #--------------------------------------------------------------------------- # Common interrupt handling code. - .extern __default_interrupt_vsr -__default_interrupt_vsr: + .globl cyg_hal_default_interrupt_vsr +cyg_hal_default_interrupt_vsr: # We come here with all register containing their # pre-exception values except: @@ -675,7 +596,7 @@ 2: stwu r14,-4(sp) #endif - decode_interrupt r15,r14 # get table index + hal_intc_decode r15,r14 # get table index #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT .extern cyg_hal_gdb_isr @@ -892,112 +813,6 @@ FUNC_START(hal_interrupt_stack_call_pend #endif #--------------------------------------------------------------------------- -# Code for putting the CPU in a post-reset state; disabling MMU and caches. -_init_CPU: -#ifdef CYGPKG_HAL_POWERPC_MPC8xx - lwi r3,CYGARC_REG_DC_CMD_CD - sync - mtspr CYGARC_REG_DC_CST,r3 - lwi r3,CYGARC_REG_IC_CMD_CD - isync - mtspr CYGARC_REG_IC_CST,r3 - isync -#endif - - # Set up MSR (disable MMU for now) - lwi r3,(CYG_MSR & ~(MSR_IR | MSR_DR)) - sync - mtmsr r3 - sync - blr - -#--------------------------------------------------------------------------- -# This table contains a VSR pointer for each defined exception. -# All of these except 5 and 9 point to the __default_exception_vsr -# above, 5 and 9 point to the __default_interrupt_vsr. Entries in -# this table may be changed using Cyg_Interrupt::set_vsr(). - - .data - - .globl hal_vsr_table -hal_vsr_table: - # Architecture defined vectors - .long __default_exception_vsr # reserved - .long __default_exception_vsr # system reset - .long __default_exception_vsr # machine check - .long __default_exception_vsr # data storage - .long __default_exception_vsr # instruction storage - - .long __default_interrupt_vsr # external interrupt - - .long __default_exception_vsr # alignment - .long __default_exception_vsr # program - .long __default_exception_vsr # floating point unavailable - - .long __default_interrupt_vsr # decrementer - - .long __default_exception_vsr # reserved 0x0a00 - .long __default_exception_vsr # reserved 0x0b00 - .long __default_exception_vsr # system call - .long __default_exception_vsr # trace - .long __default_exception_vsr # floating point assist - .long __default_exception_vsr # reserved 0x0f00 - -#ifdef CYGPKG_HAL_POWERPC_MPC8xx - - # Implementation defined vectors - .long __default_exception_vsr # software emulation - .long __default_exception_vsr # instruction TLB miss - .long __default_exception_vsr # data TLB miss - .long __default_exception_vsr # instruction TLB error - .long __default_exception_vsr # data TLB error - .long __default_exception_vsr # reserved 0x1500 - .long __default_exception_vsr # reserved 0x1600 - .long __default_exception_vsr # reserved 0x1700 - .long __default_exception_vsr # reserved 0x1800 - .long __default_exception_vsr # reserved 0x1900 - .long __default_exception_vsr # reserved 0x1a00 - .long __default_exception_vsr # reserved 0x1b00 - .long __default_exception_vsr # data breakpoint - .long __default_exception_vsr # instruction breakpoint - .long __default_exception_vsr # peripheral breakpoint - .long __default_exception_vsr # non maskable development port -#endif - -#--------------------------------------------------------------------------- -# Interrupt vector tables. -# These tables contain the isr, data and object pointers used to deliver -# interrupts to user code. - -#if (CYG_ISR_TABLE_SIZE > 2) - .data -#else - .section ".sdata","aw" -#endif - - .extern hal_default_decrementer_isr - .extern hal_default_isr - - .globl hal_interrupt_handlers -hal_interrupt_handlers: - .long hal_default_decrementer_isr - .rept CYG_ISR_TABLE_SIZE-1 - .long hal_default_isr - .endr - - .globl hal_interrupt_data -hal_interrupt_data: - .rept CYG_ISR_TABLE_SIZE - .long 0 - .endr - - .globl hal_interrupt_objects -hal_interrupt_objects: - .rept CYG_ISR_TABLE_SIZE - .long 0 - .endr - -#--------------------------------------------------------------------------- ## Temporary interrupt stack .section ".bss"
--- a/packages/hal/powerpc/arch/current/tests/PKGconf.mak +++ b/packages/hal/powerpc/arch/current/tests/PKGconf.mak @@ -36,7 +36,5 @@ include ../../../../../pkgconf/system.ma TESTS := -TESTS += intr0 - include $(COMPONENT_REPOSITORY)/pkgconf/makrules.tst
deleted file mode 100644 --- a/packages/hal/powerpc/arch/current/tests/intr0.c +++ /dev/null @@ -1,298 +0,0 @@ -//================================================================= -// -// intr0.c -// -// Interrupt test 0 -// -//================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): jskov -// Contributors: jskov -// Date: 1998-12-01 -// Description: Simple test of MPC860 interrupt handling when the -// kernel has not been configured. Uses timer interrupts. -// Options: -//####DESCRIPTIONEND#### - -//#define DEBUG_PRINTFS -#ifdef DEBUG_PRINTFS -extern diag_printf( char *format, ... ); -#endif - -#include <pkgconf/hal.h> - -#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS -#include <cyg/hal/ppc_regs.h> - -#include <cyg/hal/hal_intr.h> - -#include <cyg/infra/testcase.h> - -#if defined(CYGPKG_HAL_POWERPC_MPC860) - -#undef CHECK(b) -#define CHECK(b) CYG_TEST_CHECK(b,#b) - -// Can't rely on Cyg_Interrupt class being defined. -#define Cyg_InterruptHANDLED 1 - -// This is the period between interrupts, measured in decrementer ticks. -// Period must be longer than the time required for setting up all the -// interrupt handlers. -#define PIT_PERIOD 5000 - -#ifdef CYGPKG_HAL_POWERPC_MBX -#define TB_PERIOD (PIT_PERIOD*384) // PTA period is 15.36 uS -#else -#define TB_PERIOD (PIT_PERIOD*32) // assuming 512/16 divisors -#endif - -#define ID_RTC_SEC 12345 -#define ID_RTC_ALR 23451 -#define ID_PIT 34512 -#define ID_TBA 45123 -#define ID_TBB 51234 - -volatile cyg_uint32 count = 0; - -// Time/PERIOD 0 1 2 3 4 5 6 7 8 9 10 -// Interrupt PIT TBA PIT PIT TBB PIT PIT -// pit_count 0 0 0 1 1 2 2 3 3 4 4 -// count 0 0 1 3 4 4 5 40 41 42 - -static cyg_uint32 count_verify_table[] = {1, 4, 5, 41, 42}; -static int pit_count = 0; - -// These are useful for debugging: -static cyg_uint32 count_actual_table[] = { -1, -1, -1, -1, -1}; -static cyg_uint32 tbr_actual_table[] = { -1, -1, -1, -1, -1}; - -// Periodic timer ISR. Should be executing 5 times. -static cyg_uint32 isr_pit(CYG_ADDRWORD vector, CYG_ADDRWORD data) -{ - cyg_uint32 verify_value; - - CYG_UNUSED_PARAM(CYG_ADDRWORD, data); - - CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_PIT == vector, "Wrong vector!"); - CYG_ASSERT (ID_PIT == data, "Wrong data!"); - - HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_PIT); - - count++; - - count_actual_table[pit_count] = count; - { - cyg_uint32 tbl; - CYGARC_MFTB (TBL_R, tbl); - tbr_actual_table[pit_count] = tbl; - } - - verify_value = count_verify_table[pit_count++]; - -#ifdef DEBUG_PRINTFS - diag_printf( "ISR_PIT executed %d of 5\n", pit_count ); -#endif - - CYG_ASSERT (count == verify_value, "Count wrong!"); - - // End of test when count is 42. Mask interrupts and print PASS text. - if (42 <= count || 5 == pit_count) { - HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_PIT); - HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_TB_A); - HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_TB_B); - -#ifdef DEBUG_PRINTFS - diag_printf( "INFO: Actual counts: %d %d %d %d %d\n", - count_actual_table[0], - count_actual_table[1], - count_actual_table[2], - count_actual_table[3], - count_actual_table[4] ); - diag_printf( "INFO: Actuals tbrs: %d %d %d %d %d\n", - tbr_actual_table[0], - tbr_actual_table[1], - tbr_actual_table[2], - tbr_actual_table[3], - tbr_actual_table[4] ); -#endif - if (42 == count && 5 == pit_count) - CYG_TEST_PASS_FINISH("Intr 0 OK"); - else - CYG_TEST_FAIL_FINISH("Intr 0 Failed."); - } - - return Cyg_InterruptHANDLED; -} - -// TimeBase A ISR. Should be executing once. -static cyg_uint32 isr_tba(CYG_ADDRWORD vector, CYG_ADDRWORD data) -{ - CYG_UNUSED_PARAM(CYG_ADDRWORD, data); - - CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_TB_A == vector, "Wrong vector!"); - CYG_ASSERT (ID_TBA == data, "Wrong data!"); - - HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_TB_A); - - count = count * 3; - -#ifdef DEBUG_PRINTFS - diag_printf( "ISR_TBA executed\n" ); -#endif - - return Cyg_InterruptHANDLED; -} - -// TimeBase B ISR. Should be executing once. -static cyg_uint32 isr_tbb(CYG_ADDRWORD vector, CYG_ADDRWORD data) -{ - CYG_UNUSED_PARAM(CYG_ADDRWORD, data); - - CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_TB_B == vector, "Wrong vector!"); - CYG_ASSERT (ID_TBB == data, "Wrong data!"); - - HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_TB_B); - - count = count * 8; - -#ifdef DEBUG_PRINTFS - diag_printf( "ISR_TBB executed\n" ); -#endif - - return Cyg_InterruptHANDLED; -} - -void intr0_main( void ) -{ - CYG_TEST_INIT(); - -#if 0 - // The A.3 revision of the CPU I'm using at the moment generates a - // machine check exception when writing to IMM_RTCSC. Smells a - // bit like the "SIU4. Spurious External Bus Transaction Following - // PLPRCR Write." CPU errata. Have to find out for sure. Run real - // time clock interrupts on level 0 - { - // Still to do. - } -#endif - - // Run periodic timer interrupt on level 1 - { - cyg_uint16 piscr; - - // Attach pit arbiter. - HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_LVL1, - &hal_arbitration_isr_pit, ID_PIT, 0); - HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_LVL1); - - // Attach pit isr. - HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_PIT, &isr_pit, - ID_PIT, 0); - HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_PIT, 1); - HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_PIT); - - - // Set period. - HAL_WRITE_UINT32 (CYGARC_REG_IMM_PITC, - (2*PIT_PERIOD) << CYGARC_REG_IMM_PITC_COUNT_SHIFT); - -#ifdef DEBUG_PRINTFS - diag_printf( "PIT set to %d\n", 2*PIT_PERIOD ); -#endif - // Enable. - HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); - piscr |= CYGARC_REG_IMM_PISCR_PTE; - HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr); - } - - // Run timebase interrupts on level 2 - { - cyg_uint16 tbscr; - cyg_uint32 tbl; - - // Attach tb arbiter. - HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_LVL2, - &hal_arbitration_isr_tb, ID_TBA, 0); - HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_LVL2); - - // Attach tb isrs. - HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_TB_A, &isr_tba, - ID_TBA, 0); - HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_TB_B, &isr_tbb, - ID_TBB, 0); - HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_TB_A, 2); - HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_TB_A); - HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_TB_B); - - // Set reference A & B registers. - CYGARC_MFTB (TBL_R, tbl); - tbl += TB_PERIOD*3; - HAL_WRITE_UINT32 (CYGARC_REG_IMM_TBREF0, tbl); - tbl += TB_PERIOD*4; - HAL_WRITE_UINT32 (CYGARC_REG_IMM_TBREF1, tbl); - -#ifdef DEBUG_PRINTFS - diag_printf( "TB initial %d, !1 %d !2 %d\n", - tbl - 7*TB_PERIOD, - tbl - 4*TB_PERIOD, - tbl - 0*TB_PERIOD ); -#endif - // Enable. - HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - tbscr |= (CYGARC_REG_IMM_TBSCR_REFA | CYGARC_REG_IMM_TBSCR_REFB | - CYGARC_REG_IMM_TBSCR_TBE); - HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - tbscr |= CYGARC_REG_IMM_TBSCR_REFAE | CYGARC_REG_IMM_TBSCR_REFBE; - HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - } - - HAL_ENABLE_INTERRUPTS(); - - for (;;); -} - -externC void -cyg_start( void ) -{ - intr0_main(); -} - -#else // ifdef CYGPKG_HAL_POWERPC_MPC860 - -externC void -cyg_start( void ) -{ - CYG_TEST_INIT(); - CYG_TEST_PASS_FINISH("N/A: Not a MPC860"); -} - -#endif // ifdef CYGPKG_HAL_POWERPC_MPC860 - -// EOF intr0.c
--- a/packages/hal/powerpc/cogent/current/ChangeLog +++ b/packages/hal/powerpc/cogent/current/ChangeLog @@ -1,3 +1,25 @@ +2000-02-10 Jesper Skov <jskov@redhat.com> + + * include/plf_stub.h: + HAL_STUB_PLATFORM_STUBS_INIT->HAL_STUB_PLATFORM_INIT + + * misc/STUBS_config: + Removed stubs as a legal startup type. + +2000-02-07 Jesper Skov <jskov@redhat.com> + + * include/pkgconf/mlt_powerpc_cogent_ram.mlt: + * include/pkgconf/mlt_powerpc_cogent_rom.mlt: + Fixed some typos. + + * src/hal_diag.c: Depend on CYGSEM_HAL_ROM_MONITOR instead of + STARTUP_STUBS. + + * include/pkgconf/mlt*.*: Updated to new stubs scheme. + * include/pkgconf/hal_powerpc_cogent.h: Removed stubs startup + type. Use MPC8xx variant code. + + 2000-02-03 Jesper Skov <jskov@redhat.com> * src/cma_ser.inl: * src/cogent.S:
--- a/packages/hal/powerpc/cogent/current/include/pkgconf/hal_powerpc_cogent.h +++ b/packages/hal/powerpc/cogent/current/include/pkgconf/hal_powerpc_cogent.h @@ -51,6 +51,7 @@ display "Cogent PowerPC evaluation board" type radio parent CYGPKG_HAL_POWERPC + requires CYGPKG_HAL_POWERPC_MPC8xx platform cogent description " The cogent HAL package provides the support needed to run @@ -62,19 +63,17 @@ parent CYGPKG_HAL_POWERPC_COGENT #type count type enum - legal_values ram rom stubs + legal_values ram rom startup description " When targetting the cogent board it is possible to build - the system for either RAM bootstrap, ROM bootstrap, or STUB - bootstrap. RAM bootstrap generally requires that the board + the system for either RAM bootstrap or ROM bootstrap. + RAM bootstrap generally requires that the board is equipped with ROMs containing a suitable ROM monitor or equivalent software that allows GDB to download the eCos application on to the board. The ROM bootstrap typically requires that the eCos application be blown into EPROMs or - equivalent technology. STUB bootstrap is for configurations - of eCos used only as GDB stub ROMs; the use of memory is - limited to the top 1MB." + equivalent technology." } #### There will be a flood of PRs if the config tool is allowed to fiddle
--- a/packages/hal/powerpc/cogent/current/include/pkgconf/mlt_powerpc_cogent_ram.ldi +++ b/packages/hal/powerpc/cogent/current/include/pkgconf/mlt_powerpc_cogent_ram.ldi @@ -36,7 +36,10 @@ MEMORY SECTIONS { SECTIONS_BEGIN - SECTION_vectors (ram, 0x0, LMA_EQ_VMA) + __reserved_vectors = 0; . = __reserved_vectors + 0x3000; + __reserved_vsr_table = ALIGN (0x1); . = __reserved_vsr_table + 0x200; + __reserved_for_rom = ALIGN (0x1); . = __reserved_for_rom + 0xce00; + SECTION_vectors (ram, ALIGN(0x4), LMA_EQ_VMA) SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
--- a/packages/hal/powerpc/cogent/current/include/pkgconf/mlt_powerpc_cogent_ram.mlt +++ b/packages/hal/powerpc/cogent/current/include/pkgconf/mlt_powerpc_cogent_ram.mlt @@ -1,6 +1,9 @@ version 0 region ram 0 800000 0 ! -section vectors 0 1 0 1 1 1 1 1 0 0 text text ! +section reserved_vectors 3000 1 0 0 1 1 1 1 0 0 reserved_vsr_table reserved_vsr_table ! +section reserved_vsr_table 200 1 0 0 0 1 0 1 reserved_for_rom reserved_for_rom ! +section reserved_for_rom ce00 1 0 0 0 1 0 1 vectors vectors ! +section vectors 0 4 0 1 0 1 0 1 text text ! section text 0 4 0 1 0 1 0 1 fini fini ! section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 ! section rodata1 0 8 0 1 0 1 0 1 rodata rodata !
--- a/packages/hal/powerpc/cogent/current/include/pkgconf/mlt_powerpc_cogent_rom.h +++ b/packages/hal/powerpc/cogent/current/include/pkgconf/mlt_powerpc_cogent_rom.h @@ -5,8 +5,8 @@ #include <cyg/infra/cyg_type.h> #include <stddef.h> -#define CYGMEM_REGION_ram (0x2000) -#define CYGMEM_REGION_ram_SIZE (0x7fe000) +#define CYGMEM_REGION_ram (0x0) +#define CYGMEM_REGION_ram_SIZE (0x800000) #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) #define CYGMEM_REGION_rom (0xfff00000) #define CYGMEM_REGION_rom_SIZE (0x40000)
--- a/packages/hal/powerpc/cogent/current/include/pkgconf/mlt_powerpc_cogent_rom.ldi +++ b/packages/hal/powerpc/cogent/current/include/pkgconf/mlt_powerpc_cogent_rom.ldi @@ -31,7 +31,7 @@ MEMORY { rom : ORIGIN = 0xfff00000, LENGTH = 0x40000 - ram : ORIGIN = 0x00002000, LENGTH = 0x7fe000 + ram : ORIGIN = 0x00000000, LENGTH = 0x800000 } SECTIONS @@ -44,7 +44,9 @@ SECTIONS SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) - SECTION_data (ram, 0x2000, FOLLOWING (.gcc_except_table)) + __reserved_vectors = 0; . = __reserved_vectors + 0x3000; + __reserved_vsr_table = ALIGN (0x1); . = __reserved_vsr_table + 0x200; + SECTION_data (ram, ALIGN (0x10), FOLLOWING (.gcc_except_table)) SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA) SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) SECTIONS_END
--- a/packages/hal/powerpc/cogent/current/include/pkgconf/mlt_powerpc_cogent_rom.mlt +++ b/packages/hal/powerpc/cogent/current/include/pkgconf/mlt_powerpc_cogent_rom.mlt @@ -1,7 +1,9 @@ version 0 -region ram 2000 7fe000 0 ! +region ram 0 800000 0 ! region rom fff00000 40000 1 ! -section data 0 1 1 1 1 1 0 0 2000 sbss ! +section reserved_vectors 3000 1 0 0 1 1 1 1 0 0 reserved_vsr_table reserved_vsr_table ! +section reserved_vsr_table 200 4 0 0 0 1 0 1 data data ! +section data 0 10 0 1 0 1 0 1 sbss sbss ! section sbss 0 4 0 1 0 1 0 1 bss bss ! section bss 0 10 0 1 0 0 0 0 ! section vectors 0 1 0 1 1 1 1 1 fff00000 fff00000 text text !
--- a/packages/hal/powerpc/cogent/current/include/plf_cache.h +++ b/packages/hal/powerpc/cogent/current/include/plf_cache.h @@ -49,9 +49,14 @@ //--------------------------------------------------------------------------- // Initial cache enabling -#define CYGPRI_INIT_CACHES 1 -#ifdef CYG_HAL_STARTUP_RAM // Don't enable caches in ROM -# define CYGPRI_ENABLE_CACHES 1 +// Cogent board doesn't support burst access to the ROM and on the +// MPC8xx caches require burst. +#ifdef CYG_HAL_STARTUP_ROM +# define CYGPRI_INIT_CACHES +# undef CYGPRI_ENABLE_CACHES +#else +# define CYGPRI_INIT_CACHES +# define CYGPRI_ENABLE_CACHES #endif //-----------------------------------------------------------------------------
--- a/packages/hal/powerpc/cogent/current/include/plf_stub.h +++ b/packages/hal/powerpc/cogent/current/include/plf_stub.h @@ -84,9 +84,12 @@ externC void hal_cma_stub_init_break_irq //---------------------------------------------------------------------------- // Stub initializer. +#ifdef CYGSEM_HAL_ROM_MONITOR extern void diag_init (void); -#define HAL_STUB_PLATFORM_STUBS_INIT() diag_init() - +# define HAL_STUB_PLATFORM_INIT() diag_init() +#else +# define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT +#endif //---------------------------------------------------------------------------- // Reset.
--- a/packages/hal/powerpc/cogent/current/misc/STUBS_config +++ b/packages/hal/powerpc/cogent/current/misc/STUBS_config @@ -17,8 +17,8 @@ else exit 1 fi -$TCL $1/pkgconf.tcl \ - --target=powerpc --platform=cogent --startup=stubs \ +$TCL $1/pkgconf.tcl \ + --target=powerpc --platform=cogent --startup=rom \ --disable CYGPKG_KERNEL --disable CYGPKG_UITRON \ --disable CYGPKG_LIBC --disable CYGPKG_LIBM \ --disable CYGPKG_ERROR --disable CYGPKG_IO \ @@ -26,18 +26,36 @@ fi --disable CYGPKG_DEVICES_WATCHDOG patch <<END_OF_PATCH -p0 ---- pkgconf/hal.h~ Thu Jul 8 08:26:44 1999 -+++ pkgconf/hal.h Wed Jul 28 10:51:07 1999 -@@ -110,7 +110,7 @@ +--- pkgconf/hal.h.orig Thu Feb 10 09:05:07 2000 ++++ pkgconf/hal.h Thu Feb 10 09:04:56 2000 +@@ -122,7 +122,7 @@ } }}CFG_DATA */ -#define CYGFUN_HAL_COMMON_KERNEL_SUPPORT +#undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT + #undef CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL + + #ifdef CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL +@@ -243,7 +243,7 @@ + #define CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096 + #undef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING +-#define CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT ++#undef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + #undef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN + #undef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS + +@@ -272,7 +272,7 @@ + } + + }}CFG_DATA */ +-#define CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM ++#undef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM /* {{CFG_DATA - -@@ -369,10 +369,10 @@ + +@@ -423,10 +423,10 @@ }}CFG_DATA */ @@ -51,6 +69,15 @@ patch <<END_OF_PATCH -p0 /* * NOTE: +@@ -522,7 +522,7 @@ + + + /* Enable this when configuring as a ROM monitor (i.e., stub) */ +-#undef CYGSEM_HAL_ROM_MONITOR ++#define CYGSEM_HAL_ROM_MONITOR + + #include CYGBLD_HAL_TARGET_H + #include CYGBLD_HAL_PLATFORM_H END_OF_PATCH make
--- a/packages/hal/powerpc/cogent/current/src/hal_diag.c +++ b/packages/hal/powerpc/cogent/current/src/hal_diag.c @@ -70,7 +70,7 @@ #endif // Always use LCD when building a GDB stub ROM. -#ifdef CYG_HAL_STARTUP_STUBS +#ifdef CYGSEM_HAL_ROM_MONITOR #undef CYG_KERNEL_DIAG_SERIAL #undef CYG_KERNEL_DIAG_ROMART @@ -78,9 +78,9 @@ #endif // Assumption: all diagnostic output must be GDB packetized unless -// this is a ROM (i.e. totally stand-alone) system. -#ifdef CYG_HAL_STARTUP_ROM -#define HAL_DIAG_USES_HARDWARE +// this is a configuration for a stand-alone ROM system. +#if defined(CYG_HAL_STARTUP_ROM) && !defined(CYGSEM_HAL_ROM_MONITOR) +# define HAL_DIAG_USES_HARDWARE #endif @@ -309,7 +309,7 @@ void hal_diag_init() lcd_dis( LCD_LINE1, lcd_line[1] ); -#ifdef CYG_HAL_STARTUP_STUBS +#ifdef CYGSEM_HAL_ROM_MONITOR // It's handy to have the LCD initialized at reset when using it // for debugging output. {
--- a/packages/hal/powerpc/fads/current/ChangeLog +++ b/packages/hal/powerpc/fads/current/ChangeLog @@ -1,3 +1,22 @@ +2000-02-10 Jesper Skov <jskov@redhat.com> + + * include/plf_stub.h: + HAL_STUB_PLATFORM_STUBS_INIT->HAL_STUB_PLATFORM_INIT + +2000-02-08 Jesper Skov <jskov@redhat.com> + + * include/pkgconf/mlt_powerpc_fads_ram.ldi: + * include/pkgconf/mlt_powerpc_fads_ram.mlt: + Reserve space for vectors. + + * include/pkgconf/hal_powerpc_fads.h: + Don't rely on ROM monitor (isn't eCos compatible stub). + +2000-02-07 Jesper Skov <jskov@redhat.com> + + * include/pkgconf/hal_powerpc_fads.h: + Use MPC8xx CPU variant. + 2000-02-03 Jesper Skov <jskov@redhat.com> * src/fads.S:
--- a/packages/hal/powerpc/fads/current/include/pkgconf/hal_powerpc_fads.h +++ b/packages/hal/powerpc/fads/current/include/pkgconf/hal_powerpc_fads.h @@ -71,6 +71,8 @@ display "Motorola FADS PowerPC evaluation board" type radio parent CYGPKG_HAL_POWERPC + requires CYGPKG_HAL_POWERPC_PPC8xx + requires !CYGSEM_HAL_USE_ROM_MONITOR platform fads description " The FADS HAL package provides the support needed to run
--- a/packages/hal/powerpc/fads/current/include/pkgconf/mlt_powerpc_fads_ram.ldi +++ b/packages/hal/powerpc/fads/current/include/pkgconf/mlt_powerpc_fads_ram.ldi @@ -36,7 +36,10 @@ MEMORY SECTIONS { SECTIONS_BEGIN - SECTION_vectors (ram, 0x0, LMA_EQ_VMA) + __reserved_vectors = 0; . = __reserved_vectors + 0x3000; + __reserved_vsr_table = ALIGN (0x1); . = __reserved_vsr_table + 0x200; + __reserved_for_rom = ALIGN (0x1); . = __reserved_for_rom + 0xce00; + SECTION_vectors (ram, ALIGN (0x4), LMA_EQ_VMA) SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
--- a/packages/hal/powerpc/fads/current/include/pkgconf/mlt_powerpc_fads_ram.mlt +++ b/packages/hal/powerpc/fads/current/include/pkgconf/mlt_powerpc_fads_ram.mlt @@ -1,6 +1,8 @@ version 0 region ram 0 800000 0 ! -section vectors 0 1 0 1 1 1 1 1 0 0 text text ! +section reserved_vectors 3000 1 0 0 1 1 1 1 0 0 reserved_vsr_table reserved_vsr_table ! +section reserved_vsr_table 200 1 0 0 0 1 0 1 vectors vectors ! +section vectors 0 4 0 1 0 1 0 1 text text ! section text 0 4 0 1 0 1 0 1 fini fini ! section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 ! section rodata1 0 8 0 1 0 1 0 1 rodata rodata !
--- a/packages/hal/powerpc/fads/current/include/plf_stub.h +++ b/packages/hal/powerpc/fads/current/include/plf_stub.h @@ -65,7 +65,7 @@ //---------------------------------------------------------------------------- // Stub initializer. -#define HAL_STUB_PLATFORM_STUBS_INIT() CYG_EMPTY_STATEMENT +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT //---------------------------------------------------------------------------- // Reset.
--- a/packages/hal/powerpc/mbx/current/ChangeLog +++ b/packages/hal/powerpc/mbx/current/ChangeLog @@ -1,3 +1,24 @@ +2000-02-10 Jesper Skov <jskov@redhat.com> + + * include/plf_stub.h: + Removed HAL_STUB_PLATFORM_STUBS_INIT. + + * misc/STUBS_config: [added] + Removed stubs as a legal startup type. + +2000-02-07 Jesper Skov <jskov@redhat.com> + + * include/pkgconf/mlt_powerpc_mbx_ram.mlt: + * include/pkgconf/mlt_powerpc_mbx_rom.mlt: + Fixed some typos. + + * src/mbx.S: Use CYGHWR_HAL_POWERPC_BOARD_SPEED. + + * include/pkgconf/mlt*.*: Use new exception scheme. + * include/pkgconf/hal_powerpc_mbx.h: Use + CYGHWR_HAL_POWERPC_BOARD_SPEED. Use MPC8xx variant code. + + 2000-01-26 Jesper Skov <jskov@redhat.com> * include/plf_cache.h: Added.
--- a/packages/hal/powerpc/mbx/current/include/pkgconf/hal_powerpc_mbx.h +++ b/packages/hal/powerpc/mbx/current/include/pkgconf/hal_powerpc_mbx.h @@ -52,6 +52,7 @@ type radio parent CYGPKG_HAL_POWERPC requires CYGPKG_HAL_QUICC + requires CYGPKG_HAL_POWERPC_MPC860 platform mbx description " The MBX HAL package provides the support needed to run @@ -117,11 +118,9 @@ #define CYGNUM_HAL_RTC_NUMERATOR 1000000000 #define CYGNUM_HAL_RTC_DENOMINATOR 100 -# define CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED CYGHWR_HAL_POWERPC_BOARD_SPEED - -#if 40 == CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED +#if 40 == CYGHWR_HAL_POWERPC_BOARD_SPEED # define CYGNUM_HAL_RTC_PERIOD 25000 -#elif 50 == CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED +#elif 50 == CYGHWR_HAL_POWERPC_BOARD_SPEED # define CYGNUM_HAL_RTC_PERIOD 31250 #else # error Bad Board speed defined: see CYGBLD_HAL_PLATFORM_H
--- a/packages/hal/powerpc/mbx/current/include/pkgconf/mlt_powerpc_mbx_ram.h +++ b/packages/hal/powerpc/mbx/current/include/pkgconf/mlt_powerpc_mbx_ram.h @@ -5,6 +5,6 @@ #include <cyg/infra/cyg_type.h> #include <stddef.h> -#define CYGMEM_REGION_ram (0x10000) -#define CYGMEM_REGION_ram_SIZE (0x3f0000) +#define CYGMEM_REGION_ram (0x0) +#define CYGMEM_REGION_ram_SIZE (0x400000) #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
--- a/packages/hal/powerpc/mbx/current/include/pkgconf/mlt_powerpc_mbx_ram.ldi +++ b/packages/hal/powerpc/mbx/current/include/pkgconf/mlt_powerpc_mbx_ram.ldi @@ -30,13 +30,16 @@ MEMORY { - ram : ORIGIN = 0x00010000, LENGTH = 0x3f0000 + ram : ORIGIN = 0x00000000, LENGTH = 0x400000 } SECTIONS { SECTIONS_BEGIN - SECTION_vectors (ram, 0x10000, LMA_EQ_VMA) + __reserved_vectors = 0; . = __reserved_vectors + 0x3000; + __reserved_vsr_table = ALIGN (0x1); . = __reserved_vsr_table + 0x200; + __reserved_for_rom = ALIGN (0x1); . = __reserved_for_rom + 0xce00; + SECTION_vectors (ram, ALIGN (0x4), LMA_EQ_VMA) SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
--- a/packages/hal/powerpc/mbx/current/include/pkgconf/mlt_powerpc_mbx_ram.mlt +++ b/packages/hal/powerpc/mbx/current/include/pkgconf/mlt_powerpc_mbx_ram.mlt @@ -1,6 +1,9 @@ version 0 -region ram 10000 3f0000 0 ! -section vectors 0 1 0 1 1 1 1 1 10000 10000 text text ! +region ram 0 400000 0 ! +section reserved_vectors 3000 1 0 0 1 1 1 1 0 0 reserved_vsr_table reserved_vsr_table ! +section reserved_vsr_table 200 1 0 0 0 1 0 1 reserved_for_rom reserved_for_rom ! +section reserved_for_rom ce00 1 0 0 0 1 0 1 vectors vectors ! +section vectors 0 4 0 1 0 1 0 1 text text ! section text 0 4 0 1 0 1 0 1 fini fini ! section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 ! section rodata1 0 8 0 1 0 1 0 1 rodata rodata !
--- a/packages/hal/powerpc/mbx/current/include/pkgconf/mlt_powerpc_mbx_rom.h +++ b/packages/hal/powerpc/mbx/current/include/pkgconf/mlt_powerpc_mbx_rom.h @@ -5,8 +5,8 @@ #include <cyg/infra/cyg_type.h> #include <stddef.h> -#define CYGMEM_REGION_ram (0x2000) -#define CYGMEM_REGION_ram_SIZE (0x3fe000) +#define CYGMEM_REGION_ram (0x0) +#define CYGMEM_REGION_ram_SIZE (0x400000) #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) #define CYGMEM_REGION_rom (0xfe000000) #define CYGMEM_REGION_rom_SIZE (0x800000)
--- a/packages/hal/powerpc/mbx/current/include/pkgconf/mlt_powerpc_mbx_rom.ldi +++ b/packages/hal/powerpc/mbx/current/include/pkgconf/mlt_powerpc_mbx_rom.ldi @@ -31,7 +31,7 @@ MEMORY { rom : ORIGIN = 0xfe000000, LENGTH = 0x800000 - ram : ORIGIN = 0x00002000, LENGTH = 0x3fe000 + ram : ORIGIN = 0x00000000, LENGTH = 0x400000 } SECTIONS @@ -44,7 +44,9 @@ SECTIONS SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA) SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) - SECTION_data (ram, 0x2000, FOLLOWING (.gcc_except_table)) + __reserved_vectors = 0; . = __reserved_vectors + 0x3000; + __reserved_vsr_table = ALIGN (0x1); . = __reserved_vsr_table + 0x200; + SECTION_data (ram, ALIGN (0x10), FOLLOWING (.gcc_except_table)) SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA) SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) SECTIONS_END
--- a/packages/hal/powerpc/mbx/current/include/pkgconf/mlt_powerpc_mbx_rom.mlt +++ b/packages/hal/powerpc/mbx/current/include/pkgconf/mlt_powerpc_mbx_rom.mlt @@ -1,7 +1,9 @@ version 0 -region ram 2000 3fe000 0 ! +region ram 0 400000 0 ! region rom fe000000 800000 1 ! -section data 0 1 1 1 1 1 0 0 2000 sbss ! +section reserved_vectors 3000 1 0 0 1 1 1 1 0 0 reserved_vsr_table reserved_vsr_table ! +section reserved_vsr_table 200 4 0 0 0 1 0 1 data data ! +section data 0 10 0 1 0 1 0 1 sbss sbss ! section sbss 0 4 0 1 0 1 0 1 bss bss ! section bss 0 10 0 1 0 0 0 0 ! section vectors 0 1 0 1 1 1 1 1 fe000000 fe000000 text text !
--- a/packages/hal/powerpc/mbx/current/include/plf_cache.h +++ b/packages/hal/powerpc/mbx/current/include/plf_cache.h @@ -49,9 +49,9 @@ //--------------------------------------------------------------------------- // Initial cache enabling -#ifndef CYGSEM_HAL_ROM_MONITOR // unless we are making a stub rom -# define CYGPRI_INIT_CACHES 1 -# define CYGPRI_ENABLE_CACHES 1 +#ifdef CYGSEM_HAL_ROM_MONITOR +# define CYGPRI_INIT_CACHES +# define CYGPRI_ENABLE_CACHES #endif //-----------------------------------------------------------------------------
--- a/packages/hal/powerpc/mbx/current/include/plf_stub.h +++ b/packages/hal/powerpc/mbx/current/include/plf_stub.h @@ -74,8 +74,6 @@ externC void hal_mbx_set_led( int val ); // to distinguish eCos stub ROM ready state from either CygMon or app. #endif -#define HAL_STUB_PLATFORM_STUBS_INIT() CYG_EMPTY_STATEMENT - //---------------------------------------------------------------------------- #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT #define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mbx/current/misc/STUBS_config @@ -0,0 +1,85 @@ +#! /bin/sh +# Configure PowerPC/cogent eCos to create Cogent GDB stubs +# Ensure that PATH include the directory where the PPC tools reside. +# +# Run from an empty temporary directory with one argument: the path to +# the packages directory (i.e., where pkgconf.tcl lives). +# +# Output will be ./stubrom.bin which is suitable for burning into ROM. +# Remember to be careful with byte-endianess in the ROM programmer. + +if ( echo | tclsh ) 2>/dev/null ; then + TCL=tclsh +elif ( echo | cygtclsh80 ) 2>/dev/null ; then + TCL=cygtclsh80 +else + echo Could not find TCL interpreter + exit 1 +fi + +$TCL $1/pkgconf.tcl \ + --target=powerpc --platform=mbx --startup=rom \ + --disable CYGPKG_KERNEL --disable CYGPKG_UITRON \ + --disable CYGPKG_LIBC --disable CYGPKG_LIBM \ + --disable CYGPKG_ERROR --disable CYGPKG_IO \ + --disable CYGPKG_IO_SERIAL --disable CYGPKG_DEVICES_WALLCLOCK \ + --disable CYGPKG_DEVICES_WATCHDOG + +patch <<END_OF_PATCH -p0 +--- pkgconf/hal.h.orig Thu Feb 10 09:05:07 2000 ++++ pkgconf/hal.h Thu Feb 10 09:04:56 2000 +@@ -122,7 +122,7 @@ + } + + }}CFG_DATA */ +-#define CYGFUN_HAL_COMMON_KERNEL_SUPPORT ++#undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT + #undef CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL + + #ifdef CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL +@@ -243,7 +243,7 @@ + #define CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096 + #undef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING +-#define CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT ++#undef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + #undef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN + #undef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS + +@@ -272,7 +272,7 @@ + } + + }}CFG_DATA */ +-#define CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM ++#undef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + + /* {{CFG_DATA + +@@ -423,10 +423,10 @@ + + }}CFG_DATA */ + +-#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS ++#define CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + #undef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +-#define CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT +-#define CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT ++#undef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT ++#undef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + + /* + * NOTE: +@@ -522,7 +522,7 @@ + + + /* Enable this when configuring as a ROM monitor (i.e., stub) */ +-#undef CYGSEM_HAL_ROM_MONITOR ++#define CYGSEM_HAL_ROM_MONITOR + + #include CYGBLD_HAL_TARGET_H + #include CYGBLD_HAL_PLATFORM_H +END_OF_PATCH + +make +make -C hal/common/current/src/stubrom +powerpc-eabi-objcopy -O binary hal/common/current/src/stubrom/stubrom stubrom.bin
deleted file mode 100644 --- a/packages/hal/powerpc/mbx/current/misc/stubrom.perm +++ /dev/null @@ -1,37 +0,0 @@ -# -# A configuration for building a GDB stub ROM for the Motorola MBX board, -# with MPC 860 or 821 CPU. -# -# To build the ROMs: -# 1. Create a build directory and cd into it. -# 2. Run: permtest.tcl --srcdir=<SOURCEDIR> <SOURCEDIR>/hal/powerpc/mbx/current/misc/stubrom.perm -# Where <SOURCEDIR> is the path to your source repository. -# (If necessary, make sure the system clock speed is set correctly in -# pkgconf/hal_powerpc_mbx.h: 40MHz (MPC821) versus 50MHz (MPC860) by default) -# If you do not have permtest, use the config tool or an editor to make -# the changes listed below to the relevant configuration files. -# If you intend to install the image into the 32-bit flash device instead of -# the 8-bit socketed ROM, set the option CYGHWR_HAL_POWERPC_MBX_BOOT_32BIT_FLASH -# in hal_powerpc_mbx.h -# 3. Run: make -# 4. Run: make -C hal/common/current/src/stubrom -# -# The file hal/common/current/src/stubrom/stubrom will be an excutable of the ROM. -# Use objcopy to convert this to the appropriate format for your PROM burner: -# powerpc-eabi-objcopy -O binary hal/common/current/src/stubrom/stubrom stubrom.img -# Enjoy! -# - -pkgconf --target=powerpc --platform=mbx --startup=rom --disable-kernel --disable-uitron --disable-libc --disable-libm --disable-io --disable-io_serial --disable-wallclock --disable-watchdog - -header hal.h { - enable CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS - disable CYGFUN_HAL_COMMON_KERNEL_SUPPORT - disable CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT - disable CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT - disable CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT - enable CYG_HAL_ROM_MONITOR -} - -# enable CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT excluded for now -
--- a/packages/hal/powerpc/mbx/current/src/mbx.S +++ b/packages/hal/powerpc/mbx/current/src/mbx.S @@ -55,9 +55,9 @@ #------------------------------------------------------------------------------ # this is kept thus for commonality with CygMon code -#if 40 == CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED +#if 40 == CYGHWR_HAL_POWERPC_BOARD_SPEED # define __40MHZ 1 -#elif 50 == CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED +#elif 50 == CYGHWR_HAL_POWERPC_BOARD_SPEED # define __50MHZ 1 #else # error Bad Board speed defined: see CYGBLD_HAL_PLATFORM_H
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8xx/current/ChangeLog @@ -0,0 +1,46 @@ +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/var_intr.c (Cyg_InterruptHANDLED): Mask out CALL_DSR flag + before return. + + * tests/intr0.c: Moved here from arch. + + * src/var_intr.c: + * src/PKGconf.mak: + Move 860 arbiters to variant sources. + +2000-02-10 Jesper Skov <jskov@redhat.com> + + * include/var_intr.h: Bad undef/define order fixed. + + * include/variant.inc: Renamed default VSR handlers. + +2000-02-07 Jesper Skov <jskov@redhat.com> + + * Created. + +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8xx/current/include/pkgconf/hal_powerpc_mpc8xx.h @@ -0,0 +1,90 @@ +#ifndef CYGONCE_PKGCONF_HAL_POWERPC_MPC8XX_H +#define CYGONCE_PKGCONF_HAL_POWERPC_MPC8XX_H +// ==================================================================== +// +// pkgconf/hal_powerpc_mpc8xx.h +// +// HAL configuration file +// +// ==================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 2000-02-04 +// Purpose: To allow the user to edit HAL configuration options. +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +#include <pkgconf/hal_powerpc.h> +#include CYGBLD_HAL_PLATFORM_H + +/* ------------------------------------------------------------------- + * Decide which variant of the PowerPC family we have. + + {{CFG_DATA + + cdl_package CYGPKG_HAL_POWERPC_MPC8xx { + display "PowerPC variant" + type radio + parent CYGFUN_HAL_POWERPC_VARIANTS + target powerpc_mpc8xx + description " + The MPC8xx architecture HAL package provides generic support + for this processor architecture. It is also necessary to + select a specific target platform HAL package." + } + + cdl_option CYGPKG_HAL_POWERPC_MPC860 { + display "MPC860 microprocessor" + parent CYGPKG_HAL_POWERPC_MPC860 + type radio + description " + The MPC860 microprocessor. This is an embedded part that in + addition to the PowerPC processor core has built in peripherals + such as memory controllers, DMA controllers, serial ports and + timers/counters." + } + + }}CFG_DATA */ + +#define CYGPKG_HAL_POWERPC_MPC860 + +// ------------------------------------------------------------------- +// Characterize the CPU so that the generic architecture part can +// configure itself. + +#undef CYGHWR_HAL_POWERPC_FPU // We have no FPU +#define CYGPKG_HAL_POWERPC_MSBFIRST // Big-endian CPU +#define CYGSEM_HAL_USE_ROM_MONITOR + +//---------------------------------------------------------------------- +#endif // CYGONCE_PKGCONF_HAL_POWERPC_MPC8XX_H +// EOF hal_powerpc_mpc8xx.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8xx/current/include/var_cache.h @@ -0,0 +1,375 @@ +#ifndef CYGONCE_VAR_CACHE_H +#define CYGONCE_VAR_CACHE_H +//============================================================================= +// +// var_cache.h +// +// Variant HAL cache control API +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:nickg, jskov +// Date: 2000-04-02 +// Purpose: Variant cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations on the MPC8xx variant CPUs. +// Usage: Is included via the architecture cache header: +// #include <cyg/hal/hal_cache.h> +// ... +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/ppc_regs.h> + +#include <cyg/hal/plf_cache.h> + + +//----------------------------------------------------------------------------- +// Cache dimensions - these vary between the 8xx sub-models + +#if defined(CYGPKG_HAL_POWERPC_MPC860) +// Data cache +#define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes +#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line +#define HAL_DCACHE_WAYS 2 // Associativity of the cache + +// Instruction cache +#define HAL_ICACHE_SIZE 4096 // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line +#define HAL_ICACHE_WAYS 2 // Associativity of the cache +#endif // defined(CYGPKG_HAL_POWERPC_MPC860) + +#if defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850) +// Data cache +#define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes +#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line +#define HAL_DCACHE_WAYS 2 // Associativity of the cache + +// Instruction cache +#define HAL_ICACHE_SIZE 2048 // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line +#define HAL_ICACHE_WAYS 2 // Associativity of the cache +#endif // defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850) + +#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() \ + asm volatile ("sync;" \ + "mtspr %0, %1;" \ + : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CE)) + +// Disable the data cache +#define HAL_DCACHE_DISABLE() \ + asm volatile ("sync;" \ + "mtspr %0, %1;" \ + : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CD)) + +// Invalidate the entire cache +// Note: Any locked lines will not be invalidated. +#define HAL_DCACHE_INVALIDATE_ALL() \ + asm volatile ("sync;" \ + "mtspr %0, %1;" \ + : : "I" (CYGARC_REG_DC_CST), \ + "r" (CYGARC_REG_DC_CMD_IA)) + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() \ + CYG_MACRO_START \ + cyg_int32 i; \ + for (i = 0; i < HAL_DCACHE_SETS; i++){ \ + asm volatile ("sync;" \ + "mtspr %0, %2;" \ + "mtspr %1, %4;" \ + "mtspr %0, %3;" \ + "mtspr %1, %4;" \ + : /* no output */ \ + : /* %0 */ "I" (CYGARC_REG_DC_ADR), \ + /* %1 */ "I" (CYGARC_REG_DC_CST), \ + /* %2 */ "r" (CYGARC_REG_DC_ADR_WAY0 \ + |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \ + /* %3 */ "r" (CYGARC_REG_DC_ADR_WAY1 \ + |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \ + /* %4 */ "r" (CYGARC_REG_DC_CMD_FL)); \ + } \ + CYG_MACRO_END + +// Query the state of the data cache +#define HAL_DCACHE_IS_ENABLED(_state_) \ + asm volatile ("mfspr %0, %1;" \ + "rlwinm %0,%0,1,31,31;" \ + : "=r" (_state_) : "I" (CYGARC_REG_DC_CST)) + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. + +// Restrictions: This implementation only allows a single area to be +// locked at any one time. This area must be 2kB or less in size. + +// Implementation: Flush entire cache, then invalidate it. This +// ensures that the fetched data go into way0. + +#define HAL_DCACHE_LOCK(_base_, _size_) \ + CYG_MACRO_START \ + cyg_int32 __scratch; \ + cyg_uint32 __base = (cyg_uint32)(_base_); \ + cyg_int32 __l = ((__base / HAL_DCACHE_LINE_SIZE) % HAL_DCACHE_SETS); \ + cyg_int32 __count = ((_size_) / HAL_DCACHE_LINE_SIZE); \ + HAL_DCACHE_DISABLE(); \ + HAL_DCACHE_SYNC (); \ + HAL_DCACHE_INVALIDATE_ALL (); \ + HAL_DCACHE_ENABLE(); \ + do { \ + asm volatile ("lbz %0,0(%1);" \ + "sync;" \ + "mtspr %2, %4;" \ + "mtspr %3, %5;" \ + : /* %0 */ "=&r" (__scratch) \ + : /* %1 */ "b" (__base), \ + /* %2 */ "I" (CYGARC_REG_DC_ADR), \ + /* %3 */ "I" (CYGARC_REG_DC_CST), \ + /* %4 */ "r" (CYGARC_REG_DC_ADR_WAY0 \ + |(__l<<CYGARC_REG_DC_ADR_SETID_SHIFT)), \ + /* %5 */ "r" (CYGARC_REG_DC_CMD_LL)); \ + __l++; \ + __base += HAL_DCACHE_LINE_SIZE; \ + } while (__count--); \ + CYG_MACRO_END + + +// Undo a previous lock operation + +// Implementation: Unlocks entire cache. + +#define HAL_DCACHE_UNLOCK(_base_, _size_) \ + HAL_DCACHE_UNLOCK_ALL() + + +// Unlock entire cache +#define HAL_DCACHE_UNLOCK_ALL() \ + CYG_MACRO_START \ + asm volatile ("sync;" \ + "mtspr %0, %1;" \ + : : "I" (CYGARC_REG_DC_CST), \ + "r" (CYGARC_REG_DC_CMD_UA)); \ + CYG_MACRO_END + + + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +#define HAL_DCACHE_FLUSH( _base_ , _size_ ) \ + CYG_MACRO_START \ + cyg_uint32 __base = (cyg_uint32) (_base_); \ + cyg_int32 __size = (cyg_int32) (_size_); \ + while (__size > 0) { \ + asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \ + __base += HAL_DCACHE_LINE_SIZE; \ + __size -= HAL_DCACHE_LINE_SIZE; \ + } \ + CYG_MACRO_END + +// Invalidate cache lines in the given range without writing to memory. +#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \ + CYG_MACRO_START \ + cyg_uint32 __base = (cyg_uint32) (_base_); \ + cyg_int32 __size = (cyg_int32) (_size_); \ + while (__size > 0) { \ + asm volatile ("dcbi 0,%0;sync;" : : "r" (__base)); \ + __base += HAL_DCACHE_LINE_SIZE; \ + __size -= HAL_DCACHE_LINE_SIZE; \ + } \ + CYG_MACRO_END + +// Write dirty cache lines to memory for the given address range. +#define HAL_DCACHE_STORE( _base_ , _size_ ) \ + CYG_MACRO_START \ + cyg_uint32 __base = (cyg_uint32) (_base_); \ + cyg_int32 __size = (cyg_int32) (_size_); \ + while (__size > 0) { \ + asm volatile ("dcbst 0,%0;sync;" : : "r" (__base)); \ + __base += HAL_DCACHE_LINE_SIZE; \ + __size -= HAL_DCACHE_LINE_SIZE; \ + } \ + CYG_MACRO_END + +// Preread the given range into the cache with the intention of reading +// from it later. +#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) \ + CYG_MACRO_START \ + cyg_uint32 __base = (cyg_uint32) (_base_); \ + cyg_int32 __size = (cyg_int32) (_size_); \ + while (__size > 0) { \ + asm volatile ("dcbt 0,%0;" : : "r" (__base)); \ + __base += HAL_DCACHE_LINE_SIZE; \ + __size -= HAL_DCACHE_LINE_SIZE; \ + } \ + CYG_MACRO_END + +// Preread the given range into the cache with the intention of writing +// to it later. +#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) \ + CYG_MACRO_START \ + cyg_uint32 __base = (cyg_uint32) (_base_); \ + cyg_int32 __size = (cyg_int32) (_size_); \ + while (__size > 0) { \ + asm volatile ("dcbtst 0,%0;" : : "r" (__base)); \ + __base += HAL_DCACHE_LINE_SIZE; \ + __size -= HAL_DCACHE_LINE_SIZE; \ + } \ + CYG_MACRO_END + +// Allocate and zero the cache lines associated with the given range. +#define HAL_DCACHE_ZERO( _base_ , _size_ ) \ + CYG_MACRO_START \ + cyg_uint32 __base = (cyg_uint32) (_base_); \ + cyg_int32 __size = (cyg_int32) (_size_); \ + while (__size > 0) { \ + asm volatile ("dcbz 0,%0;" : : "r" (__base)); \ + __base += HAL_DCACHE_LINE_SIZE; \ + __size -= HAL_DCACHE_LINE_SIZE; \ + } \ + CYG_MACRO_END + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() \ + asm volatile ("isync;" \ + "mtspr %0, %1;" \ + "isync" \ + : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CE)) + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() \ + asm volatile ("isync;" \ + "mtspr %0, %1;" \ + "isync" \ + : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CD)) + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() \ + asm volatile ("isync;" \ + "mtspr %0, %1;" \ + "isync" \ + : : "I" (CYGARC_REG_IC_CST), \ + "r" (CYGARC_REG_IC_CMD_IA)) + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() \ + HAL_ICACHE_INVALIDATE_ALL() + +// Query the state of the instruction cache +#define HAL_ICACHE_IS_ENABLED(_state_) \ + asm volatile ("mfspr %0, %1;" \ + "rlwinm %0,%0,1,31,31;" \ + : "=r" (_state_) : "I" (CYGARC_REG_IC_CST)) + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. + +// Restrictions: This implementation only allows a single area to be +// locked at any one time. This area must be 2kB or less in size. + +// Implementation: Flush entire cache, then invalidate it. This +// ensures that the fetched data go into way0. + +#define HAL_ICACHE_LOCK(_base_, _size_) \ + CYG_MACRO_START \ + unsigned long __base = \ + ((unsigned long) (_base_)) & ~(HAL_ICACHE_LINE_SIZE-1); \ + int __count = ((_size_) / HAL_ICACHE_LINE_SIZE); \ + do { \ + asm volatile ("mtspr %0, %2;" \ + "mtspr %1, %3;" \ + "isync;" \ + : /* no output */ \ + : /* %0 */ "I" (CYGARC_REG_IC_ADR), \ + /* %1 */ "I" (CYGARC_REG_IC_CST), \ + /* %2 */ "r" (__base), \ + /* %3 */ "r" (CYGARC_REG_IC_CMD_LL)); \ + __base += HAL_ICACHE_LINE_SIZE; \ + } while (__count--); \ + CYG_MACRO_END + +// Undo a previous lock operation + +// Implementation: Unlocks entire cache. +#define HAL_ICACHE_UNLOCK(_base_, _size_) \ + HAL_ICACHE_UNLOCK_ALL() + +// Unlock entire cache +#define HAL_ICACHE_UNLOCK_ALL() \ + CYG_MACRO_START \ + asm volatile ("sync;" \ + "mtspr %0, %1;" \ + : : "I" (CYGARC_REG_IC_CST), \ + "r" (CYGARC_REG_IC_CMD_UA)); \ + CYG_MACRO_END + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_VAR_CACHE_H +// End of var_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8xx/current/include/var_intr.h @@ -0,0 +1,688 @@ +#ifndef CYGONCE_VAR_INTR_H +#define CYGONCE_VAR_INTR_H +//============================================================================= +// +// var_intr.h +// +// Variant HAL interrupt and clock support +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:nickg, jskov, jlarmour, hmt +// Date: 2000-04-02 +// Purpose: Variant interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock on the MPC8xx variant CPUs. +// Usage: Is included via the architecture interrupt header: +// #include <cyg/hal/hal_intr.h> +// ... +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // types + +#include <cyg/hal/ppc_regs.h> // register definitions + +#include <cyg/hal/hal_io.h> // io macros +#include <cyg/infra/cyg_ass.h> // CYG_FAIL + +//----------------------------------------------------------------------------- +// Exception vectors. + +// Additional exceptions on the MPC8xx CPUs +#define CYGNUM_HAL_VECTOR_RESERVED_F 15 +#define CYGNUM_HAL_VECTOR_SW_EMUL 16 +#define CYGNUM_HAL_VECTOR_ITLB_MISS 17 +#define CYGNUM_HAL_VECTOR_DTLB_MISS 18 +#define CYGNUM_HAL_VECTOR_ITLB_ERROR 19 +#define CYGNUM_HAL_VECTOR_DTLB_ERROR 20 +#define CYGNUM_HAL_VECTOR_RESERVED_15 21 +#define CYGNUM_HAL_VECTOR_RESERVED_16 22 +#define CYGNUM_HAL_VECTOR_RESERVED_17 23 +#define CYGNUM_HAL_VECTOR_RESERVED_18 24 +#define CYGNUM_HAL_VECTOR_RESERVED_19 25 +#define CYGNUM_HAL_VECTOR_RESERVED_1A 26 +#define CYGNUM_HAL_VECTOR_RESERVED_1B 27 +#define CYGNUM_HAL_VECTOR_DATA_BP 28 +#define CYGNUM_HAL_VECTOR_INSTRUCTION_BP 29 +#define CYGNUM_HAL_VECTOR_PERIPHERAL_BP 30 +#define CYGNUM_HAL_VECTOR_NMI 31 + +#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_NMI + +// These are the values used when passed out to an +// external exception handler using cyg_hal_deliver_exception() + +#define CYGNUM_HAL_EXCEPTION_RESERVED_0 CYGNUM_HAL_VECTOR_RESERVED_0 +#define CYGNUM_HAL_EXCEPTION_MACHINE_CHECK CYGNUM_HAL_VECTOR_MACHINE_CHECK +#ifdef CYGPKG_HAL_POWERPC_MPC860 +// The MPC860 does not generate DSI and ISI: instead it goes to machine +// check, so that a software VM system can then call into vectors 0x300 or +// 0x400 if the address is truly invalid rather than merely not in the TLB +// right now. Shades of IBM wanting to port OS/MVS here! +// See pp 7-9/10 in "PowerQUICC - MPC860 User's Manual" +# undef CYGNUM_HAL_EXCEPTION_DATA_ACCESS +# define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_MACHINE_CHECK +// do not define catchers for DSI and ISI - should never happen. +# undef CYGNUM_HAL_EXCEPTION_MACHINE_CHECK +# undef CYGNUM_HAL_EXCEPTION_CODE_ACCESS +#else +# define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_DSI +# define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_ISI +#endif +#define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS \ + CYGNUM_HAL_VECTOR_ALIGNMENT +#define CYGNUM_HAL_EXCEPTION_FPU_NOT_AVAIL CYGNUM_HAL_VECTOR_FP_UNAVAILABLE +#define CYGNUM_HAL_EXCEPTION_RESERVED_A CYGNUM_HAL_VECTOR_RESERVED_A +#define CYGNUM_HAL_EXCEPTION_RESERVED_B CYGNUM_HAL_VECTOR_RESERVED_B +#define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL CYGNUM_HAL_VECTOR_SYSTEM_CALL +#define CYGNUM_HAL_EXCEPTION_TRACE CYGNUM_HAL_VECTOR_TRACE +#define CYGNUM_HAL_EXCEPTION_FP_ASSIST CYGNUM_HAL_VECTOR_FP_ASSIST +#define CYGNUM_HAL_EXCEPTION_RESERVED_F CYGNUM_HAL_VECTOR_RESERVED_F +#define CYGNUM_HAL_EXCEPTION_SW_EMUL CYGNUM_HAL_VECTOR_SW_EMUL +#define CYGNUM_HAL_EXCEPTION_CODE_TLBMISS_ACCESS CYGNUM_HAL_VECTOR_ITLB_MISS +#define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS CYGNUM_HAL_VECTOR_DTLB_MISS +#define CYGNUM_HAL_EXCEPTION_CODE_TLBERROR_ACCESS \ + CYGNUM_HAL_VECTOR_ITLB_ERROR +#define CYGNUM_HAL_EXCEPTION_DATA_TLBERROR_ACCESS \ + CYGNUM_HAL_VECTOR_DTLB_ERROR +#define CYGNUM_HAL_EXCEPTION_RESERVED_15 CYGNUM_HAL_VECTOR_RESERVED_15 +#define CYGNUM_HAL_EXCEPTION_RESERVED_16 CYGNUM_HAL_VECTOR_RESERVED_16 +#define CYGNUM_HAL_EXCEPTION_RESERVED_17 CYGNUM_HAL_VECTOR_RESERVED_17 +#define CYGNUM_HAL_EXCEPTION_RESERVED_18 CYGNUM_HAL_VECTOR_RESERVED_18 +#define CYGNUM_HAL_EXCEPTION_RESERVED_19 CYGNUM_HAL_VECTOR_RESERVED_19 +#define CYGNUM_HAL_EXCEPTION_RESERVED_1A CYGNUM_HAL_VECTOR_RESERVED_1A +#define CYGNUM_HAL_EXCEPTION_RESERVED_1B CYGNUM_HAL_VECTOR_RESERVED_1B +#define CYGNUM_HAL_EXCEPTION_DATA_BP CYGNUM_HAL_VECTOR_DATA_BP +#define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP CYGNUM_HAL_VECTOR_INSTRUCTION_BP +#define CYGNUM_HAL_EXCEPTION_PERIPHERAL_BP CYGNUM_HAL_VECTOR_PERIPHERAL_BP +#define CYGNUM_HAL_EXCEPTION_NMI CYGNUM_HAL_VECTOR_NMI + +#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_RESERVED_0 +#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_NMI + +#define CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED + +//----------------------------------------------------------------------------- +// Interrupts + +// The first level of external interrupts +#define CYGNUM_HAL_INTERRUPT_SIU_IRQ0 1 +#define CYGNUM_HAL_INTERRUPT_SIU_LVL0 2 +#define CYGNUM_HAL_INTERRUPT_SIU_IRQ1 3 +#define CYGNUM_HAL_INTERRUPT_SIU_LVL1 4 +#define CYGNUM_HAL_INTERRUPT_SIU_IRQ2 5 +#define CYGNUM_HAL_INTERRUPT_SIU_LVL2 6 +#define CYGNUM_HAL_INTERRUPT_SIU_IRQ3 7 +#define CYGNUM_HAL_INTERRUPT_SIU_LVL3 8 +#define CYGNUM_HAL_INTERRUPT_SIU_IRQ4 9 +#define CYGNUM_HAL_INTERRUPT_SIU_LVL4 10 +#define CYGNUM_HAL_INTERRUPT_SIU_IRQ5 11 +#define CYGNUM_HAL_INTERRUPT_SIU_LVL5 12 +#define CYGNUM_HAL_INTERRUPT_SIU_IRQ6 13 +#define CYGNUM_HAL_INTERRUPT_SIU_LVL6 14 +#define CYGNUM_HAL_INTERRUPT_SIU_IRQ7 15 +#define CYGNUM_HAL_INTERRUPT_SIU_LVL7 16 + +// Further decoded interrups +#define CYGNUM_HAL_INTERRUPT_SIU_TB_A 17 +#define CYGNUM_HAL_INTERRUPT_SIU_TB_B 18 +#define CYGNUM_HAL_INTERRUPT_SIU_PIT 19 +#define CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC 20 +#define CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR 21 +#define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_A_IRQ 22 +#define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_A_CHLVL 23 +#define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_B_IRQ 24 +#define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_B_CHLVL 25 +#define CYGNUM_HAL_INTERRUPT_SIU_CPM 26 + +// Even further... +#define CYGNUM_HAL_INTERRUPT_CPM_PC15 27 +#define CYGNUM_HAL_INTERRUPT_CPM_SCC1 28 +#define CYGNUM_HAL_INTERRUPT_CPM_SCC2 29 +#define CYGNUM_HAL_INTERRUPT_CPM_SCC3 30 +#define CYGNUM_HAL_INTERRUPT_CPM_SCC4 31 +#define CYGNUM_HAL_INTERRUPT_CPM_PC14 32 +#define CYGNUM_HAL_INTERRUPT_CPM_TIMER1 33 +#define CYGNUM_HAL_INTERRUPT_CPM_PC13 34 +#define CYGNUM_HAL_INTERRUPT_CPM_PC12 35 +#define CYGNUM_HAL_INTERRUPT_CPM_SDMA 36 +#define CYGNUM_HAL_INTERRUPT_CPM_IDMA1 37 +#define CYGNUM_HAL_INTERRUPT_CPM_IDMA2 38 +#define CYGNUM_HAL_INTERRUPT_CPM_RESERVED_13 39 +#define CYGNUM_HAL_INTERRUPT_CPM_TIMER2 40 +#define CYGNUM_HAL_INTERRUPT_CPM_RISCTT 41 +#define CYGNUM_HAL_INTERRUPT_CPM_I2C 42 +#define CYGNUM_HAL_INTERRUPT_CPM_PC11 43 +#define CYGNUM_HAL_INTERRUPT_CPM_PC10 44 +#define CYGNUM_HAL_INTERRUPT_CPM_RESERVED_0D 45 +#define CYGNUM_HAL_INTERRUPT_CPM_TIMER3 46 +#define CYGNUM_HAL_INTERRUPT_CPM_PC9 47 +#define CYGNUM_HAL_INTERRUPT_CPM_PC8 48 +#define CYGNUM_HAL_INTERRUPT_CPM_PC7 49 +#define CYGNUM_HAL_INTERRUPT_CPM_RESERVED_08 50 +#define CYGNUM_HAL_INTERRUPT_CPM_TIMER4 51 +#define CYGNUM_HAL_INTERRUPT_CPM_PC6 52 +#define CYGNUM_HAL_INTERRUPT_CPM_SPI 53 +#define CYGNUM_HAL_INTERRUPT_CPM_SMC1 54 +#define CYGNUM_HAL_INTERRUPT_CPM_SMC2_PIP 55 +#define CYGNUM_HAL_INTERRUPT_CPM_PC5 56 +#define CYGNUM_HAL_INTERRUPT_CPM_PC4 57 +#define CYGNUM_HAL_INTERRUPT_CPM_ERROR 58 + +#define CYGNUM_HAL_INTERRUPT_CPM_FIRST CYGNUM_HAL_INTERRUPT_CPM_PC15 +#define CYGNUM_HAL_INTERRUPT_CPM_LAST CYGNUM_HAL_INTERRUPT_CPM_ERROR + +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_CPM_LAST +#endif + + +//-------------------------------------------------------------------------- +// Interrupt controller access + +#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED + +#ifdef CYGPKG_HAL_POWERPC_MPC860 + +static __inline__ void +cyg_hal_interrupt_mask ( cyg_uint32 vector ) +{ + switch (vector) { + case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7: + { + // SIU interrupt vectors + cyg_uint32 simask; + + HAL_READ_UINT32 (CYGARC_REG_IMM_SIMASK, simask); + simask &= ~(((cyg_uint32) CYGARC_REG_IMM_SIMASK_IRQ0) + >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0)); + HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIMASK, simask); + break; + } + case CYGNUM_HAL_INTERRUPT_SIU_TB_A: + { + // TimeBase A interrupt + cyg_uint16 tbscr; + + HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); + tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFAE); + HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); + break; + } + case CYGNUM_HAL_INTERRUPT_SIU_TB_B: + { + // TimeBase B interrupt + cyg_uint16 tbscr; + + HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); + tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFBE); + HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); + break; + } + case CYGNUM_HAL_INTERRUPT_SIU_PIT: + { + // Periodic Interrupt + cyg_uint16 piscr; + + HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); + piscr &= ~(CYGARC_REG_IMM_PISCR_PIE); + HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr); + break; + } + case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC: + { + // Real Time Clock Second + cyg_uint16 rtcsc; + + HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); + rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SIE); + HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); + break; + } + case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR: + { + // Real Time Clock Alarm + cyg_uint16 rtcsc; + + HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); + rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALE); + HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); + break; + } + // PCMCIA_A_IRQ + // PCMCIA_A_CHLVL + // PCMCIA_B_IRQ + // PCMCIA_B_CHLVL + case CYGNUM_HAL_INTERRUPT_SIU_CPM: + { + // Communications Processor Module + cyg_uint32 cicr; + + HAL_READ_UINT32 (CYGARC_REG_IMM_CICR, cicr); + cicr &= ~(CYGARC_REG_IMM_CICR_IEN); + HAL_WRITE_UINT32 (CYGARC_REG_IMM_CICR, cicr); + break; + } + case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST: + { + // CPM interrupts + cyg_uint32 cimr; + + HAL_READ_UINT32 (CYGARC_REG_IMM_CIMR, cimr); + cimr &= ~(((cyg_uint32) 0x80000000) + >> (vector - CYGNUM_HAL_INTERRUPT_CPM_FIRST)); + HAL_WRITE_UINT32 (CYGARC_REG_IMM_CIMR, cimr); + break; + } + default: + CYG_FAIL("Unknown Interrupt!!!"); + break; + } +} + +static __inline__ void +cyg_hal_interrupt_unmask ( cyg_uint32 vector ) +{ + switch (vector) { + case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7: + { + // SIU interrupt vectors + cyg_uint32 simask; + + HAL_READ_UINT32 (CYGARC_REG_IMM_SIMASK, simask); + simask |= (((cyg_uint32) CYGARC_REG_IMM_SIMASK_IRQ0) + >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0)); + HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIMASK, simask); + break; + } + case CYGNUM_HAL_INTERRUPT_SIU_TB_A: + { + // TimeBase A interrupt + cyg_uint16 tbscr; + + HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); + tbscr |= CYGARC_REG_IMM_TBSCR_REFAE; + HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); + break; + } + case CYGNUM_HAL_INTERRUPT_SIU_TB_B: + { + // TimeBase B interrupt + cyg_uint16 tbscr; + + HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); + tbscr |= CYGARC_REG_IMM_TBSCR_REFBE; + HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); + break; + } + case CYGNUM_HAL_INTERRUPT_SIU_PIT: + { + // Periodic Interrupt + cyg_uint16 piscr; + + HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); + piscr |= CYGARC_REG_IMM_PISCR_PIE; + HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr); + break; + } + case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC: + { + // Real Time Clock Second + cyg_uint16 rtcsc; + + HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); + rtcsc |= CYGARC_REG_IMM_RTCSC_SIE; + HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); + break; + } + case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR: + { + // Real Time Clock Alarm + cyg_uint16 rtcsc; + + HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); + rtcsc |= CYGARC_REG_IMM_RTCSC_ALE; + HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); + break; + } + // PCMCIA_A_IRQ + // PCMCIA_A_CHLVL + // PCMCIA_B_IRQ + // PCMCIA_B_CHLVL + case CYGNUM_HAL_INTERRUPT_SIU_CPM: + { + // Communications Processor Module + cyg_uint32 cicr; + + HAL_READ_UINT32 (CYGARC_REG_IMM_CICR, cicr); + cicr |= CYGARC_REG_IMM_CICR_IEN; + HAL_WRITE_UINT32 (CYGARC_REG_IMM_CICR, cicr); + break; + } + case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST: + { + // CPM interrupts + cyg_uint32 cimr; + + HAL_READ_UINT32 (CYGARC_REG_IMM_CIMR, cimr); + cimr |= (((cyg_uint32) 0x80000000) + >> (vector - CYGNUM_HAL_INTERRUPT_CPM_FIRST)); + HAL_WRITE_UINT32 (CYGARC_REG_IMM_CIMR, cimr); + break; + } + default: + CYG_FAIL("Unknown Interrupt!!!"); + break; + } +} + +static __inline__ void +cyg_hal_interrupt_acknowledge ( cyg_uint32 vector ) +{ + switch (vector) { + case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7: + { + // SIU interrupt vectors + cyg_uint32 sipend; + + // When IRQx is configured as an edge interrupt it needs to be + // cleared. Write to INTx and IRQ/level bits are ignore so + // it's safe to do always. + HAL_READ_UINT32 (CYGARC_REG_IMM_SIPEND, sipend); + sipend |= (((cyg_uint32) CYGARC_REG_IMM_SIPEND_IRQ0) + >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0)); + HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIPEND, sipend); + break; + } + case CYGNUM_HAL_INTERRUPT_SIU_TB_A: + { + // TimeBase A interrupt + cyg_uint16 tbscr; + + HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); + tbscr |= CYGARC_REG_IMM_TBSCR_REFA; + HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); + break; + } + case CYGNUM_HAL_INTERRUPT_SIU_TB_B: + { + // TimeBase B interrupt + cyg_uint16 tbscr; + + HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); + tbscr |= CYGARC_REG_IMM_TBSCR_REFB; + HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); + break; + } + case CYGNUM_HAL_INTERRUPT_SIU_PIT: + { + // Periodic Interrupt + cyg_uint16 piscr; + + HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); + piscr |= CYGARC_REG_IMM_PISCR_PS; + HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr); + break; + } + case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC: + { + // Real Time Clock Second + cyg_uint16 rtcsc; + + HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); + rtcsc |= CYGARC_REG_IMM_RTCSC_SEC; + HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); + break; + } + case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR: + { + // Real Time Clock Alarm + cyg_uint16 rtcsc; + + HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); + rtcsc |= CYGARC_REG_IMM_RTCSC_ALR; + HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); + break; + } + // PCMCIA_A_IRQ + // PCMCIA_A_CHLVL + // PCMCIA_B_IRQ + // PCMCIA_B_CHLVL + case CYGNUM_HAL_INTERRUPT_SIU_CPM: + // Communications Processor Module + // The CPM interrupts must be acknowledged individually. + break; + case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST: + { + // CPM interrupts + cyg_uint32 cisr; + + HAL_READ_UINT32 (CYGARC_REG_IMM_CISR, cisr); + cisr |= (((cyg_uint32) 0x80000000) + >> (vector - CYGNUM_HAL_INTERRUPT_CPM_FIRST)); + HAL_WRITE_UINT32 (CYGARC_REG_IMM_CISR, cisr); + break; + } + default: + CYG_FAIL("Unknown Interrupt!!!"); + break; + } +} + +static __inline__ void +cyg_hal_interrupt_configure ( cyg_uint32 vector, + cyg_bool level, + cyg_bool up ) +{ + switch (vector) { + case CYGNUM_HAL_INTERRUPT_SIU_IRQ0: + case CYGNUM_HAL_INTERRUPT_SIU_IRQ1: + case CYGNUM_HAL_INTERRUPT_SIU_IRQ2: + case CYGNUM_HAL_INTERRUPT_SIU_IRQ3: + case CYGNUM_HAL_INTERRUPT_SIU_IRQ4: + case CYGNUM_HAL_INTERRUPT_SIU_IRQ5: + case CYGNUM_HAL_INTERRUPT_SIU_IRQ6: + case CYGNUM_HAL_INTERRUPT_SIU_IRQ7: + { + // External interrupts + cyg_uint32 siel, bit; + + CYG_ASSERT( level || !up, "Only falling edge is supported"); + + bit = (((cyg_uint32) CYGARC_REG_IMM_SIEL_IRQ0) + >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0)); + + HAL_READ_UINT32 (CYGARC_REG_IMM_SIEL, siel); + siel &= ~bit; + if (!level) { + // Set edge detect bit. + siel |= bit; + } + HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIEL, siel); + break; + } + case CYGNUM_HAL_INTERRUPT_SIU_LVL0: + case CYGNUM_HAL_INTERRUPT_SIU_LVL1: + case CYGNUM_HAL_INTERRUPT_SIU_LVL2: + case CYGNUM_HAL_INTERRUPT_SIU_LVL3: + case CYGNUM_HAL_INTERRUPT_SIU_LVL4: + case CYGNUM_HAL_INTERRUPT_SIU_LVL5: + case CYGNUM_HAL_INTERRUPT_SIU_LVL6: + case CYGNUM_HAL_INTERRUPT_SIU_LVL7: + case CYGNUM_HAL_INTERRUPT_SIU_TB_A: + case CYGNUM_HAL_INTERRUPT_SIU_TB_B: + case CYGNUM_HAL_INTERRUPT_SIU_PIT: + case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC: + case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR: + // PCMCIA_A_IRQ + // PCMCIA_A_CHLVL + // PCMCIA_B_IRQ + // PCMCIA_B_CHLVL + case CYGNUM_HAL_INTERRUPT_SIU_CPM: + case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST: + // These cannot be configured. + break; + + default: + CYG_FAIL("Unknown Interrupt!!!"); + break; + } +} + +static __inline__ void +cyg_hal_interrupt_set_level ( cyg_uint32 vector, cyg_uint32 level ) +{ + // Note: highest priority has the lowest numerical value. + CYG_ASSERT( level >= CYGARC_SIU_PRIORITY_HIGH, "Invalid priority"); + CYG_ASSERT( level <= CYGARC_SIU_PRIORITY_LOW, "Invalid priority"); + + switch (vector) { + case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7: + // These cannot be configured. + break; + case CYGNUM_HAL_INTERRUPT_SIU_TB_A: + case CYGNUM_HAL_INTERRUPT_SIU_TB_B: + { + // TimeBase A+B interrupt + cyg_uint16 tbscr; + + HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); + tbscr &= ~(CYGARC_REG_IMM_TBSCR_IRQMASK); + tbscr |= CYGARC_REG_IMM_TBSCR_IRQ0 >> level; + HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); + break; + } + case CYGNUM_HAL_INTERRUPT_SIU_PIT: + { + // Periodic Interrupt + cyg_uint16 piscr; + + HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); + piscr &= ~(CYGARC_REG_IMM_PISCR_IRQMASK); + piscr |= CYGARC_REG_IMM_PISCR_IRQ0 >> level; + HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr); + break; + } + case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC: + case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR: + { + // Real Time Clock Second & Real Time Clock Alarm + cyg_uint16 rtcsc; + + HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); + rtcsc &= ~(CYGARC_REG_IMM_RTCSC_IRQMASK); + rtcsc |= CYGARC_REG_IMM_RTCSC_IRQ0 >> level; + HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); + break; + } + // PCMCIA_A_IRQ + // PCMCIA_A_CHLVL + // PCMCIA_B_IRQ + // PCMCIA_B_CHLVL + case CYGNUM_HAL_INTERRUPT_SIU_CPM: + { + // Communications Processor Module + cyg_uint32 cicr; + + HAL_READ_UINT32 (CYGARC_REG_IMM_CICR, cicr); + cicr &= ~(CYGARC_REG_IMM_CICR_IRQMASK); + cicr |= level << CYGARC_REG_IMM_CICR_IRQ_SHIFT; + HAL_WRITE_UINT32 (CYGARC_REG_IMM_CICR, cicr); + break; + } + case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST: + // CPM interrupt levels are for internal priority. All interrupts + // fed to the CPU use the CPM level set above. + // FIXME: Control of SCdP ordering. + break; + default: + CYG_FAIL("Unknown Interrupt!!!"); + break; + } +} + +// The decrementer interrupt cannnot be masked, configured or acknowledged. + +#define HAL_INTERRUPT_MASK( _vector_ ) \ + CYG_MACRO_START \ + if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ + cyg_hal_interrupt_mask ( (_vector_) ); \ + CYG_MACRO_END + +#define HAL_INTERRUPT_UNMASK( _vector_ ) \ + CYG_MACRO_START \ + if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ + cyg_hal_interrupt_unmask ( (_vector_) ); \ + CYG_MACRO_END + +#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ + CYG_MACRO_START \ + if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ + cyg_hal_interrupt_acknowledge ( (_vector_) ); \ + CYG_MACRO_END + +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \ + CYG_MACRO_START \ + if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ + cyg_hal_interrupt_configure ( (_vector_), (_level_), (_up_) ); \ + CYG_MACRO_END + +#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \ + CYG_MACRO_START \ + if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ + cyg_hal_interrupt_set_level ( (_vector_) , (_level_) ); \ + CYG_MACRO_END + +#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED + +#endif + +//-------------------------------------------------------------------------- +// Interrupt arbiters + +#ifdef CYGPKG_HAL_POWERPC_MPC860 + +externC cyg_uint32 hal_arbitration_isr_tb (CYG_ADDRWORD vector, + CYG_ADDRWORD data); +externC cyg_uint32 hal_arbitration_isr_pit (CYG_ADDRWORD vector, + CYG_ADDRWORD data); +externC cyg_uint32 hal_arbitration_isr_rtc (CYG_ADDRWORD vector, + CYG_ADDRWORD data); +externC cyg_uint32 hal_arbitration_isr_cpm (CYG_ADDRWORD vector, + CYG_ADDRWORD data); + +#endif // ifdef CYGPKG_HAL_POWERPC_MPC860 + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_VAR_INTR_H +// End of var_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8xx/current/include/var_regs.h @@ -0,0 +1,341 @@ +#ifndef CYGONCE_HAL_VAR_REGS_H +#define CYGONCE_HAL_VAR_REGS_H + +//========================================================================== +// +// var_regs.h +// +// PowerPC 8xx variant CPU definitions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 2000-02-04 +// Purpose: Provide MPC8xx register definitions +// Description: Provide MPC8xx register definitions +// The short difinitions (sans CYGARC_REG_) are exported only +// if CYGARC_HAL_COMMON_EXPORT_CPU_MACROS is defined. +// Usage: Included via the acrhitecture register header: +// #include <cyg/hal/ppc_regs.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +//-------------------------------------------------------------------------- +// Instruction cache control. +#define CYGARC_REG_IC_CST 560 +#define CYGARC_REG_IC_ADR 561 +#define CYGARC_REG_IC_DAT 562 + +#define CYGARC_REG_IC_CMD_CE 0x02000000 // cache enable +#define CYGARC_REG_IC_CMD_CD 0x04000000 // cache disable +#define CYGARC_REG_IC_CMD_LL 0x06000000 // load & lock +#define CYGARC_REG_IC_CMD_UL 0x08000000 // unlock line +#define CYGARC_REG_IC_CMD_UA 0x0a000000 // unlock all +#define CYGARC_REG_IC_CMD_IA 0x0c000000 // invalidate all + +#define CYGARC_REG_IC_ADR_SETID_SHIFT 4 // set id is bits 21-27 +#define CYGARC_REG_IC_ADR_WAY0 0x00000000 // select way0 +#define CYGARC_REG_IC_ADR_WAY1 0x00001000 // select way1 + +#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#define IC_CST CYGARC_REG_IC_CST +#define IC_ADR CYGARC_REG_IC_ADR +#define IC_DAT CYGARC_REG_IC_DAT + +#define IC_CMD_CE CYGARC_REG_IC_CMD_CE +#define IC_CMD_CD CYGARC_REG_IC_CMD_CD +#define IC_CMD_LL CYGARC_REG_IC_CMD_LL +#define IC_CMD_UL CYGARC_REG_IC_CMD_UL +#define IC_CMD_UA CYGARC_REG_IC_CMD_UA +#define IC_CMD_IA CYGARC_REG_IC_CMD_IA + +#define IC_ADR_SETID_SHIFT CYGARC_REG_IC_ADR_SETID_SHIFT +#define IC_ADR_WAY0 CYGARC_REG_IC_ADR_WAY0 +#define IC_ADR_WAY1 CYGARC_REG_IC_ADR_WAY1 +#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +//-------------------------------------------------------------------------- +// Data cache control. +#define CYGARC_REG_DC_CST 568 +#define CYGARC_REG_DC_ADR 569 +#define CYGARC_REG_DC_DAT 570 + +#define CYGARC_REG_DC_CMD_CE 0x02000000 // cache enable +#define CYGARC_REG_DC_CMD_CD 0x04000000 // cache disable +#define CYGARC_REG_DC_CMD_LL 0x06000000 // lock line +#define CYGARC_REG_DC_CMD_UL 0x08000000 // unlock line +#define CYGARC_REG_DC_CMD_UA 0x0a000000 // unlock all +#define CYGARC_REG_DC_CMD_IA 0x0c000000 // invalidate all +#define CYGARC_REG_DC_CMD_FL 0x0e000000 // flush line +#define CYGARC_REG_DC_CMD_SW 0x01000000 // set writethrough +#define CYGARC_REG_DC_CMD_CW 0x03000000 // clear writethrough +#define CYGARC_REG_DC_CMD_SS 0x05000000 // set little endian swap +#define CYGARC_REG_DC_CMD_CS 0x07000000 // clear little endian swap + +#define CYGARC_REG_DC_ADR_SETID_SHIFT 4 // set id is bits 21-27 +#define CYGARC_REG_DC_ADR_WAY0 0x00000000 // select way0 +#define CYGARC_REG_DC_ADR_WAY1 0x00001000 // select way1 + +#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#define DC_CST CYGARC_REG_DC_CST +#define DC_ADR CYGARC_REG_DC_ADR +#define DC_DAT CYGARC_REG_DC_DAT + +#define DC_CMD_CE CYGARC_REG_DC_CMD_CE +#define DC_CMD_CD CYGARC_REG_DC_CMD_CD +#define DC_CMD_LL CYGARC_REG_DC_CMD_LL +#define DC_CMD_UL CYGARC_REG_DC_CMD_UL +#define DC_CMD_UA CYGARC_REG_DC_CMD_UA +#define DC_CMD_IA CYGARC_REG_DC_CMD_IA +#define DC_CMD_FL CYGARC_REG_DC_CMD_FL +#define DC_CMD_SW CYGARC_REG_DC_CMD_SW +#define DC_CMD_CW CYGARC_REG_DC_CMD_CW +#define DC_CMD_SS CYGARC_REG_DC_CMD_SS +#define DC_CMD_CS CYGARC_REG_DC_CMD_CS + +#define DC_ADR_SETID_SHIFT CYGARC_REG_DC_ADR_SETID_SHIFT +#define DC_ADR_WAY0 CYGARC_REG_DC_ADR_WAY0 +#define DC_ADR_WAY1 CYGARC_REG_DC_ADR_WAY1 +#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +//-------------------------------------------------------------------------- +// MMU control. +#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#define M_CASID 793 // current address space id register + +#define MI_CTR 784 // instruction MMU control +#define MI_EPN 787 // instruction MMU effective page num +#define MI_TWC 789 // instruction MMU tablewalk count +#define MI_RPN 790 // instruction MMU real page num +#define MI_DCAM 816 // instruction MMU CAM read +#define MI_DRAM0 817 // instruction MMU RAM read 0 +#define MI_DRAM1 818 // instruction MMU RAM read 1 + +#define MI_EPN_EPNMASK 0xfffff000 // effective page no mask +#define MI_EPN_EV 0x00000200 // entry valid + +#define MI_RPN_RPNMASK 0xfffff000 // real page no mask +#define MI_RPN_PPRWRW 0x000008f0 // page protection (rw/rw, page valid) +#define MI_RPN_LPS 0x00000008 // large page size +#define MI_RPN_SH 0x00000004 // shared page (1 = no ASID cmp) +#define MI_RPN_CI 0x00000002 // cache inhibited +#define MI_RPN_V 0x00000001 // entry valid + +#define MI_TWC_PS8MB 0x0000000c // page size = 8MB +#define MI_TWC_G 0x00000010 // guarded +#define MI_TWC_WT 0x00000002 // writethrough +#define MI_TWC_V 0x00000001 // entry valid + +#define MI_CTR_INDX_SHIFT 8 // the ITLB_INDX starts at bit 23 + +#define MD_CTR 792 // data MMU control +#define MD_EPN 795 // data MMU effective page num +#define MD_TWC 797 // data MMU tablewalk count +#define MD_RPN 798 // data MMU real page num +#define MD_DCAM 824 // data MMU CAM read +#define MD_DRAM0 825 // data MMU RAM read 0 +#define MD_DRAM1 826 // data MMU RAM read 1 + +#define MD_RPN_CHANGED 0x00000100 // page changed +#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +//-------------------------------------------------------------------------- +// Internal Memory Map. +#define CYGARC_REG_IMMR 638 // internal memory map base register +#define CYGARC_REG_IMMR_BASEMASK 0xffff0000 // imm base location mask (rw) +#define CYGARC_REG_IMMR_PARTNUM 0x0000ff00 // part number mask (ro) +#define CYGARC_REG_IMMR_MASKNUM 0x000000ff // mask number mask (ro) + +#define CYGARC_REG_IMM_BASE 0xff000000 // the internal memory map base + +// system protection control +#define CYGARC_REG_IMM_SYPCR (CYGARC_REG_IMM_BASE + 0x004) +#define CYGARC_REG_IMM_SYPCR_SWTC_MASK 0xffff0000 +#define CYGARC_REG_IMM_SYPCR_BMT_MASK 0x0000ff00 +#define CYGARC_REG_IMM_SYPCR_BME 0x00000080 +#define CYGARC_REG_IMM_SYPCR_SWF 0x00000008 +#define CYGARC_REG_IMM_SYPCR_SWE 0x00000004 +#define CYGARC_REG_IMM_SYPCR_SWRI 0x00000002 +#define CYGARC_REG_IMM_SYPCR_SWP 0x00000001 + +// interrupt pend register +#define CYGARC_REG_IMM_SIPEND (CYGARC_REG_IMM_BASE + 0x010) +#define CYGARC_REG_IMM_SIPEND_IRQ0 0x80000000 // irq0 is bit 0... + +// interrupt mask +#define CYGARC_REG_IMM_SIMASK (CYGARC_REG_IMM_BASE + 0x014) +#define CYGARC_REG_IMM_SIMASK_IRQ0 0x80000000 // ... irq n is bit n*2 + +// interrupt edge level mask +#define CYGARC_REG_IMM_SIEL (CYGARC_REG_IMM_BASE + 0x018) +#define CYGARC_REG_IMM_SIEL_IRQ0 0x80000000 + +// interrupt vector +#define CYGARC_REG_IMM_SIVEC (CYGARC_REG_IMM_BASE + 0x01c) + +// memory controller +#define CYGARC_REG_IMM_BR0 (CYGARC_REG_IMM_BASE + 0x100) +#define CYGARC_REG_IMM_OR0 (CYGARC_REG_IMM_BASE + 0x104) +#define CYGARC_REG_IMM_BR1 (CYGARC_REG_IMM_BASE + 0x108) +#define CYGARC_REG_IMM_OR1 (CYGARC_REG_IMM_BASE + 0x10c) +#define CYGARC_REG_IMM_BR2 (CYGARC_REG_IMM_BASE + 0x110) +#define CYGARC_REG_IMM_OR2 (CYGARC_REG_IMM_BASE + 0x114) +#define CYGARC_REG_IMM_BR3 (CYGARC_REG_IMM_BASE + 0x118) +#define CYGARC_REG_IMM_OR3 (CYGARC_REG_IMM_BASE + 0x11c) +#define CYGARC_REG_IMM_BR4 (CYGARC_REG_IMM_BASE + 0x120) +#define CYGARC_REG_IMM_OR4 (CYGARC_REG_IMM_BASE + 0x124) +#define CYGARC_REG_IMM_BR5 (CYGARC_REG_IMM_BASE + 0x128) +#define CYGARC_REG_IMM_OR5 (CYGARC_REG_IMM_BASE + 0x12c) +#define CYGARC_REG_IMM_BR6 (CYGARC_REG_IMM_BASE + 0x130) +#define CYGARC_REG_IMM_OR6 (CYGARC_REG_IMM_BASE + 0x134) +#define CYGARC_REG_IMM_BR7 (CYGARC_REG_IMM_BASE + 0x138) +#define CYGARC_REG_IMM_OR7 (CYGARC_REG_IMM_BASE + 0x13c) + +#define CYGARC_REG_IMM_BR_BA_MASK 0xffff8000 // base address +#define CYGARC_REG_IMM_BR_AT_MASK 0x00007000 // address type +#define CYGARC_REG_IMM_BR_PS_8 0x00000400 // port size 8 bits +#define CYGARC_REG_IMM_BR_PS_16 0x00000800 // port size 16 bits +#define CYGARC_REG_IMM_BR_PS_32 0x00000000 // port size 32 bits +#define CYGARC_REG_IMM_BR_PARE 0x00000200 // parity enable +#define CYGARC_REG_IMM_BR_WP 0x00000100 // write protect +#define CYGARC_REG_IMM_BR_MS_GPCM 0x00000000 // machine select G.P.C.M +#define CYGARC_REG_IMM_BR_MS_UPMA 0x00000080 // machine select U.P.M.A +#define CYGARC_REG_IMM_BR_MS_UPMB 0x000000c0 // machine select U.P.M.B +#define CYGARC_REG_IMM_BR_V 0x00000001 // valid bit + +#define CYGARC_REG_IMM_OR_AM 0xffff8000 // address mask +#define CYGARC_REG_IMM_OR_ATM 0x00007000 // address type mask +#define CYGARC_REG_IMM_OR_CSNT 0x00000800 // GPCM:chip select negation time +#define CYGARC_REG_IMM_OR_SAM 0x00000800 // UPMx:start address multiplex +#define CYGARC_REG_IMM_OR_ACS_0 0x00000000 // GPCM:CS output immediately +#define CYGARC_REG_IMM_OR_ACS_4 0x00000400 // GPCM:CS output 1/4 clock later +#define CYGARC_REG_IMM_OR_ACS_2 0x00000600 // GPCM:CS output 1/2 clock later +#define CYGARC_REG_IMM_OR_G5LA 0x00000400 // UPMx:general-purpose line 5 A +#define CYGARC_REG_IMM_OR_G5LS 0x00000200 // UPMx:general-purpose line 5 S +#define CYGARC_REG_IMM_OR_BI 0x00000100 // burst inhibit +#define CYGARC_REG_IMM_OR_SCY_MASK 0x000000f0 // cycle length in clocks +#define CYGARC_REG_IMM_OR_SCY_SHIFT 4 +#define CYGARC_REG_IMM_OR_SETA 0x00000008 // external transfer ack +#define CYGARC_REG_IMM_OR_TRLX 0x00000004 // timing relaxed +#define CYGARC_REG_IMM_OR_EHTR 0x00000002 // extended hold time on read + +// timebase status and control +#define CYGARC_REG_IMM_TBSCR (CYGARC_REG_IMM_BASE + 0x200) +#define CYGARC_REG_IMM_TBSCR_REFA 0x0080 // reference interrupt status A +#define CYGARC_REG_IMM_TBSCR_REFB 0x0040 // reference interrupt status B +#define CYGARC_REG_IMM_TBSCR_REFAE 0x0008 // reference interrupt enable A +#define CYGARC_REG_IMM_TBSCR_REFBE 0x0004 // reference interrupt enable B +#define CYGARC_REG_IMM_TBSCR_TBF 0x0002 // timebase freeze +#define CYGARC_REG_IMM_TBSCR_TBE 0x0001 // timebase enable +#define CYGARC_REG_IMM_TBSCR_IRQ0 0x8000 // highest interrupt level +#define CYGARC_REG_IMM_TBSCR_IRQMASK 0xff00 // irq priority mask + +// timebase reference register 0 +#define CYGARC_REG_IMM_TBREF0 (CYGARC_REG_IMM_BASE + 0x204) +// timebase reference register 1 +#define CYGARC_REG_IMM_TBREF1 (CYGARC_REG_IMM_BASE + 0x208) + +// real time clock +#define CYGARC_REG_IMM_RTCSC (CYGARC_REG_IMM_BASE + 0x220) +#define CYGARC_REG_IMM_RTCSC_SEC 0x0080 // once per second interrupt +#define CYGARC_REG_IMM_RTCSC_ALR 0x0040 // alarm interrupt +#define CYGARC_REG_IMM_RTCSC_38K 0x0010 // source select +#define CYGARC_REG_IMM_RTCSC_SIE 0x0008 // second interrupt enable +#define CYGARC_REG_IMM_RTCSC_ALE 0x0004 // alarm interrupt enable +#define CYGARC_REG_IMM_RTCSC_RTF 0x0002 // real time clock freeze +#define CYGARC_REG_IMM_RTCSC_RTE 0x0001 // real time clock enable +#define CYGARC_REG_IMM_RTCSC_IRQ0 0x8000 // highest interrupt level +#define CYGARC_REG_IMM_RTCSC_IRQMASK 0xff00 // irq priority mask + +// periodic interrupt status & ctrl +#define CYGARC_REG_IMM_PISCR (CYGARC_REG_IMM_BASE + 0x240) +#define CYGARC_REG_IMM_PISCR_PS 0x0080 // periodic interrupt status +#define CYGARC_REG_IMM_PISCR_PIE 0x0004 // periodic interrupt enable +#define CYGARC_REG_IMM_PISCR_PITF 0x0002 // periodic interrupt timer freeze +#define CYGARC_REG_IMM_PISCR_PTE 0x0001 // periodic timer enable +#define CYGARC_REG_IMM_PISCR_IRQ0 0x8000 // highest interrupt level +#define CYGARC_REG_IMM_PISCR_IRQMASK 0xff00 // irq priority mask + +// periodic interrupt timer count +#define CYGARC_REG_IMM_PITC (CYGARC_REG_IMM_BASE + 0x244) +#define CYGARC_REG_IMM_PITC_COUNT_SHIFT 16 // count is stored in bits 0-15 + +// system clock control +#define CYGARC_REG_IMM_SCCR (CYGARC_REG_IMM_BASE + 0x280) +#define CYGARC_REG_IMM_SCCR_TBS 0x02000000 // timebase source +#define CYGARC_REG_IMM_SCCR_RTDIV 0x01000000 // rtc clock divide +#define CYGARC_REG_IMM_SCCR_RTSEL 0x00800000 // rtc clock select + +// CPM interrupt vector register +#define CYGARC_REG_IMM_CIVR (CYGARC_REG_IMM_BASE + 0x930) +#define CYGARC_REG_IMM_CIVR_IACK 0x0001 // set this to update register +#define CYGARC_REG_IMM_CIVR_VECTOR_SHIFT 11 // vector is at bits 0-4 + +// CPM interrupt configuration reg +#define CYGARC_REG_IMM_CICR (CYGARC_REG_IMM_BASE + 0x940) +#define CYGARC_REG_IMM_CICR_IEN 0x00000080 // interrupt enable +#define CYGARC_REG_IMM_CICR_IRQMASK 0x0000e000 // irq priority mask +#define CYGARC_REG_IMM_CICR_IRQ_SHIFT 13 + +// CPM interrupt mask register +#define CYGARC_REG_IMM_CIMR (CYGARC_REG_IMM_BASE + 0x948) +// CPM interrupt in-service register +#define CYGARC_REG_IMM_CISR (CYGARC_REG_IMM_BASE + 0x94C) + + +#define CYGARC_SIU_PRIORITY_LOW 7 // the lowest irq priority +#define CYGARC_SIU_PRIORITY_HIGH 0 // the highest irq priority + +#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +//----------------------------------------------------------------------------- +// Development Support. +#define CYGARC_REG_DER 149 + +#define CYGARC_REG_ICTRL 158 // instruction support control reg +#define CYGARC_REG_ICTRL_SERSHOW 0x00000000 // serialized, show cycles +#define CYGARC_REG_ICTRL_NOSERSHOW 0x00000007 //non-serialized&no show cycles + +#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#define DER CYGARC_REG_DER + +#define ICTRL CYGARC_REG_ICTRL +#define ICTRL_SERSHOW CYGARC_REG_ICTRL_SERSHOW +#define ICTRL_NOSERSHOW CYGARC_REG_ICTRL_NOSERSHOW +#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +//----------------------------------------------------------------------------- +#endif // ifdef CYGONCE_HAL_VAR_REGS_H +// End of var_regs.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8xx/current/include/variant.inc @@ -0,0 +1,230 @@ +#ifndef CYGONCE_HAL_VARIANT_INC +#define CYGONCE_HAL_VARIANT_INC +##============================================================================= +## +## variant.inc +## +## MPC8xx family assembler header file +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): jskov +## Contributors:jskov +## Date: 2000-02-04 +## Purpose: MPC8xx family definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the MPC8xx CPU family. +## Usage: +## #include <cyg/hal/variant.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/ppc.inc> + +##----------------------------------------------------------------------------- +## MPC8xx defined vectors + + .macro hal_extra_vectors + # MPC8xx vectors + exception_vector software_emu + exception_vector instruction_tlb_miss + exception_vector data_tlb_miss + exception_vector instruction_tlb_error + exception_vector data_tlb_error + exception_vector reserved_01500 + exception_vector reserved_01600 + exception_vector reserved_01700 + exception_vector reserved_01800 + exception_vector reserved_01900 + exception_vector reserved_01A00 + exception_vector reserved_01B00 + exception_vector data_breakpoint + exception_vector instruction_breakpoint + exception_vector peripheral_breakpoint + exception_vector NMI_port + .endm + +##----------------------------------------------------------------------------- +## MPC8xx CPU initialization +## +## Initialize CPU to a post-reset state, ensuring the ground doesn''t +## shift under us while we try to set things up. + + .macro hal_cpu_init + # Disable special MPC8xx "development support" which + # suppresses trace exceptions. The CPU seems to hang, not + # executing from offset 0x1e00(?) as expected. + lwi r3,0x00000007 + mtspr ICTRL,r3 + li r3,0 + mtspr DER, r3 + + # Disable caches + lwi r3,CYGARC_REG_DC_CMD_CD + sync + mtspr CYGARC_REG_DC_CST,r3 + lwi r3,CYGARC_REG_IC_CMD_CD + isync + mtspr CYGARC_REG_IC_CST,r3 + isync + + # Set up MSR (disable MMU for now) + lwi r3,(CYG_MSR & ~(MSR_IR | MSR_DR)) + sync + mtmsr r3 + sync + .endm + +##----------------------------------------------------------------------------- +## MPC8xx monitor initialization + +# FIXME: Need to generate these C/asm shared variables automatically +#define CYGNUM_HAL_VECTOR_INTERRUPT 5 +#define CYGNUM_HAL_VECTOR_DECREMENTER 9 +#define CYGNUM_HAL_VECTOR_NMI 31 +#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_NMI +#define CYGNUM_HAL_VSR_COUNT ( CYGNUM_HAL_VSR_MAX + 1 ) + + +#ifndef CYGPKG_HAL_PPC_MON_DEFINED + +#if defined(CYG_HAL_STARTUP_ROM) || \ + ( defined(CYG_HAL_STARTUP_RAM) && \ + !defined(CYGSEM_HAL_USE_ROM_MONITOR)) + + # If we are starting up from ROM, or we are starting in + # RAM and NOT using a ROM monitor, copy exception handler + # code to 0 and initialize the VSR table. + + .macro hal_mon_init + # First copy exception vectors to RAM + lwi r3,rom_vectors # r3 = rom start + lwi r4,0 # r4 = ram start + lwi r5,rom_vectors_end # r5 = rom end + cmplw r3,r5 # skip if no vectors + beq 2f + + subi r3,r3,4 + subi r4,r4,4 + subi r5,r5,4 +1: + lwzu r0,4(r3) # get word from ROM + stwu r0,4(r4) # store in RAM + cmplw r3,r5 # compare + blt 1b # loop if not yet done +2: + + # Initialize VSR table + # First fill with exception handlers + lwi r3,cyg_hal_default_exception_vsr + lwi r4,hal_vsr_table + subi r4,r4,4 + li r5,CYGNUM_HAL_VSR_COUNT +1: stwu r3,4(r4) + subi r5,r5,1 + cmpwi r5,0 + bne 1b + + # Then fill in the special vectors + lwi r3,cyg_hal_default_interrupt_vsr + lwi r4,hal_vsr_table + stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4) + stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4) + .endm + +#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR) + + # Initialize the VSR table entries + # We only take control of the interrupt vectors, + # the rest are left to the ROM for now... + + .macro hal_mon_init + lwi r3,cyg_hal_default_interrupt_vsr + lwi r4,hal_vsr_table + stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4) + stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4) + .endm + + +#else + + .macro hal_mon_init + + .endm + +#endif + + +#define CYGPKG_HAL_PPC_MON_DEFINED + +#endif // CYGPKG_HAL_PPC_MON_DEFINED + + + + +##----------------------------------------------------------------------------- +## Indicate that the ISR tables are defined in variant.S + +## Note: CYG_ISR_TABLE_SIZE must match CYG_ISR_COUNT defined in hal_intr.h. +#define CYG_ISR_TABLE_SIZE 59 + +#define CYG_HAL_MIPS_ISR_TABLES_DEFINED + +##----------------------------------------------------------------------------- +## MPC8xx interrupt handling. + +#ifndef CYGPKG_HAL_POWERPC_INTC_DEFINED + +## First level decoding of MPC8xx SIU interrupt controller. + + # decode the interrupt + .macro hal_intc_decode dreg,state + lwz \dreg,ppcreg_vector(\state) # retrieve vector number, + rlwinm. \dreg,\dreg,22,31,31 # isolate bit 21 + beq 0f # done if decrementer (vec 0) + lwi \dreg,CYGARC_REG_IMM_SIVEC # if external, get SIU + lbz \dreg,0(\dreg) # vector. + srwi \dreg,\dreg,2 + addi \dreg,\dreg,1 # Skip decrementer vector +0: stw \dreg,ppcreg_vector(\state) # update vector in state frame. + slwi \dreg,\dreg,2 # convert to byte offset. + .endm + + +#define CYGPKG_HAL_POWERPC_INTC_DEFINED +#endif // CYGPKG_HAL_POWERPC_INTC_DEFINED + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_VARIANT_INC +# end of variant.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8xx/current/src/PKGconf.mak @@ -0,0 +1,45 @@ +#============================================================================== +# +# makefile +# +# hal/powerpc/mpc8xx/src +# +#============================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +#============================================================================== + +PACKAGE := hal_powerpc_mpc8xx +include ../../../../../pkgconf/pkgconf.mak + +LIBRARY := libtarget.a +COMPILE := var_intr.c var_misc.c variant.S +OTHER_OBJS := +OTHER_TARGETS := +OTHER_CLEAN := +OTHER_DEPS := + +include $(COMPONENT_REPOSITORY)/pkgconf/makrules.src + +EXTRAS = $(wildcard $(PREFIX)/lib/libextras.a)
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8xx/current/src/var_intr.c @@ -0,0 +1,241 @@ +//========================================================================== +// +// var_intr.c +// +// PowerPC variant interrupt handlers +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 2000-02-11 +// Purpose: PowerPC variant interrupt handlers +// Description: This file contains code to handle interrupt related issues +// on the PowerPC variant. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <cyg/hal/ppc_regs.h> + +#include <cyg/hal/hal_intr.h> // hal_interrupt_x tables + +// These are the Cyg_Interrupt::HANDLED/CALL_DSR values. +#define Cyg_InterruptHANDLED 1 +#define Cyg_InterruptCALL_DSR 2 + + +typedef cyg_uint32 cyg_ISR(cyg_uint32 vector, CYG_ADDRWORD data); + +extern void cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj ); + +static inline cyg_uint32 +hal_call_isr (cyg_uint32 vector) +{ + cyg_ISR *isr; + CYG_ADDRWORD data; + cyg_uint32 isr_ret; + + isr = (cyg_ISR*) hal_interrupt_handlers[vector]; + data = hal_interrupt_data[vector]; + + isr_ret = (*isr) (vector, data); + +#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT + if (isr_ret & Cyg_InterruptCALL_DSR) { + cyg_interrupt_post_dsr (hal_interrupt_objects[vector]); + } +#endif + + return isr_ret & ~Cyg_InterruptCALL_DSR; +} + +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#ifdef CYGPKG_HAL_POWERPC_MPC860 + +// Since the interrupt sources do not have fixed vectors on the 860 +// SIU, some arbitration is required. + +// More than one interrupt source can be programmed to use the same +// vector, so all sources on the same vector have to be queried to +// find the one raising the interrupt. This functionality has not been +// implemented, but the arbiter functions for each of the SIU +// interrupt sources can be called in sequence without change. + + + +// Timebase interrupt can be caused by match on either reference A +// or B. +// Note: If only one interrupt source is assigned per vector, and only +// reference interrupt A or B is used, this ISR is not +// necessary. Attach the timerbase reference A or B ISR directly to +// the LVLx vector instead. +externC cyg_uint32 +hal_arbitration_isr_tb (CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + cyg_uint32 isr_ret; + cyg_uint16 tbscr; + + HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); + if (tbscr & CYGARC_REG_IMM_TBSCR_REFA) { + isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_TB_A); + + CYG_ASSERT (isr_ret & Cyg_InterruptHANDLED, + "Interrupt not handled"); + +#ifndef CYGSEM_HAL_COMMON_INTERRUPTS_CHECK_ALL_SOURCES + return isr_ret; +#endif + } + + if (tbscr & CYGARC_REG_IMM_TBSCR_REFB) { + isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_TB_B); + + CYG_ASSERT (isr_ret & Cyg_InterruptHANDLED, + "Interrupt not handled"); + +#ifndef CYGSEM_HAL_COMMON_INTERRUPTS_CHECK_ALL_SOURCES + return isr_ret; +#endif + } + + return 0; +} + +// Periodic interrupt. +// Note: If only one interrupt source is assigned per vector, this ISR +// is not necessary. Attach the periodic interrupt ISR directly to the +// LVLx vector instead. +externC cyg_uint32 +hal_arbitration_isr_pit (CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + cyg_uint32 isr_ret; + cyg_uint16 piscr; + + HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); + if (piscr & CYGARC_REG_IMM_PISCR_PS) { + isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_PIT); + + CYG_ASSERT (isr_ret & Cyg_InterruptHANDLED, + "Interrupt not handled"); + +#ifndef CYGSEM_HAL_COMMON_INTERRUPTS_CHECK_ALL_SOURCES + return isr_ret; +#endif + } + + return 0; +} + +// Real time clock interrupts can be caused by the alarm or +// once-per-second. +// Note: If only one interrupt source is assigned per vector, and only +// the alarm or once-per-second interrupt is used, this ISR is not +// necessary. Attach the alarm or once-per-second ISR directly to the +// LVLx vector instead. +externC cyg_uint32 +hal_arbitration_isr_rtc (CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + cyg_uint32 isr_ret; + cyg_uint16 rtcsc; + + HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); + if (rtcsc & CYGARC_REG_IMM_RTCSC_SEC) { + isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC); + + CYG_ASSERT (isr_ret & Cyg_InterruptHANDLED, + "Interrupt not handled"); + +#ifndef CYGSEM_HAL_COMMON_INTERRUPTS_CHECK_ALL_SOURCES + return isr_ret; +#endif + } + + if (rtcsc & CYGARC_REG_IMM_RTCSC_ALR) { + isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR); + + CYG_ASSERT (isr_ret & Cyg_InterruptHANDLED, + "Interrupt not handled"); + +#ifndef CYGSEM_HAL_COMMON_INTERRUPTS_CHECK_ALL_SOURCES + return isr_ret; +#endif + } + + return 0; +} + +// Communication Processor Module interrupt can be caused by any of +// the CPM sources. +externC cyg_uint32 +hal_arbitration_isr_cpm (CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + cyg_uint32 isr_ret; + cyg_uint16 civr; + + HAL_WRITE_UINT16 (CYGARC_REG_IMM_CIVR, CYGARC_REG_IMM_CIVR_IACK); + HAL_READ_UINT16 (CYGARC_REG_IMM_CIVR, civr); + civr >>= CYGARC_REG_IMM_CIVR_VECTOR_SHIFT; + if (civr) { + isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_CPM_LAST - civr); + + CYG_ASSERT (isr_ret & Cyg_InterruptHANDLED, + "Interrupt not handled"); + +#ifndef CYGSEM_HAL_COMMON_INTERRUPTS_CHECK_ALL_SOURCES + return isr_ret; +#endif + } + + return 0; +} +#endif // ifdef CYGPKG_HAL_POWERPC_MPC860 + +externC void +hal_variant_IRQ_init(void) +{ +#ifdef CYGHWR_HAL_POWERPC_MPC860_CPM_ENABLE + // Attach first-level CPM arbiter to the configured SIU level and + // enable CPM interrupts. +#define ID_CPM 0xDEAD +#define CYGPRI_SIU_LVL (CYGNUM_HAL_INTERRUPT_SIU_LVL0 \ + +CYGHWR_HAL_POWERPC_MPC860_CPM_LVL*2) + + HAL_INTERRUPT_ATTACH (CYGPRI_SIU_LVL, &hal_arbitration_isr_cpm, ID_CPM, 0); + HAL_INTERRUPT_UNMASK (CYGPRI_SIU_LVL); + HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_CPM, + CYGHWR_HAL_POWERPC_MPC860_CPM_LVL); + HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_CPM); +#endif +} + +// ------------------------------------------------------------------------- +// EOF var_intr.c +
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8xx/current/src/var_misc.c @@ -0,0 +1,50 @@ +//========================================================================== +// +// var_misc.c +// +// HAL implementation miscellaneous functions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 2000-02-04 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +void hal_variant_init(void) +{ +} + +//-------------------------------------------------------------------------- +// End of var_misc.c
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8xx/current/src/variant.S @@ -0,0 +1,84 @@ +##============================================================================= +## +## variant.S +## +## POWERPC MPC8xx variant code +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): jskov +## Contributors:jskov +## Date: 2000-02-04 +## Purpose: PowerPC MPC8xx variant code +## Description: Variant specific code for PowerPC MPC8xx CPUs. +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#include <cyg/hal/variant.inc> + +#--------------------------------------------------------------------------- +# Interrupt vector tables. +# These tables contain the isr, data and object pointers used to deliver +# interrupts to user code. + +#if (CYG_ISR_TABLE_SIZE > 2) + .data +#else + .section ".sdata","aw" +#endif + + .extern hal_default_decrementer_isr + .extern hal_default_isr + + .globl hal_interrupt_handlers +hal_interrupt_handlers: + .long hal_default_decrementer_isr + .rept CYG_ISR_TABLE_SIZE-1 + .long hal_default_isr + .endr + + .globl hal_interrupt_data +hal_interrupt_data: + .rept CYG_ISR_TABLE_SIZE + .long 0 + .endr + + .globl hal_interrupt_objects +hal_interrupt_objects: + .rept CYG_ISR_TABLE_SIZE + .long 0 + .endr + +##----------------------------------------------------------------------------- +## end of variant.S +
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8xx/current/tests/PKGconf.mak @@ -0,0 +1,42 @@ +#============================================================================== +# +# makefile +# +# hal/powerpc/mpc8xx/tests +# +#============================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +#============================================================================== + +PACKAGE := hal_powerpc +include ../../../../../pkgconf/pkgconf.mak +include ../../../../../pkgconf/system.mak + +TESTS := + +TESTS += intr0 + +include $(COMPONENT_REPOSITORY)/pkgconf/makrules.tst +
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8xx/current/tests/intr0.c @@ -0,0 +1,298 @@ +//================================================================= +// +// intr0.c +// +// Interrupt test 0 +// +//================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 1998-12-01 +// Description: Simple test of MPC860 interrupt handling when the +// kernel has not been configured. Uses timer interrupts. +// Options: +//####DESCRIPTIONEND#### + +//#define DEBUG_PRINTFS +#ifdef DEBUG_PRINTFS +extern diag_printf( char *format, ... ); +#endif + +#include <pkgconf/hal.h> + +#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#include <cyg/hal/ppc_regs.h> + +#include <cyg/hal/hal_intr.h> + +#include <cyg/infra/testcase.h> + +#ifdef CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE + +#undef CHECK(b) +#define CHECK(b) CYG_TEST_CHECK(b,#b) + +// Can't rely on Cyg_Interrupt class being defined. +#define Cyg_InterruptHANDLED 1 + +// This is the period between interrupts, measured in decrementer ticks. +// Period must be longer than the time required for setting up all the +// interrupt handlers. +#define PIT_PERIOD 5000 + +#ifdef CYGPKG_HAL_POWERPC_MBX +#define TB_PERIOD (PIT_PERIOD*384) // PTA period is 15.36 uS +#else +#define TB_PERIOD (PIT_PERIOD*32) // assuming 512/16 divisors +#endif + +#define ID_RTC_SEC 12345 +#define ID_RTC_ALR 23451 +#define ID_PIT 34512 +#define ID_TBA 45123 +#define ID_TBB 51234 + +volatile cyg_uint32 count = 0; + +// Time/PERIOD 0 1 2 3 4 5 6 7 8 9 10 +// Interrupt PIT TBA PIT PIT TBB PIT PIT +// pit_count 0 0 0 1 1 2 2 3 3 4 4 +// count 0 0 1 3 4 4 5 40 41 42 + +static cyg_uint32 count_verify_table[] = {1, 4, 5, 41, 42}; +static int pit_count = 0; + +// These are useful for debugging: +static cyg_uint32 count_actual_table[] = { -1, -1, -1, -1, -1}; +static cyg_uint32 tbr_actual_table[] = { -1, -1, -1, -1, -1}; + +// Periodic timer ISR. Should be executing 5 times. +static cyg_uint32 isr_pit(CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + cyg_uint32 verify_value; + + CYG_UNUSED_PARAM(CYG_ADDRWORD, data); + + CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_PIT == vector, "Wrong vector!"); + CYG_ASSERT (ID_PIT == data, "Wrong data!"); + + HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_PIT); + + count++; + + count_actual_table[pit_count] = count; + { + cyg_uint32 tbl; + CYGARC_MFTB (TBL_R, tbl); + tbr_actual_table[pit_count] = tbl; + } + + verify_value = count_verify_table[pit_count++]; + +#ifdef DEBUG_PRINTFS + diag_printf( "ISR_PIT executed %d of 5\n", pit_count ); +#endif + + CYG_ASSERT (count == verify_value, "Count wrong!"); + + // End of test when count is 42. Mask interrupts and print PASS text. + if (42 <= count || 5 == pit_count) { + HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_PIT); + HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_TB_A); + HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_TB_B); + +#ifdef DEBUG_PRINTFS + diag_printf( "INFO: Actual counts: %d %d %d %d %d\n", + count_actual_table[0], + count_actual_table[1], + count_actual_table[2], + count_actual_table[3], + count_actual_table[4] ); + diag_printf( "INFO: Actuals tbrs: %d %d %d %d %d\n", + tbr_actual_table[0], + tbr_actual_table[1], + tbr_actual_table[2], + tbr_actual_table[3], + tbr_actual_table[4] ); +#endif + if (42 == count && 5 == pit_count) + CYG_TEST_PASS_FINISH("Intr 0 OK"); + else + CYG_TEST_FAIL_FINISH("Intr 0 Failed."); + } + + return Cyg_InterruptHANDLED; +} + +// TimeBase A ISR. Should be executing once. +static cyg_uint32 isr_tba(CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + CYG_UNUSED_PARAM(CYG_ADDRWORD, data); + + CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_TB_A == vector, "Wrong vector!"); + CYG_ASSERT (ID_TBA == data, "Wrong data!"); + + HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_TB_A); + + count = count * 3; + +#ifdef DEBUG_PRINTFS + diag_printf( "ISR_TBA executed\n" ); +#endif + + return Cyg_InterruptHANDLED; +} + +// TimeBase B ISR. Should be executing once. +static cyg_uint32 isr_tbb(CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + CYG_UNUSED_PARAM(CYG_ADDRWORD, data); + + CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_TB_B == vector, "Wrong vector!"); + CYG_ASSERT (ID_TBB == data, "Wrong data!"); + + HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_TB_B); + + count = count * 8; + +#ifdef DEBUG_PRINTFS + diag_printf( "ISR_TBB executed\n" ); +#endif + + return Cyg_InterruptHANDLED; +} + +void intr0_main( void ) +{ + CYG_TEST_INIT(); + +#if 0 + // The A.3 revision of the CPU I'm using at the moment generates a + // machine check exception when writing to IMM_RTCSC. Smells a + // bit like the "SIU4. Spurious External Bus Transaction Following + // PLPRCR Write." CPU errata. Have to find out for sure. Run real + // time clock interrupts on level 0 + { + // Still to do. + } +#endif + + // Run periodic timer interrupt on level 1 + { + cyg_uint16 piscr; + + // Attach pit arbiter. + HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_LVL1, + &hal_arbitration_isr_pit, ID_PIT, 0); + HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_LVL1); + + // Attach pit isr. + HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_PIT, &isr_pit, + ID_PIT, 0); + HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_PIT, 1); + HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_PIT); + + + // Set period. + HAL_WRITE_UINT32 (CYGARC_REG_IMM_PITC, + (2*PIT_PERIOD) << CYGARC_REG_IMM_PITC_COUNT_SHIFT); + +#ifdef DEBUG_PRINTFS + diag_printf( "PIT set to %d\n", 2*PIT_PERIOD ); +#endif + // Enable. + HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); + piscr |= CYGARC_REG_IMM_PISCR_PTE; + HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr); + } + + // Run timebase interrupts on level 2 + { + cyg_uint16 tbscr; + cyg_uint32 tbl; + + // Attach tb arbiter. + HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_LVL2, + &hal_arbitration_isr_tb, ID_TBA, 0); + HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_LVL2); + + // Attach tb isrs. + HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_TB_A, &isr_tba, + ID_TBA, 0); + HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_TB_B, &isr_tbb, + ID_TBB, 0); + HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_TB_A, 2); + HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_TB_A); + HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_TB_B); + + // Set reference A & B registers. + CYGARC_MFTB (TBL_R, tbl); + tbl += TB_PERIOD*3; + HAL_WRITE_UINT32 (CYGARC_REG_IMM_TBREF0, tbl); + tbl += TB_PERIOD*4; + HAL_WRITE_UINT32 (CYGARC_REG_IMM_TBREF1, tbl); + +#ifdef DEBUG_PRINTFS + diag_printf( "TB initial %d, !1 %d !2 %d\n", + tbl - 7*TB_PERIOD, + tbl - 4*TB_PERIOD, + tbl - 0*TB_PERIOD ); +#endif + // Enable. + HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); + tbscr |= (CYGARC_REG_IMM_TBSCR_REFA | CYGARC_REG_IMM_TBSCR_REFB | + CYGARC_REG_IMM_TBSCR_TBE); + HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); + tbscr |= CYGARC_REG_IMM_TBSCR_REFAE | CYGARC_REG_IMM_TBSCR_REFBE; + HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); + } + + HAL_ENABLE_INTERRUPTS(); + + for (;;); +} + +externC void +cyg_start( void ) +{ + intr0_main(); +} + +#else // ifdef CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE + +externC void +cyg_start( void ) +{ + CYG_TEST_INIT(); + CYG_TEST_PASS_FINISH("N/A: CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE disabled"); +} + +#endif // ifdef CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE + +// EOF intr0.c
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc60x/current/ChangeLog @@ -0,0 +1,38 @@ +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/PKGconf.mak (COMPILE): + Added var_intr.c + +2000-02-10 Jesper Skov <jskov@redhat.com> + + * include/variant.inc: Renamed default VSR handlers. + +2000-02-07 Jesper Skov <jskov@redhat.com> + + * Created. + +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc60x/current/include/pkgconf/hal_powerpc_ppc60x.h @@ -0,0 +1,87 @@ +#ifndef CYGONCE_PKGCONF_HAL_POWERPC_PPC60X_H +#define CYGONCE_PKGCONF_HAL_POWERPC_PPC60X_H +// ==================================================================== +// +// pkgconf/hal_powerpc_ppc60x.h +// +// HAL configuration file +// +// ==================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 2000-02-04 +// Purpose: To allow the user to edit HAL configuration options. +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +#include <pkgconf/hal_powerpc.h> +#include CYGBLD_HAL_PLATFORM_H + +/* ------------------------------------------------------------------- + * Decide which variant of the PowerPC family we have. + + {{CFG_DATA + + cdl_package CYGPKG_HAL_POWERPC_PPC60X { + display "PowerPC variant" + type radio + parent CYGFUN_HAL_POWERPC_VARIANTS + target powerpc_ppc60x + description " + The PPC60x architecture HAL package provides generic support + for this processor architecture. It is also necessary to + select a specific target platform HAL package." + } + + cdl_option CYGPKG_HAL_POWERPC_PPC603 { + display "PPC603 microprocessor" + parent CYGPKG_HAL_POWERPC_PPC60X + type radio + description " + The PPC603 microprocessor. " + } + + }}CFG_DATA */ + +#define CYGPKG_HAL_POWERPC_PPC603 + +// ------------------------------------------------------------------- +// Characterize the CPU so that the generic architecture part can +// configure itself. + +#undef CYGHWR_HAL_POWERPC_FPU // We have no FPU +#define CYGPKG_HAL_POWERPC_MSBFIRST // Big-endian CPU +#undef CYGSEM_HAL_USE_ROM_MONITOR + +//---------------------------------------------------------------------- +#endif // CYGONCE_PKGCONF_HAL_POWERPC_PPC60X_H +// EOF hal_powerpc_ppc60x.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc60x/current/include/var_cache.h @@ -0,0 +1,184 @@ +#ifndef CYGONCE_VAR_CACHE_H +#define CYGONCE_VAR_CACHE_H +//============================================================================= +// +// var_cache.h +// +// Variant HAL cache control API +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:nickg, jskov +// Date: 2000-04-02 +// Purpose: Variant cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations on the PPC60x variant CPUs. +// Usage: Is included via the architecture cache header: +// #include <cyg/hal/hal_cache.h> +// ... +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/ppc_regs.h> + +#include <cyg/hal/plf_cache.h> + + +//----------------------------------------------------------------------------- +// Cache dimensions + +// Data cache +#define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes +#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line +#define HAL_DCACHE_WAYS 2 // Associativity of the cache + +// Instruction cache +#define HAL_ICACHE_SIZE 4096 // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line +#define HAL_ICACHE_WAYS 2 // Associativity of the cache + +#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() + +// Query the state of the data cache +#define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +//#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_DCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +//#define HAL_DCACHE_STORE( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_DCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() + +// Query the state of the instruction cache +#define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_VAR_CACHE_H +// End of var_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc60x/current/include/var_intr.h @@ -0,0 +1,54 @@ +#ifndef CYGONCE_VAR_INTR_H +#define CYGONCE_VAR_INTR_H +//============================================================================= +// +// var_intr.h +// +// Variant HAL interrupt and clock support +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:nickg, jskov, jlarmour, hmt +// Date: 2000-04-02 +// Purpose: Variant interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock on the PPC60x variant CPUs. +// Usage: Is included via the architecture interrupt header: +// #include <cyg/hal/hal_intr.h> +// ... +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +// No builtin interrupt controller in the PPC60x CPUs. + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_VAR_INTR_H +// End of var_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc60x/current/include/var_regs.h @@ -0,0 +1,100 @@ +#ifndef CYGONCE_HAL_VAR_REGS_H +#define CYGONCE_HAL_VAR_REGS_H + +//========================================================================== +// +// var_regs.h +// +// PowerPC 60x variant CPU definitions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 2000-02-04 +// Purpose: Provide PPC60x register definitions +// Description: Provide PPC60x register definitions +// The short difinitions (sans CYGARC_REG_) are exported only +// if CYGARC_HAL_COMMON_EXPORT_CPU_MACROS is defined. +// Usage: Included via the acrhitecture register header: +// #include <cyg/hal/ppc_regs.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +//-------------------------------------------------------------------------- +// Cache +#define CYGARC_REG_HID0 1008 + +#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#define HID0 CYGARC_REG_HID0 +#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +//-------------------------------------------------------------------------- +// BATs +#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#define IBAT0U 528 +#define IBAT0L 529 +#define IBAT1U 530 +#define IBAT1L 531 +#define IBAT2U 532 +#define IBAT2L 533 +#define IBAT3U 534 +#define IBAT3L 535 + +#define DBAT0U 536 +#define DBAT0L 537 +#define DBAT1U 538 +#define DBAT1L 539 +#define DBAT2U 540 +#define DBAT2L 541 +#define DBAT3U 542 +#define DBAT3L 543 + +#define UBAT_BEPIMASK 0xfffe0000 // effective address mask +#define UBAT_BLMASK 0x00001ffc // block length mask +#define UBAT_VS 0x00000002 // supervisor mode valid bit +#define UBAT_VP 0x00000001 // problem mode valid bit + +#define LBAT_BRPNMASK 0xfffe0000 // real address mask +#define LBAT_W 0x00000040 // write-through +#define LBAT_I 0x00000020 // caching-inhibited +#define LBAT_M 0x00000010 // memory coherence +#define LBAT_G 0x00000008 // guarded + +#define LBAT_PP_NA 0x00000000 // no access +#define LBAT_PP_RO 0x00000001 // read-only +#define LBAT_PP_RW 0x00000002 // read/write +#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +//----------------------------------------------------------------------------- +#endif // ifdef CYGONCE_HAL_VAR_REGS_H +// End of var_regs.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc60x/current/include/variant.inc @@ -0,0 +1,168 @@ +#ifndef CYGONCE_HAL_VARIANT_INC +#define CYGONCE_HAL_VARIANT_INC +##============================================================================= +## +## variant.inc +## +## PPC60x family assembler header file +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): jskov +## Contributors:jskov +## Date: 2000-02-04 +## Purpose: MPC8xx family definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the PPC60x CPU family. +## Usage: +## #include <cyg/hal/variant.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/ppc.inc> + +##----------------------------------------------------------------------------- +## PPC60x defined vectors + + .macro hal_extra_vectors + .endm + +##----------------------------------------------------------------------------- +## PPC60x CPU initialization +## +## Initialize CPU to a post-reset state, ensuring the ground doesn''t +## shift under us while we try to set things up. + + .macro hal_cpu_init + # Set up MSR (disable MMU for now) + lwi r3,(CYG_MSR & ~(MSR_IR | MSR_DR)) + sync + mtmsr r3 + sync + .endm + +##----------------------------------------------------------------------------- +## PPC60x monitor initialization + +# FIXME: Need to generate these C/asm shared variables automatically +#define CYGNUM_HAL_VECTOR_INTERRUPT 5 +#define CYGNUM_HAL_VECTOR_DECREMENTER 9 +#define CYGNUM_HAL_VECTOR_NMI 31 +#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_NMI +#define CYGNUM_HAL_VSR_COUNT ( CYGNUM_HAL_VSR_MAX + 1 ) + + +#ifndef CYGPKG_HAL_PPC_MON_DEFINED + +#if defined(CYG_HAL_STARTUP_ROM) || \ + ( defined(CYG_HAL_STARTUP_RAM) && \ + !defined(CYGSEM_HAL_USE_ROM_MONITOR)) + + # If we are starting up from ROM, or we are starting in + # RAM and NOT using a ROM monitor, copy exception handler + # code to 0 and initialize the VSR table. + + .macro hal_mon_init + # First copy exception vectors to RAM + lwi r3,rom_vectors # r3 = rom start + lwi r4,0 # r4 = ram start + lwi r5,rom_vectors_end # r5 = rom end + cmplw r3,r5 # skip if no vectors + beq 2f + + subi r3,r3,4 + subi r4,r4,4 + subi r5,r5,4 +1: + lwzu r0,4(r3) # get word from ROM + stwu r0,4(r4) # store in RAM + cmplw r3,r5 # compare + blt 1b # loop if not yet done +2: + + # Initialize VSR table + # First fill with exception handlers + lwi r3,cyg_hal_default_exception_vsr + lwi r4,hal_vsr_table + subi r4,r4,4 + li r5,CYGNUM_HAL_VSR_COUNT +1: stwu r3,4(r4) + subi r5,r5,1 + cmpwi r5,0 + bne 1b + + # Then fill in the special vectors + lwi r3,cyg_hal_default_interrupt_vsr + lwi r4,hal_vsr_table + stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4) + stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4) + .endm + +#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR) + + # Initialize the VSR table entries + # We only take control of the interrupt vectors, + # the rest are left to the ROM for now... + + .macro hal_mon_init + lwi r3,cyg_hal_default_interrupt_vsr + lwi r4,hal_vsr_table + stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4) + stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4) + .endm + + +#else + + .macro hal_mon_init + + .endm + +#endif + + +#define CYGPKG_HAL_PPC_MON_DEFINED + +#endif // CYGPKG_HAL_PPC_MON_DEFINED + + +##----------------------------------------------------------------------------- +## Indicate that the ISR tables are defined in variant.S + +## Note: CYG_ISR_TABLE_SIZE must match CYG_ISR_COUNT defined in hal_intr.h. +#define CYG_ISR_TABLE_SIZE 2 + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_VARIANT_INC +# end of variant.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc60x/current/src/PKGconf.mak @@ -0,0 +1,45 @@ +#============================================================================== +# +# makefile +# +# hal/powerpc/ppc60x/src +# +#============================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +#============================================================================== + +PACKAGE := hal_powerpc_ppc60x +include ../../../../../pkgconf/pkgconf.mak + +LIBRARY := libtarget.a +COMPILE := var_intr.c var_misc.c variant.S +OTHER_OBJS := +OTHER_TARGETS := +OTHER_CLEAN := +OTHER_DEPS := + +include $(COMPONENT_REPOSITORY)/pkgconf/makrules.src + +EXTRAS = $(wildcard $(PREFIX)/lib/libextras.a)
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc60x/current/src/var_intr.c @@ -0,0 +1,56 @@ +//========================================================================== +// +// var_intr.c +// +// PowerPC variant interrupt handlers +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 2000-02-11 +// Purpose: PowerPC variant interrupt handlers +// Description: This file contains code to handle interrupt related issues +// on the PowerPC variant. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <cyg/hal/ppc_regs.h> + +externC void +hal_variant_IRQ_init(void) +{ + // No special init required for 60x series. +} + +// ------------------------------------------------------------------------- +// EOF var_intr.c +
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc60x/current/src/var_misc.c @@ -0,0 +1,50 @@ +//========================================================================== +// +// var_misc.c +// +// HAL implementation miscellaneous functions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 2000-02-04 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +void hal_variant_init(void) +{ +} + +//-------------------------------------------------------------------------- +// End of var_misc.c
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc60x/current/src/variant.S @@ -0,0 +1,84 @@ +##============================================================================= +## +## variant.S +## +## PowerPC PPC60x variant code +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): jskov +## Contributors:jskov +## Date: 2000-02-04 +## Purpose: PowerPC PPC60x variant code +## Description: Variant specific code for PowerPC 60x CPUs. +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#include <cyg/hal/variant.inc> + +#--------------------------------------------------------------------------- +# Interrupt vector tables. +# These tables contain the isr, data and object pointers used to deliver +# interrupts to user code. + +#if (CYG_ISR_TABLE_SIZE > 2) + .data +#else + .section ".sdata","aw" +#endif + + .extern hal_default_decrementer_isr + .extern hal_default_isr + + .globl hal_interrupt_handlers +hal_interrupt_handlers: + .long hal_default_decrementer_isr + .rept CYG_ISR_TABLE_SIZE-1 + .long hal_default_isr + .endr + + .globl hal_interrupt_data +hal_interrupt_data: + .rept CYG_ISR_TABLE_SIZE + .long 0 + .endr + + .globl hal_interrupt_objects +hal_interrupt_objects: + .rept CYG_ISR_TABLE_SIZE + .long 0 + .endr + +##----------------------------------------------------------------------------- +## end of variant.S +
--- a/packages/hal/powerpc/quicc/current/ChangeLog +++ b/packages/hal/powerpc/quicc/current/ChangeLog @@ -1,3 +1,8 @@ +2000-02-04 Jesper Skov <jskov@redhat.com> + + * src/quicc_smc1.c (cyg_quicc_smc1_uart_rcvchar): Get frequency + from new CYGHWR_HAL_POWERPC_BOARD_SPEED variable. + 2000-02-03 Jesper Skov <jskov@redhat.com> * src/quicc_smc1.c: CYG_HAL_POWERPC_x->CYGPKG_...
--- a/packages/hal/powerpc/quicc/current/src/quicc_smc1.c +++ b/packages/hal/powerpc/quicc/current/src/quicc_smc1.c @@ -60,7 +60,7 @@ #include <cyg/hal/hal_intr.h> // HAL_INTERRUPT_UNMASK(...) #endif -#define UART_BIT_RATE(n) (((CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED*1000000)/16)/n) +#define UART_BIT_RATE(n) (((CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/16)/n) #define UART_BAUD_RATE 38400 #define Rxbd 0x2800 /* Rx Buffer Descriptor Offset */
--- a/packages/hal/powerpc/sim/current/ChangeLog +++ b/packages/hal/powerpc/sim/current/ChangeLog @@ -1,3 +1,8 @@ +2000-02-07 Jesper Skov <jskov@redhat.com> + + * include/pkgconf/hal_powerpc_sim.h: + Use 60x variant code. + 2000-01-26 Jesper Skov <jskov@redhat.com> * include/plf_cache.h: Added.
--- a/packages/hal/powerpc/sim/current/include/pkgconf/hal_powerpc_sim.h +++ b/packages/hal/powerpc/sim/current/include/pkgconf/hal_powerpc_sim.h @@ -51,6 +51,7 @@ display "Minimal simulator" type radio parent CYGPKG_HAL_POWERPC + requires CYGPKG_HAL_POWERPC_PPC60x platform sim description " The minimal simulator HAL package is provided for use when
--- a/packages/infra/current/ChangeLog +++ b/packages/infra/current/ChangeLog @@ -1,3 +1,13 @@ +2000-02-08 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/cyg_trac.h: Define and document CYG_TRACE_PRINT() and + CYG_TRACE_DUMP() macros for outputting buffered trace output, and + kernel state dump respectively + + * src/fancy.cxx (cyg_trace_dump): Add (from buffer.cxx) + * src/simple.cxx (cyg_trace_dump): Add (from buffer.cxx) + * src/null.cxx (cyg_trace_dump): Add as empty function + 1999-11-26 Gary Thomas <gthomas@cygnus.co.uk> * include/cyg_type.h: Add MLT symbols CYGMEM_REGION_ATTR_R/W.
--- a/packages/infra/current/include/cyg_trac.h +++ b/packages/infra/current/include/cyg_trac.h @@ -238,6 +238,13 @@ type information, by file, function and can greatly reduce the size of an image with tracing disabled, which may be crucial in debugging on actual shipped hardware with limited memory. +If configured for buffered tracing then CYG_TRACE_PRINT() can be used to +output the contents of the trace buffer on demand. + +CYG_TRACE_DUMP() outputs a form of "core dump" containing info on the +scheduler and threads at the time. This information will be invalid if +the kernel is not running. + C/C++: in C++ the function reporting is implemented using a class object with a destructor; this allows reporting of a return which has not been explicitly reported, and detection of accidental multiple return reports. @@ -311,6 +318,12 @@ CYG_REPORT_FUNCARG1XV... CYG_REPORT_FUNCARG1YV... use "arg=%x" CYG_REPORT_FUNCARG1DV... use "arg=%d" +Other +----- + +CYG_TRACE_DUMP() dumps kernel state +CYG_TRACE_PRINT() prints buffered tracing + --------------------------------------------------------------------------- @@ -380,15 +393,35 @@ also fits in a byte as number or a bitse // ------------------------------------------------------------------------- // We define macros and appropriate prototypes for the trace/fail // system. These are: -// CYG_TRACE0..8 - trace if boolean -// CYG_TRACEPROC - default no comment proc entry -// CYG_TRACEPROCOUT - default no comment proc exit +// CYG_TRACE0..8 - trace if boolean +// CYG_TRACEPROC - default no comment proc entry +// CYG_TRACEPROCOUT - default no comment proc exit +// CYG_TRACE_DUMP - outputs a form of "core dump", including the state +// of the kernel scheduler, threads, etc. +// CYG_TRACE_PRINT - Forces manual output of any trace info that has +// been buffered up. // these are executed to deal with tracing - breakpoint? externC void cyg_tracenomsg( char *psz_func, char *psz_file, cyg_uint32 linenum ); +externC void +cyg_trace_dump(void); + +#define CYG_TRACE_DUMP() cyg_trace_dump() + +#ifdef CYGDBG_INFRA_DEBUG_TRACE_ASSERT_BUFFER + +externC void +cyg_trace_print(void); + +#define CYG_TRACE_PRINT() cyg_trace_print() + +#else +#define CYG_TRACE_PRINT() CYG_EMPTY_STATEMENT +#endif + // provide every other one of these as a space/caller bloat compromise. # ifdef CYGDBG_INFRA_DEBUG_TRACE_MESSAGE @@ -1067,6 +1100,9 @@ CYG_MACRO_END #define CYG_REPORT_RETURN() CYG_EMPTY_STATEMENT #define CYG_REPORT_RETVAL( _value_ ) CYG_EMPTY_STATEMENT +#define CYG_TRACE_PRINT() CYG_EMPTY_STATEMENT +#define CYG_TRACE_DUMP() CYG_EMPTY_STATEMENT + #endif // ! CYGDBG_USE_TRACING // -------------------------------------------------------------------------
--- a/packages/infra/current/src/fancy.cxx +++ b/packages/infra/current/src/fancy.cxx @@ -469,6 +469,117 @@ cyg_tracemsg8( cyg_uint32 what, HAL_RESTORE_INTERRUPTS(old_ints); }; +// ------------------------------------------------------------------------- + +externC void +cyg_trace_dump(void) +{ +#if defined(CYGPKG_KERNEL) && defined(CYG_DIAG_PRINTF) + + { + diag_printf("\nScheduler:\n\n"); + + Cyg_Scheduler *sched = &Cyg_Scheduler::scheduler; + + diag_printf("Lock: %d\n",sched->get_sched_lock() ); + +# ifdef CYGVAR_KERNEL_THREADS_NAME + + diag_printf("Current Thread: %s\n",sched->get_current_thread()->get_name()); + +# else + + diag_printf("Current Thread: %d\n",sched->get_current_thread()->get_unique_id()); + +# endif + + } + +# ifdef CYGVAR_KERNEL_THREADS_LIST + + { + Cyg_Thread *t = Cyg_Thread::get_list_head(); + + diag_printf("\nThreads:\n\n"); + + while( NULL != t ) + { + cyg_uint32 state = t->get_state(); + char tstate[7]; + char *tstate1 = "SCUKX"; + static char *(reasons[8]) = + { + "NONE", // No recorded reason + "WAIT", // Wait with no timeout + "DELAY", // Simple time delay + "TIMEOUT", // Wait with timeout/timeout expired + "BREAK", // forced break out of sleep + "DESTRUCT", // wait object destroyed[note] + "EXIT", // forced termination + "DONE" // Wait/delay complete + }; + + if( 0 != state ) + { + // Knock out chars that do not correspond to set bits. + for( int i = 0; i < 6 ; i++ ) + if( 0 == (state & (1<<i)) ) + tstate[i] = ' '; + else tstate[i] = tstate1[i]; + tstate[6] = 0; + } + else tstate[0] = 'R', tstate[1] = 0; + +# ifdef CYGVAR_KERNEL_THREADS_NAME + + diag_printf( "%20s pri = %3d state = %6s id = %3d\n", + t->get_name(), + t->get_priority(), + tstate, + t->get_unique_id() + ); +# else + + diag_printf( "Thread %3d pri = %3d state = %6s\n", + t->get_unique_id(), + t->get_priority(), + tstate + ); + +# endif + diag_printf( "%20s stack base = %08x ptr = %08x size = %08x\n", + "", + t->get_stack_base(), +#ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT + t->get_saved_context(), +#else + 0, +#endif + t->get_stack_size() + ); + + diag_printf( "%20s sleep reason %8s wake reason %8s\n", + "", + reasons[t->get_sleep_reason()], + reasons[t->get_wake_reason()] + ); + + diag_printf( "%20s queue = %08x wait info = %08x\n", + "", + t->get_current_queue(), + t->get_wait_info() + ); + + diag_printf("\n"); + t = t->get_list_next(); + } + + } +# endif // CYGVAR_KERNEL_THREADS_LIST + +#endif // CYG_DIAG_PRINTF +} + #endif // CYGDBG_USE_TRACING // -------------------------------------------------------------------------
--- a/packages/infra/current/src/null.cxx +++ b/packages/infra/current/src/null.cxx @@ -117,6 +117,12 @@ cyg_tracemsg8( cyg_uint32 what, CYG_ADDRWORD arg6, CYG_ADDRWORD arg7 ) {} +// ------------------------------------------------------------------------- + +externC void +cyg_trace_dump(void) +{} + #endif // CYGDBG_USE_TRACING // -------------------------------------------------------------------------
--- a/packages/infra/current/src/simple.cxx +++ b/packages/infra/current/src/simple.cxx @@ -370,6 +370,117 @@ cyg_tracemsg8( cyg_uint32 what, HAL_RESTORE_INTERRUPTS(old_ints); }; +// ------------------------------------------------------------------------- + +externC void +cyg_trace_dump(void) +{ +#if defined(CYGPKG_KERNEL) && defined(CYG_DIAG_PRINTF) + + { + diag_printf("\nScheduler:\n\n"); + + Cyg_Scheduler *sched = &Cyg_Scheduler::scheduler; + + diag_printf("Lock: %d\n",sched->get_sched_lock() ); + +# ifdef CYGVAR_KERNEL_THREADS_NAME + + diag_printf("Current Thread: %s\n",sched->get_current_thread()->get_name()); + +# else + + diag_printf("Current Thread: %d\n",sched->get_current_thread()->get_unique_id()); + +# endif + + } + +# ifdef CYGVAR_KERNEL_THREADS_LIST + + { + Cyg_Thread *t = Cyg_Thread::get_list_head(); + + diag_printf("\nThreads:\n\n"); + + while( NULL != t ) + { + cyg_uint32 state = t->get_state(); + char tstate[7]; + char *tstate1 = "SCUKX"; + static char *(reasons[8]) = + { + "NONE", // No recorded reason + "WAIT", // Wait with no timeout + "DELAY", // Simple time delay + "TIMEOUT", // Wait with timeout/timeout expired + "BREAK", // forced break out of sleep + "DESTRUCT", // wait object destroyed[note] + "EXIT", // forced termination + "DONE" // Wait/delay complete + }; + + if( 0 != state ) + { + // Knock out chars that do not correspond to set bits. + for( int i = 0; i < 6 ; i++ ) + if( 0 == (state & (1<<i)) ) + tstate[i] = ' '; + else tstate[i] = tstate1[i]; + tstate[6] = 0; + } + else tstate[0] = 'R', tstate[1] = 0; + +# ifdef CYGVAR_KERNEL_THREADS_NAME + + diag_printf( "%20s pri = %3d state = %6s id = %3d\n", + t->get_name(), + t->get_priority(), + tstate, + t->get_unique_id() + ); +# else + + diag_printf( "Thread %3d pri = %3d state = %6s\n", + t->get_unique_id(), + t->get_priority(), + tstate + ); + +# endif + diag_printf( "%20s stack base = %08x ptr = %08x size = %08x\n", + "", + t->get_stack_base(), +#ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT + t->get_saved_context(), +#else + 0, +#endif + t->get_stack_size() + ); + + diag_printf( "%20s sleep reason %8s wake reason %8s\n", + "", + reasons[t->get_sleep_reason()], + reasons[t->get_wake_reason()] + ); + + diag_printf( "%20s queue = %08x wait info = %08x\n", + "", + t->get_current_queue(), + t->get_wait_info() + ); + + diag_printf("\n"); + t = t->get_list_next(); + } + + } +# endif // CYGVAR_KERNEL_THREADS_LIST + +#endif // CYG_DIAG_PRINTF +} + #endif // CYGDBG_USE_TRACING // -------------------------------------------------------------------------
--- a/packages/io/serial/current/ChangeLog +++ b/packages/io/serial/current/ChangeLog @@ -1,3 +1,15 @@ +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + * src/sparclite/sleb_sdtr.c: + serial_devio => cyg_io_serial_devio + +2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/mn10300/mn10300_serial.c: Ensure all CYG_HAL_MN10300_* + preprocessor conditionals use the correct CYGPKG_HAL_MN10300_AM3* form + now. + 2000-02-03 Jesper Skov <jskov@redhat.com> * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_...
--- a/packages/io/serial/current/src/mn10300/mn10300_serial.c +++ b/packages/io/serial/current/src/mn10300/mn10300_serial.c @@ -115,7 +115,7 @@ static void mn10300_serial_tx_DSR( #define LCR_RXE 0x4000 // receive enable #define LCR_TXE 0x8000 // transmit enable -#if defined(CYG_HAL_MN10300_AM31) +#if defined(CYGPKG_HAL_MN10300_AM31) #define LCR_TWE 0x0100 // interrupt enable (only on serial2/AM31) #else #define LCR_TWE 0x0000 // Bit does not exist in other variants @@ -132,7 +132,7 @@ static void mn10300_serial_tx_DSR( //------------------------------------------------------------------------- // Serial and timer base registers: -#if defined(CYG_HAL_MN10300_AM31) +#if defined(CYGPKG_HAL_MN10300_AM31) #define SERIAL0_BASE 0x34000800 #define SERIAL1_BASE 0x34000810 @@ -146,7 +146,7 @@ static void mn10300_serial_tx_DSR( #define SERIAL1_TIMER_SELECT 0x0004 // timer 1 #define SERIAL2_TIMER_SELECT 0x0001 // timer 2 -#ifdef CYG_HAL_MN10300_AM31_STDEVAL1 +#ifdef CYGPKG_HAL_MN10300_AM31_STDEVAL1 // The use of PORT3 to provide CTS/CTR is specific to // the STDEVAL1 board only. #define PORT3_MD 0x36008025 @@ -199,7 +199,7 @@ static unsigned char select_parity[] = { LCR_PS, // Space parity }; -#if defined(CYG_HAL_MN10300_AM31) +#if defined(CYGPKG_HAL_MN10300_AM31) static unsigned short select_baud_01[] = { 0, // Unused @@ -300,7 +300,7 @@ static SERIAL_FUNS(mn10300_serial_funs, //------------------------------------------------------------------------- // Hardware info for each serial line -#ifndef CYG_HAL_MN10300_STDEVAL1 +#ifndef CYGPKG_HAL_MN10300_AM31_STDEVAL1 #ifdef CYGPKG_IO_SERIAL_MN10300_SERIAL0 static mn10300_serial_info mn10300_serial_info0 = { SERIAL0_BASE, @@ -357,7 +357,7 @@ static unsigned char mn10300_serial_in_b #define SIZEOF_BUF(_x_) sizeof(_x_) #endif -#ifndef CYG_HAL_MN10300_STDEVAL1 +#ifndef CYGPKG_HAL_MN10300_AM31_STDEVAL1 #ifdef CYGPKG_IO_SERIAL_MN10300_SERIAL0 #if CYGNUM_IO_SERIAL_MN10300_SERIAL0_BUFSIZE > 0 static SERIAL_CHANNEL_USING_INTERRUPTS(mn10300_serial_channel0, @@ -446,7 +446,7 @@ static SERIAL_CHANNEL(mn10300_serial_cha //------------------------------------------------------------------------- // And finally, the device table entries: -#ifndef CYG_HAL_MN10300_STDEVAL1 +#ifndef CYGPKG_HAL_MN10300_AM31_STDEVAL1 #ifdef CYGPKG_IO_SERIAL_MN10300_SERIAL0 // On the standard eval board serial0 is not connected. If enabled, it // generates continuous frame error and overrun interrupts. Hence we do @@ -577,7 +577,7 @@ mn10300_serial_config_port(serial_channe cr |= LCR_RXE | LCR_TXE; // enable Rx and Tx -#ifdef CYG_HAL_MN10300_AM31 +#ifdef CYGPKG_HAL_MN10300_AM31 if( mn10300_chan->is_serial2 ) { // AM31 has an extra TX interrupt enable bit for serial 2.
--- a/packages/io/serial/current/src/sparclite/sleb_sdtr.c +++ b/packages/io/serial/current/src/sparclite/sleb_sdtr.c @@ -162,7 +162,7 @@ static SERIAL_CHANNEL(sleb_sdtr_channel1 DEVTAB_ENTRY(sleb_sdtr_io1, CYGDAT_IO_SERIAL_SPARCLITE_SLEB_CON2_NAME, 0, // Does not depend on a lower level interface - &serial_devio, + &cyg_io_serial_devio, sleb_sdtr_init, sleb_sdtr_lookup, // Serial driver may need initializing &sleb_sdtr_channel1
--- a/packages/kernel/current/ChangeLog +++ b/packages/kernel/current/ChangeLog @@ -1,3 +1,13 @@ +2000-02-11 Jesper Skov <jskov@redhat.com> + + * tests/dhrystone.c (PASSES): Reduced for MPC8xx targets. + +2000-02-10 Jesper Skov <jskov@redhat.com> + + * tests/except1.cxx (except0_main): + * tests/kexcept1.c (except0_main): + Also reclaim DATA_TLB_MISS vector if available. + 2000-02-03 Jesper Skov <jskov@redhat.com> * src/sched/lottery.cxx (schedule): CYG_HAL_POWERPC_x->CYGPKG_...
--- a/packages/kernel/current/tests/dhrystone.c +++ b/packages/kernel/current/tests/dhrystone.c @@ -61,6 +61,8 @@ dtime(void) #define PASSES 100000 #elif defined(CYGPKG_HAL_ARM_CMA230) #define PASSES 100000 +#elif defined(CYGPKG_HAL_POWERPC_MPC8xx) +#define PASSES 250000 #else #define PASSES 400000 #endif
--- a/packages/kernel/current/tests/except1.cxx +++ b/packages/kernel/current/tests/except1.cxx @@ -183,6 +183,9 @@ void except0_main( void ) #ifdef CYGNUM_HAL_EXCEPTION_DATA_ACCESS HAL_VSR_SET_TO_ECOS_HANDLER( CYGNUM_HAL_EXCEPTION_DATA_ACCESS, NULL ); #endif +#ifdef CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS + HAL_VSR_SET_TO_ECOS_HANDLER( CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS, NULL ); +#endif #ifdef CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS HAL_VSR_SET_TO_ECOS_HANDLER( CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS, NULL ); #endif
--- a/packages/kernel/current/tests/kexcept1.c +++ b/packages/kernel/current/tests/kexcept1.c @@ -190,6 +190,9 @@ void except0_main( void ) #ifdef CYGNUM_HAL_EXCEPTION_DATA_ACCESS HAL_VSR_SET_TO_ECOS_HANDLER( CYGNUM_HAL_EXCEPTION_DATA_ACCESS, NULL ); #endif +#ifdef CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS + HAL_VSR_SET_TO_ECOS_HANDLER( CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS, NULL ); +#endif #ifdef CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS HAL_VSR_SET_TO_ECOS_HANDLER( CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS, NULL ); #endif
--- a/packages/language/c/libc/current/ChangeLog +++ b/packages/language/c/libc/current/ChangeLog @@ -1,3 +1,8 @@ +2000-02-10 Jesper Skov <jskov@redhat.com> + + * tests/signal/signal2.c (main): + Also reclaim DATA_TLB_MISS vector if available. + 1999-10-19 Jonathan Larmour <jlarmour@cygnus.co.uk> * src/stdio/output/vfnprintf.cxx: We can now remove Berkeley
--- a/packages/language/c/libc/current/tests/signal/signal2.c +++ b/packages/language/c/libc/current/tests/signal/signal2.c @@ -167,6 +167,9 @@ main( int argc, char *argv[] ) #ifdef CYGNUM_HAL_EXCEPTION_DATA_ACCESS HAL_VSR_SET_TO_ECOS_HANDLER( CYGNUM_HAL_EXCEPTION_DATA_ACCESS, NULL ); #endif +#ifdef CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS + HAL_VSR_SET_TO_ECOS_HANDLER( CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS, NULL ); +#endif #ifdef CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS HAL_VSR_SET_TO_ECOS_HANDLER( CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS, NULL ); #endif
--- a/packages/packages +++ b/packages/packages @@ -250,6 +250,18 @@ package CYGPKG_HAL_QUICC { include_dir cyg/hal/quicc hardware } +package CYGPKG_HAL_POWERPC_MPC8xx { + alias { "PowerPC MPC8x family support" hal_powerpc_mpc8xx mpc8xx_hal mpc8xx } + directory hal/powerpc/mpc8xx + include_dir cyg/hal + hardware +} +package CYGPKG_HAL_POWERPC_PPC60x { + alias { "PowerPC 60x family support" hal_powerpc_ppc60x ppc60x_hal ppc60x } + directory hal/powerpc/ppc60x + include_dir cyg/hal + hardware +} package CYGPKG_HAL_POWERPC_SIM { alias { "PowerPC simulator support" hal_powerpc_sim powerpc_sim_hal } directory hal/powerpc/sim
--- a/packages/targets +++ b/packages/targets @@ -161,6 +161,7 @@ target powerpc { alias { "Cogent board" } startup { ram rom stubs } packages { + CYGPKG_HAL_POWERPC_MPC8xx CYGPKG_HAL_POWERPC_COGENT } } @@ -168,6 +169,7 @@ target powerpc { alias { "FADS board" } startup { ram rom } packages { + CYGPKG_HAL_POWERPC_MPC8xx CYGPKG_HAL_POWERPC_FADS } } @@ -176,6 +178,7 @@ target powerpc { startup { ram rom } packages { CYGPKG_HAL_POWERPC_MBX + CYGPKG_HAL_POWERPC_MPC8xx CYGPKG_HAL_QUICC } } @@ -183,6 +186,7 @@ target powerpc { alias { "Simulator" } startup { ram } packages { + CYGPKG_HAL_POWERPC_PPC60x CYGPKG_HAL_POWERPC_SIM } } @@ -208,8 +212,8 @@ target i386 { packages { CYGPKG_HAL_I386_LINUX } + } - } } target arm {