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annotate packages/hal/arm/ebsa285/current/include/hal_platform_ints.h @ 110:84e4bde58b26 ecos-sw-2000-07-14

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Merge from eCos master repository on 2000-07-14-22:00:02-BST
author jlarmour
date Mon, 17 Jul 2000 14:42:27 +0000
parents 435cced73e2f
children 25e238959bae
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1 #ifndef CYGONCE_HAL_PLATFORM_INTS_H
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2 #define CYGONCE_HAL_PLATFORM_INTS_H
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3 //==========================================================================
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4 //
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5 // hal_platform_ints.h
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6 //
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7 // HAL Interrupt and clock support
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8 //
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9 //==========================================================================
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10 //####COPYRIGHTBEGIN####
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11 //
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12 // -------------------------------------------
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13 // The contents of this file are subject to the Red Hat eCos Public License
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14 // Version 1.1 (the "License"); you may not use this file except in
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15 // compliance with the License. You may obtain a copy of the License at
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16 // http://www.redhat.com/
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17 //
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18 // Software distributed under the License is distributed on an "AS IS"
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19 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 // License for the specific language governing rights and limitations under
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21 // the License.
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22 //
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23 // The Original Code is eCos - Embedded Configurable Operating System,
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24 // released September 30, 1998.
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25 //
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26 // The Initial Developer of the Original Code is Red Hat.
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27 // Portions created by Red Hat are
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28 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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29 // All Rights Reserved.
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30 // -------------------------------------------
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31 //
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32 //####COPYRIGHTEND####
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33 //==========================================================================
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34 //#####DESCRIPTIONBEGIN####
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35 //
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36 // Author(s): hmt
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37 // Contributors: hmt
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38 // Date: 1999-04-21
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39 // Purpose: Define Interrupt support
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40 // Description: The interrupt details for the EBSA285 are defined here.
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41 // Usage:
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42 // #include <cyg/hal/hal_platform_ints.h>
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43 // ...
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44 //
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45 //
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46 //####DESCRIPTIONEND####
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47 //
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48 //==========================================================================
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49
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50 #define CYGNUM_HAL_INTERRUPT_reserved0 0
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51 #define CYGNUM_HAL_INTERRUPT_SOFT_IRQ 1
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52 #define CYGNUM_HAL_INTERRUPT_SERIAL_RX 2
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53 #define CYGNUM_HAL_INTERRUPT_SERIAL_TX 3
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54 #define CYGNUM_HAL_INTERRUPT_TIMER_1 4
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55 #define CYGNUM_HAL_INTERRUPT_TIMER_2 5
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56 #define CYGNUM_HAL_INTERRUPT_TIMER_3 6
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57 #define CYGNUM_HAL_INTERRUPT_TIMER_4 7
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58 #define CYGNUM_HAL_INTERRUPT_IRQ_IN_0 8
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59 #define CYGNUM_HAL_INTERRUPT_IRQ_IN_1 9
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60 #define CYGNUM_HAL_INTERRUPT_IRQ_IN_2 10
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61 #define CYGNUM_HAL_INTERRUPT_IRQ_IN_3 11
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62 #define CYGNUM_HAL_INTERRUPT_XBUS_CS_0 12
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63 #define CYGNUM_HAL_INTERRUPT_XBUS_CS_1 13
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64 #define CYGNUM_HAL_INTERRUPT_XBUS_CS_2 14
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65 #define CYGNUM_HAL_INTERRUPT_DOORBELL 15
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66 #define CYGNUM_HAL_INTERRUPT_DMA_1 16
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67 #define CYGNUM_HAL_INTERRUPT_DMA_2 17
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68 #define CYGNUM_HAL_INTERRUPT_PCI_IRQ 18
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69 #define CYGNUM_HAL_INTERRUPT_PMCSR 19
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70 #define CYGNUM_HAL_INTERRUPT_reserved20 20
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71 #define CYGNUM_HAL_INTERRUPT_reserved21 21
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72 #define CYGNUM_HAL_INTERRUPT_BIST 22
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73 #define CYGNUM_HAL_INTERRUPT_SERR 23
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74 #define CYGNUM_HAL_INTERRUPT_SDRAM_PARITY 24
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75 #define CYGNUM_HAL_INTERRUPT_I2O_POST 25
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76 #define CYGNUM_HAL_INTERRUPT_reserved26 26
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77 #define CYGNUM_HAL_INTERRUPT_DISCARD_TIMER 27
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78 #define CYGNUM_HAL_INTERRUPT_PCI_DATA_PARITY 28
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79 #define CYGNUM_HAL_INTERRUPT_PCI_MASTER_ABORT 29
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80 #define CYGNUM_HAL_INTERRUPT_PCI_TARGET_ABORT 30
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81 #define CYGNUM_HAL_INTERRUPT_PCI_PARITY_ERROR 31
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82
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83 #define CYGNUM_HAL_ISR_MIN 0
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84 #define CYGNUM_HAL_ISR_MAX 31
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85
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86 #define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1)
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87
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88 // The vector used by the Real time clock
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89 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER_3
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90
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91 #endif // CYGONCE_HAL_PLATFORM_INTS_H