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annotate packages/devs/serial/sparclite/sleb/current/src/sleb_sdtr.c @ 130:eb9fd8c04db3 ecos-sw-2000-10-23

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Merge from eCos master repository on 2000-10-23-17:01:37-BST
author jlarmour
date Mon, 23 Oct 2000 17:10:57 +0000
parents 6ed91473a1cd
children e0c0827131d1
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1 //==========================================================================
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2 //
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3 // io/serial/sparclite/sleb_sdtr.c
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4 //
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5 // Serial I/O interface module for SPARClite Eval Board (SLEB)
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //==========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): gthomas
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35 // Contributors: gthomas
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36 // Date: 1999-02-04
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37 // Purpose: SLEB serial I/O module
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38 // Description:
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39 //
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40 //####DESCRIPTIONEND####
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41 //
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42 //==========================================================================
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43
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44 #include <pkgconf/io.h>
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45 #include <pkgconf/io_serial.h>
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46 #include <cyg/io/io.h>
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47 #include <cyg/hal/hal_intr.h>
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48 #include <cyg/io/devtab.h>
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49 #include <cyg/io/serial.h>
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50
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51 #ifdef CYGPKG_IO_SERIAL_SPARCLITE_SLEB
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52
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53 #include "sleb_sdtr.h"
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54
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55 extern void diag_printf(const char *fmt, ...);
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56
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57 #define BUFSIZE 128
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58
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59 typedef struct sleb_sdtr_info {
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60 CYG_ADDRWORD base;
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61 CYG_WORD tx_int_num;
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62 CYG_WORD rx_int_num;
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63 cyg_interrupt tx_serial_interrupt;
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64 cyg_handle_t tx_serial_interrupt_handle;
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65 cyg_interrupt rx_serial_interrupt;
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66 cyg_handle_t rx_serial_interrupt_handle;
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67 cyg_uint8 cmd_reg;
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68 bool xmit_enabled;
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69 } sleb_sdtr_info;
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70
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71 static bool sleb_sdtr_init(struct cyg_devtab_entry *tab);
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72 static bool sleb_sdtr_putc(serial_channel *chan, unsigned char c);
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73 static Cyg_ErrNo sleb_sdtr_lookup(struct cyg_devtab_entry **tab,
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74 struct cyg_devtab_entry *sub_tab,
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75 const char *name);
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76 static unsigned char sleb_sdtr_getc(serial_channel *chan);
115
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77 static Cyg_ErrNo sleb_sdtr_set_config(serial_channel *chan, cyg_uint32 key,
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78 const void *xbuf, cyg_uint32 *len);
82
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79 static void sleb_sdtr_start_xmit(serial_channel *chan);
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80 static void sleb_sdtr_stop_xmit(serial_channel *chan);
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81
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82 static cyg_uint32 sleb_sdtr_tx_ISR(cyg_vector_t vector, cyg_addrword_t data);
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83 static void sleb_sdtr_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data);
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84 static cyg_uint32 sleb_sdtr_rx_ISR(cyg_vector_t vector, cyg_addrword_t data);
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85 static void sleb_sdtr_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data);
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86
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87 static SERIAL_FUNS(sleb_sdtr_funs,
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88 sleb_sdtr_putc,
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89 sleb_sdtr_getc,
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90 sleb_sdtr_set_config,
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91 sleb_sdtr_start_xmit,
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92 sleb_sdtr_stop_xmit
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93 );
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94
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95 #ifdef CYGPKG_IO_SERIAL_SPARCLITE_SLEB_CON1
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96 static sleb_sdtr_info sleb_sdtr_info0 = {SLEB_SDTR0_BASE, SLEB_SDTR0_TX_INT, SLEB_SDTR0_RX_INT};
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97 #if CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON1_BUFSIZE > 0
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98 static unsigned char sleb_sdtr_out_buf0[CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON1_BUFSIZE];
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99 static unsigned char sleb_sdtr_in_buf0[CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON1_BUFSIZE];
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100
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101 static SERIAL_CHANNEL_USING_INTERRUPTS(sleb_sdtr_channel0,
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102 sleb_sdtr_funs,
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103 sleb_sdtr_info0,
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104 CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON1_BAUD),
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105 CYG_SERIAL_STOP_DEFAULT,
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106 CYG_SERIAL_PARITY_DEFAULT,
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107 CYG_SERIAL_WORD_LENGTH_DEFAULT,
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108 CYG_SERIAL_FLAGS_DEFAULT,
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109 &sleb_sdtr_out_buf0[0], sizeof(sleb_sdtr_out_buf0),
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110 &sleb_sdtr_in_buf0[0], sizeof(sleb_sdtr_in_buf0)
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111 );
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112 #else
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113 static SERIAL_CHANNEL(sleb_sdtr_channel0,
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114 sleb_sdtr_funs,
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115 sleb_sdtr_info0,
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116 CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON1_BAUD),
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117 CYG_SERIAL_STOP_DEFAULT,
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118 CYG_SERIAL_PARITY_DEFAULT,
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119 CYG_SERIAL_WORD_LENGTH_DEFAULT,
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120 CYG_SERIAL_FLAGS_DEFAULT
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121 );
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122 #endif
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123
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124 DEVTAB_ENTRY(sleb_sdtr_io0,
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125 CYGDAT_IO_SERIAL_SPARCLITE_SLEB_CON1_NAME,
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126 0, // Does not depend on a lower level interface
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127 &cyg_io_serial_devio,
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128 sleb_sdtr_init,
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129 sleb_sdtr_lookup, // Serial driver may need initializing
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130 &sleb_sdtr_channel0
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131 );
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132 #endif // CYGPKG_IO_SERIAL_SPARCLITE_SLEB_CON1
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133
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134 #ifdef CYGPKG_IO_SERIAL_SPARCLITE_SLEB_CON2
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135 static sleb_sdtr_info sleb_sdtr_info1 = {SLEB_SDTR1_BASE, SLEB_SDTR1_TX_INT, SLEB_SDTR1_RX_INT};
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136 #if CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON2_BUFSIZE > 0
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137 static unsigned char sleb_sdtr_out_buf1[CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON2_BUFSIZE];
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138 static unsigned char sleb_sdtr_in_buf1[CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON2_BUFSIZE];
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139
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140 static SERIAL_CHANNEL_USING_INTERRUPTS(sleb_sdtr_channel1,
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141 sleb_sdtr_funs,
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142 sleb_sdtr_info1,
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143 CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON2_BAUD),
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144 CYG_SERIAL_STOP_DEFAULT,
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145 CYG_SERIAL_PARITY_DEFAULT,
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146 CYG_SERIAL_WORD_LENGTH_DEFAULT,
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147 CYG_SERIAL_FLAGS_DEFAULT,
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148 &sleb_sdtr_out_buf1[0], sizeof(sleb_sdtr_out_buf1),
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149 &sleb_sdtr_in_buf1[0], sizeof(sleb_sdtr_in_buf1)
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150 );
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151 #else
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152 static SERIAL_CHANNEL(sleb_sdtr_channel1,
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153 sleb_sdtr_funs,
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154 sleb_sdtr_info1,
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155 CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_SPARCLITE_SLEB_CON2_BAUD),
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156 CYG_SERIAL_STOP_DEFAULT,
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157 CYG_SERIAL_PARITY_DEFAULT,
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158 CYG_SERIAL_WORD_LENGTH_DEFAULT,
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159 CYG_SERIAL_FLAGS_DEFAULT
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160 );
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161 #endif
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162
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163 DEVTAB_ENTRY(sleb_sdtr_io1,
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164 CYGDAT_IO_SERIAL_SPARCLITE_SLEB_CON2_NAME,
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165 0, // Does not depend on a lower level interface
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166 &cyg_io_serial_devio,
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167 sleb_sdtr_init,
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168 sleb_sdtr_lookup, // Serial driver may need initializing
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169 &sleb_sdtr_channel1
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170 );
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171 #endif // CYGPKG_IO_SERIAL_SPARCLITE_SLEB_CON2
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172
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173 // Internal function to actually configure the hardware to desired baud rate, etc.
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174 static bool
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175 sleb_sdtr_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init)
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176 {
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177 sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv;
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178 CYG_ADDRWORD port = sdtr_chan->base;
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179 cyg_int32 baud_divisor;
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180 cyg_int32 clk, tval;
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181 unsigned char mode;
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182 #if 0
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183 if ((new_config->baud < CYGNUM_SERIAL_BAUD_MIN) || (new_config->baud > CYGNUM_SERIAL_BAUD_MAX))
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184 return false; // Invalid baud rate
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185 #endif
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186 baud_divisor = select_baud[new_config->baud];
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187 if (baud_divisor == 0)
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188 return false; // Unsupported baud rate
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189 // Reset the port
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190 HAL_SPARC_86940_WRITE(SDTR_CONTROL(port), SDTR_CMD_RST);
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191 // Write the mode
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192 mode = SDTR_MODE_MODE_ASYNC16 |
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193 select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] |
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194 select_stop_bits[new_config->stop] |
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195 select_parity[new_config->parity];
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196 HAL_SPARC_86940_WRITE(SDTR_CONTROL(port), mode);
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197 // Set baud rate clock.
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198 // ***** CAUTION! Both ports use the same time, thus they must both run at the same baud rate!
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199 clk = *SLEB_CLOCK_SWITCH; // Compute board speed
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200 if (clk & 0x80) clk = 10;
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201 clk = (clk & 0x3F) * 1000000; // in MHz
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202 tval = (clk / (baud_divisor * 32)) - 1;
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203 HAL_SPARC_86940_WRITE(SLEB_TIMER3_RELOAD, tval);
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204 // Set up control register
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205 sdtr_chan->cmd_reg = SDTR_CMD_RTS | SDTR_CMD_DTR | SDTR_CMD_TxEN;
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206 #ifdef CYGPKG_IO_SERIAL_SPARCLITE_SLEB_CON1
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207 // Cygmon needs the receiver
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208 if ((chan->out_cbuf.len != 0) || (chan == &sleb_sdtr_channel0)) {
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209 #else
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210 if (chan->out_cbuf.len != 0) {
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211 #endif
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212 sdtr_chan->cmd_reg |= SDTR_CMD_RxEN;
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213 }
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214 if (init) {
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215 sdtr_chan->xmit_enabled = false;
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216 }
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217 HAL_SPARC_86940_WRITE(SDTR_CONTROL(port), sdtr_chan->cmd_reg);
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218 if (new_config != &chan->config)
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219 chan->config = *new_config;
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220 return true;
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221 }
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222
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223 // Function to initialize the device. Called at bootstrap time.
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224 static bool
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225 sleb_sdtr_init(struct cyg_devtab_entry *tab)
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226 {
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227 serial_channel *chan = (serial_channel *)tab->priv;
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228 sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv;
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229 #ifdef CYGDBG_IO_INIT
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230 diag_printf("SLEB SERIAL init - dev: %x.%d.%d\n", sdtr_chan->base, sdtr_chan->tx_int_num, sdtr_chan->rx_int_num);
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231 #endif
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232 (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices
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233 if (chan->out_cbuf.len != 0) {
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234 cyg_drv_interrupt_create(sdtr_chan->tx_int_num,
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235 99, // Priority - unused
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236 (cyg_addrword_t)chan, // Data item passed to interrupt handler
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237 sleb_sdtr_tx_ISR,
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238 sleb_sdtr_tx_DSR,
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239 &sdtr_chan->tx_serial_interrupt_handle,
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240 &sdtr_chan->tx_serial_interrupt);
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241 cyg_drv_interrupt_attach(sdtr_chan->tx_serial_interrupt_handle);
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242 cyg_drv_interrupt_mask(sdtr_chan->tx_int_num);
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243 cyg_drv_interrupt_create(sdtr_chan->rx_int_num,
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244 99, // Priority - unused
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245 (cyg_addrword_t)chan, // Data item passed to interrupt handler
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246 sleb_sdtr_rx_ISR,
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247 sleb_sdtr_rx_DSR,
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248 &sdtr_chan->rx_serial_interrupt_handle,
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249 &sdtr_chan->rx_serial_interrupt);
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250 cyg_drv_interrupt_attach(sdtr_chan->rx_serial_interrupt_handle);
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251 cyg_drv_interrupt_unmask(sdtr_chan->rx_int_num);
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252 }
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253 sleb_sdtr_config_port(chan, &chan->config, true);
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254 return true;
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255 }
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256
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257 // This routine is called when the device is "looked" up (i.e. attached)
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258 static Cyg_ErrNo
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259 sleb_sdtr_lookup(struct cyg_devtab_entry **tab,
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260 struct cyg_devtab_entry *sub_tab,
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261 const char *name)
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262 {
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263 serial_channel *chan = (serial_channel *)(*tab)->priv;
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264 (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices
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265 return ENOERR;
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266 }
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267
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268 // Send a character to the device output buffer.
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269 // Return 'true' if character is sent to device
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270 static bool
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271 sleb_sdtr_putc(serial_channel *chan, unsigned char c)
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272 {
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273 sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv;
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274 CYG_ADDRWORD port = sdtr_chan->base;
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275 cyg_uint8 status;
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276 HAL_SPARC_86940_READ(SDTR_STATUS(port), status);
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277 if (status & SDTR_STAT_TxRDY) {
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278 // Transmit buffer is empty
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279 HAL_SPARC_86940_WRITE(SDTR_TXDATA(port), c);
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280 return true;
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281 } else {
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282 // No space
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283 return false;
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284 }
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285 }
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286
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287 // Fetch a character from the device input buffer, waiting if necessary
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288 static unsigned char
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289 sleb_sdtr_getc(serial_channel *chan)
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290 {
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291 unsigned char c;
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292 sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv;
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293 CYG_ADDRWORD port = sdtr_chan->base;
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294 cyg_uint8 status;
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295 HAL_SPARC_86940_READ(SDTR_STATUS(port), status);
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296 while ((status & SDTR_STAT_RxRDY) == 0)
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297 HAL_SPARC_86940_READ(SDTR_STATUS(port), status); // Wait for char
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298 HAL_SPARC_86940_READ(SDTR_RXDATA(port), c);
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299 return c;
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300 }
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301
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302 // Set up the device characteristics; baud rate, etc.
115
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303 static Cyg_ErrNo
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304 sleb_sdtr_set_config(serial_channel *chan, cyg_uint32 key,
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305 const void *xbuf, cyg_uint32 *len)
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306 {
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307 switch (key) {
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308 case CYG_IO_SET_CONFIG_SERIAL_INFO:
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309 {
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310 cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf;
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311 if ( *len < sizeof(cyg_serial_info_t) ) {
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312 return -EINVAL;
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313 }
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314 *len = sizeof(cyg_serial_info_t);
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315 if ( true != sleb_sdtr_config_port(chan, config, false) )
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316 return -EINVAL;
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317 }
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318 break;
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319 default:
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320 return -EINVAL;
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321 }
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322 return ENOERR;
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323 }
82
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324
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325 // Enable the transmitter on the device
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326 static void
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327 sleb_sdtr_start_xmit(serial_channel *chan)
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328 {
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329 sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv;
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330 sdtr_chan->xmit_enabled = true;
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331 cyg_drv_interrupt_unmask(sdtr_chan->tx_int_num);
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332 }
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333
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334 // Disable the transmitter on the device
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335 static void
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336 sleb_sdtr_stop_xmit(serial_channel *chan)
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337 {
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338 sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv;
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339 cyg_drv_interrupt_mask(sdtr_chan->tx_int_num);
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340 sdtr_chan->xmit_enabled = false;
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341 }
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342
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343 // Serial I/O - low level interrupt handler (ISR)
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344 static cyg_uint32
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345 sleb_sdtr_tx_ISR(cyg_vector_t vector, cyg_addrword_t data)
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346 {
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347 serial_channel *chan = (serial_channel *)data;
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348 sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv;
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349 cyg_drv_interrupt_mask(sdtr_chan->tx_int_num);
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350 cyg_drv_interrupt_acknowledge(sdtr_chan->tx_int_num);
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351 return CYG_ISR_CALL_DSR; // Cause DSR to be run
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352 }
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353
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354 // Serial I/O - high level interrupt handler (DSR)
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355 static void
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356 sleb_sdtr_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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357 {
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358 serial_channel *chan = (serial_channel *)data;
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359 sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv;
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360 (chan->callbacks->xmt_char)(chan);
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361 if (sdtr_chan->xmit_enabled)
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362 cyg_drv_interrupt_unmask(sdtr_chan->tx_int_num);
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363 }
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364
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365 // Serial I/O - low level interrupt handler (ISR)
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366 static cyg_uint32
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367 sleb_sdtr_rx_ISR(cyg_vector_t vector, cyg_addrword_t data)
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368 {
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369 serial_channel *chan = (serial_channel *)data;
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370 sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv;
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371 cyg_drv_interrupt_mask(sdtr_chan->rx_int_num);
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372 return CYG_ISR_CALL_DSR; // Cause DSR to be run
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373 }
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374
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375 // Serial I/O - high level interrupt handler (DSR)
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376 static void
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377 sleb_sdtr_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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378 {
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379 serial_channel *chan = (serial_channel *)data;
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380 sleb_sdtr_info *sdtr_chan = (sleb_sdtr_info *)chan->dev_priv;
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381 CYG_ADDRWORD port = sdtr_chan->base;
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382 cyg_uint8 status, c;
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383 HAL_SPARC_86940_READ(SDTR_STATUS(port), status);
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384 if ((status & SDTR_STAT_RxRDY) != 0) {
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385 HAL_SPARC_86940_READ(SDTR_RXDATA(port), c);
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386 (chan->callbacks->rcv_char)(chan, c);
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387 }
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388 cyg_drv_interrupt_acknowledge(sdtr_chan->rx_int_num);
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389 cyg_drv_interrupt_unmask(sdtr_chan->rx_int_num);
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390 }
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391
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392 #endif // CYGPKG_IO_SERIAL_SPARCLITE_SLEB