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* Added execute permissions to files missed in conversion from CVS
author alexs
date Mon, 12 Oct 2009 02:26:09 +0100
parents 10851723ceff
children
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1 #ifndef CYGONCE_HAL_HAL_ARCH_H
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2 #define CYGONCE_HAL_HAL_ARCH_H
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3 //==========================================================================
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4 //
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5 // hal_arch.h
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6 //
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7 // Architecture specific abstractions
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8 //
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9 //==========================================================================
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10 //####ECOSGPLCOPYRIGHTBEGIN####
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11 // -------------------------------------------
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12 // This file is part of eCos, the Embedded Configurable Operating System.
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13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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14 //
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15 // eCos is free software; you can redistribute it and/or modify it under
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16 // the terms of the GNU General Public License as published by the Free
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17 // Software Foundation; either version 2 or (at your option) any later version.
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18 //
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19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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22 // for more details.
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23 //
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24 // You should have received a copy of the GNU General Public License along
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25 // with eCos; if not, write to the Free Software Foundation, Inc.,
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26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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27 //
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28 // As a special exception, if other files instantiate templates or use macros
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29 // or inline functions from this file, or you compile this file and link it
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30 // with other works to produce a work based on this file, this file does not
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31 // by itself cause the resulting work to be covered by the GNU General Public
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32 // License. However the source code for this file must still be made available
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33 // in accordance with section (3) of the GNU General Public License.
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34 //
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35 // This exception does not invalidate any other reasons why a work based on
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36 // this file might be covered by the GNU General Public License.
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37 //
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38 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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39 // at http://sources.redhat.com/ecos/ecos-license/
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40 // -------------------------------------------
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41 //####ECOSGPLCOPYRIGHTEND####
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42 //==========================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): Yoshinori Sato
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46 // Contributors: Yoshinori Sato
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47 // Date: 2002-02-13
208
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48 // Purpose: Define architecture abstractions
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49 // Usage: #include <cyg/hal/hal_arch.h>
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50 //
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51 //####DESCRIPTIONEND####
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52 //
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53 //==========================================================================
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54
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55 #include <pkgconf/hal.h>
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56 #include <cyg/infra/cyg_type.h>
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57
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58 #include <cyg/hal/var_arch.h>
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59
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60 //--------------------------------------------------------------------------
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61 // Exception handling function.
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62 // This function is defined by the kernel according to this prototype. It is
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63 // invoked from the HAL to deal with any CPU exceptions that the HAL does
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64 // not want to deal with itself. It usually invokes the kernel's exception
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65 // delivery mechanism.
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66
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67 externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
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68
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69 //--------------------------------------------------------------------------
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70 // Bit manipulation routines
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71
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72 externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask);
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73 externC cyg_uint32 hal_msbit_index(cyg_uint32 mask);
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74
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75 #define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask);
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76
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77 #define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask);
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78
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79 //--------------------------------------------------------------------------
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80 // Context Initialization
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81 // Initialize the context of a thread.
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82 // Arguments:
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83 // _sp_ name of variable containing current sp, will be written with new sp
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84 // _thread_ thread object address, passed as argument to entry point
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85 // _entry_ entry point address.
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86 // _id_ bit pattern used in initializing registers, for debugging.
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87
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88 #ifndef HAL_THREAD_INIT_CONTEXT_EXTRA
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89 #define HAL_THREAD_INIT_CONTEXT_EXTRA(_regs_, _id_)
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90 #endif
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91
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92 #define HAL_THREAD_INIT_CONTEXT( _sp_, _thread_, _entry_, _id_ ) \
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93 { \
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94 register HAL_SavedRegisters *_regs_; \
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95 _regs_ = (HAL_SavedRegisters *)(((CYG_ADDRWORD)(_sp_)) - \
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96 sizeof(HAL_SavedRegisters)); \
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97 HAL_THREAD_INIT_CONTEXT_EXTRA(_regs_, _id_); \
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98 _regs_->er0 = (CYG_WORD)(_thread_); \
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99 _regs_->er1 = (_id_)|0xddd1; \
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100 _regs_->er2 = (_id_)|0xddd2; \
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101 _regs_->er3 = (_id_)|0xddd3; \
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102 _regs_->er4 = (_id_)|0xddd4; \
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103 _regs_->er5 = (_id_)|0xddd5; \
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104 _regs_->er6 = (_id_)|0xddd6; \
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105 _regs_->pc = (CYG_WORD)(_entry_); \
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106 _regs_->ccr = 0x00; \
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107 _sp_ = (CYG_ADDRESS)_regs_; \
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108 }
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109
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110 //--------------------------------------------------------------------------
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111 // Context switch macros.
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112 // The arguments are pointers to locations where the stack pointer
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113 // of the current thread is to be stored, and from where the sp of the
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114 // next thread is to be fetched.
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115
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116 externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
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117 externC void hal_thread_load_context( CYG_ADDRESS to )
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118 __attribute__ ((noreturn));
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119
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120 #define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \
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121 hal_thread_switch_context((CYG_ADDRESS)_tspptr_, \
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122 (CYG_ADDRESS)_fspptr_);
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123
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124 #define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \
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125 hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
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126
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127 //--------------------------------------------------------------------------
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128 // Execution reorder barrier.
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129 // When optimizing the compiler can reorder code. In multithreaded systems
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130 // where the order of actions is vital, this can sometimes cause problems.
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131 // This macro may be inserted into places where reordering should not happen.
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132
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133 #define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
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134
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135 //--------------------------------------------------------------------------
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136 // Breakpoint support
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137 // HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to
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138 // happen if executed.
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139 // HAL_BREAKINST is the value of the breakpoint instruction and
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140 // HAL_BREAKINST_SIZE is its size in bytes.
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141
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142 #define __HAL_BREAKPOINT(_label_) # _label_
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143 #define HAL_BREAKPOINT(_label_) \
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144 asm volatile (" .globl " __HAL_BREAKPOINT(_label_) "\n" \
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145 __HAL_BREAKPOINT(_label_) ":\n\t" \
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146 "trapa #3" \
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147 );
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148
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149 #define HAL_BREAKINST 0x5730
208
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150
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151 #define HAL_BREAKINST_SIZE 2
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152
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153 //--------------------------------------------------------------------------
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154 // Thread register state manipulation for GDB support.
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155
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156 // Translate a stack pointer as saved by the thread context macros above into
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157 // a pointer to a HAL_SavedRegisters structure.
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158 #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
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159 (_regs_) = (HAL_SavedRegisters *)(_sp_)
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160
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161 #ifndef HAL_GET_GDB_EXTRA_REGISTERS
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162 #define HAL_GET_GDB_EXTRA_REGISTERS( _regval_, _regs_ )
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163 #endif
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164 #ifndef HAL_SET_GDB_EXTRA_REGISTERS
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165 #define HAL_SET_GDB_EXTRA_REGISTERS( _regs_, _regval_ )
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166 #endif
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167
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168
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169 // Copy a set of registers from a HAL_SavedRegisters structure into a
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170 // GDB ordered array.
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171 #define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \
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172 { \
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173 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
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174 \
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175 _regval_[0] = (_regs_)->er0; \
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176 _regval_[1] = (_regs_)->er1; \
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177 _regval_[2] = (_regs_)->er2; \
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178 _regval_[3] = (_regs_)->er3; \
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179 _regval_[4] = (_regs_)->er4; \
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180 _regval_[5] = (_regs_)->er5; \
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181 _regval_[6] = (_regs_)->er6; \
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182 \
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183 _regval_[7] = (_regs_)->sp; \
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184 _regval_[8] = (_regs_)->ccr; \
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185 _regval_[9] = (_regs_)->pc & 0xffffff; \
208
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186 \
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187 HAL_GET_GDB_EXTRA_REGISTERS( _regval_, _regs_ ); \
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188 }
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189
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190 // Copy a GDB ordered array into a HAL_SavedRegisters structure.
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191 #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
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192 { \
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193 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
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194 \
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195 (_regs_)->er0 = _regval_[0]; \
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196 (_regs_)->er1 = _regval_[1]; \
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197 (_regs_)->er2 = _regval_[2]; \
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198 (_regs_)->er3 = _regval_[3]; \
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199 (_regs_)->er4 = _regval_[4]; \
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200 (_regs_)->er5 = _regval_[5]; \
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201 (_regs_)->er6 = _regval_[6]; \
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202 (_regs_)->sp = _regval_[7]; \
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203 (_regs_)->ccr = _regval_[8]; \
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204 (_regs_)->pc = (_regval_[9] & 0xffffff); \
208
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205 \
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206 /* We do not allow the SP or PSW to be set. Changing the SP will \
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207 * mess up the saved state. No PSW is saved on thread context \
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208 * switches, so there is nowhere to save it to. \
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209 */ \
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210 \
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211 HAL_SET_GDB_EXTRA_REGISTERS( _regs_, _regval_ ); \
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212 }
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213
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214 #ifndef CYGARC_HAL_GET_PC_REG
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215 #define CYGARC_HAL_GET_PC_REG(_regs_,_val_) ((_val_) = (_regs_)->pc & 0xffffff)
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216 #endif
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217
208
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218 //-------------------------------------------------------------------------
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219 // HAL setjmp
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220 // Note: These definitions are repeated in context.S. If changes are required
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221 // remember to update both sets.
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222
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223 #define CYGARC_JMP_BUF_SP 0
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224 #define CYGARC_JMP_BUF_ER3 1
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225 #define CYGARC_JMP_BUF_ER4 2
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226 #define CYGARC_JMP_BUF_ER5 3
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227 #define CYGARC_JMP_BUF_ER6 4
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228 #define CYGARC_JMP_BUF_PC 5
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229
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230 #define CYGARC_JMP_BUF_SIZE 6
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231
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232 typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE];
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233
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234 externC int hal_setjmp(hal_jmp_buf env);
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235 externC void hal_longjmp(hal_jmp_buf env, int val);
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236
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237 //-------------------------------------------------------------------------
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238 // Idle thread code.
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239 // This macro is called in the idle thread loop, and gives the HAL the
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240 // chance to insert code. Typical idle thread behaviour might be to halt the
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241 // processor.
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242
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243 externC void hal_idle_thread_action(cyg_uint32 loop_count);
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244
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245 #define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
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246
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247 //-----------------------------------------------------------------------------
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248 // Minimal and sensible stack sizes: the intention is that applications
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249 // will use these to provide a stack size in the first instance prior to
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250 // proper analysis. Idle thread stack should be this big.
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251
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252 // THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
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253 // THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
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254 // YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
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255
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256 // We define quite large stack needs for SPARClite, for it requires 576
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257 // bytes (144 words) to process an interrupt and thread-switch, and
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258 // momentarily, but needed in case of recursive interrupts, it needs 208
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259 // words - if a sequence of saves to push out other regsets is interrupted.
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260
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261 // This is not a config option because it should not be adjusted except
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262 // under "enough rope" sort of disclaimers.
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263
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264 // Worst case stack frame size: return link + 4 args + 4 pushed registers.
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265 #define CYGNUM_HAL_STACK_FRAME_SIZE (40)
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266
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267 // Stack needed for a context switch:
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268 #define CYGNUM_HAL_STACK_CONTEXT_SIZE (60)
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269
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270 // Interrupt + call to ISR, interrupt_end() and the DSR
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271 #define CYGNUM_HAL_STACK_INTERRUPT_SIZE (128)
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272
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273 #if 0 //def CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
208
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274
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275 // An interrupt stack which is large enough for all possible interrupt
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276 // conditions (and only used for that purpose) exists. "User" stacks
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277 // can be much smaller
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278
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279 #define CYGNUM_HAL_STACK_SIZE_MINIMUM (CYGNUM_HAL_STACK_CONTEXT_SIZE+ \
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280 CYGNUM_HAL_STACK_INTERRUPT_SIZE*2+ \
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281 CYGNUM_HAL_STACK_FRAME_SIZE*16)
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282 #define CYGNUM_HAL_STACK_SIZE_TYPICAL (2048)
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283
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284 #else // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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285
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286 // No separate interrupt stack exists. Make sure all threads contain
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287 // a stack sufficiently large.
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288
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289 #define CYGNUM_HAL_STACK_SIZE_MINIMUM (4096)
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290 #define CYGNUM_HAL_STACK_SIZE_TYPICAL (4096)
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291
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292 #endif
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293
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294 #define CYGARC_HAL_SAVE_GP()
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295 #define CYGARC_HAL_RESTORE_GP()
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296 //--------------------------------------------------------------------------
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297 #endif // CYGONCE_HAL_HAL_ARCH_H
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298 // EOF hal_arch.h