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* Added execute permissions to files missed in conversion from CVS
author alexs
date Mon, 12 Oct 2009 02:26:09 +0100
parents f9fb4fb63c6d
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 //==========================================================================
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2 //
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3 // plf_misc.c
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4 //
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5 // HAL platform miscellaneous functions
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6 //
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7 //==========================================================================
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8 //####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later version.
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16 //
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 // for more details.
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21 //
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22 // You should have received a copy of the GNU General Public License along
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23 // with eCos; if not, write to the Free Software Foundation, Inc.,
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 //
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26 // As a special exception, if other files instantiate templates or use macros
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27 // or inline functions from this file, or you compile this file and link it
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28 // with other works to produce a work based on this file, this file does not
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29 // by itself cause the resulting work to be covered by the GNU General Public
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30 // License. However the source code for this file must still be made available
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31 // in accordance with section (3) of the GNU General Public License.
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32 //
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33 // This exception does not invalidate any other reasons why a work based on
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34 // this file might be covered by the GNU General Public License.
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35 //
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36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 // at http://sources.redhat.com/ecos/ecos-license/
208
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38 // -------------------------------------------
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39 //####ECOSGPLCOPYRIGHTEND####
156
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40 //==========================================================================
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41 //#####DESCRIPTIONBEGIN####
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42 //
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43 // Author(s): nickg
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44 // Contributors: nickg, jlarmour, dmoseley
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45 // Date: 2000-06-06
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46 // Purpose: HAL miscellaneous functions
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47 // Description: This file contains miscellaneous functions provided by the
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48 // HAL.
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49 //
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50 //####DESCRIPTIONEND####
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51 //
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52 //========================================================================*/
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53
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54 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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55 #include <pkgconf/hal.h>
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56
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57 #include <cyg/infra/cyg_type.h> // Base types
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58 #include <cyg/infra/cyg_trac.h> // tracing macros
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59 #include <cyg/infra/cyg_ass.h> // assertion macros
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60
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61 #include <cyg/hal/hal_arch.h> // architectural definitions
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62
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63 #include <cyg/hal/hal_intr.h> // Interrupt handling
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64
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65 #include <cyg/hal/hal_cache.h> // Cache handling
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66
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67 #include <cyg/hal/hal_if.h>
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68
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69
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70 #if defined(CYGPKG_IO_PCI)
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71 #include <cyg/io/pci_hw.h>
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72 #include <cyg/io/pci.h>
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73 #endif
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74
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75 /*------------------------------------------------------------------------*/
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76
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77 #if defined(CYGPKG_CYGMON)
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78 #include CYGHWR_MEMORY_LAYOUT_H
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79 extern unsigned long cygmon_memsize;
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80 #endif
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81
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82 void hal_platform_init(void)
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83 {
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84 HAL_WRITE_UINT32(HAL_DISPLAY_LEDBAR, 0xff);
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85 #if defined(CYGPKG_CYGMON)
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86 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, ' ');
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87 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, 'C');
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88 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, 'Y');
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89 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, 'G');
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90 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, 'M');
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91 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, 'O');
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92 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, 'N');
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93 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' ');
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94 #elif defined(CYGPKG_REDBOOT)
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95 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, 'R');
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96 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, 'e');
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97 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, 'd');
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98 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, 'B');
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99 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, 'o');
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100 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, 'o');
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101 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, 't');
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102 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' ');
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103 #else
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104 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, ' ');
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105 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, ' ');
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106 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, 'e');
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107 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, 'C');
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108 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, 'o');
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109 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, 's');
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110 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, ' ');
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111 HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' ');
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112 #endif
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113
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114 // Set up eCos/ROM interfaces
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115 hal_if_init();
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116
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117 HAL_ICACHE_INVALIDATE_ALL();
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118 HAL_ICACHE_ENABLE();
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119 HAL_DCACHE_INVALIDATE_ALL();
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120 HAL_DCACHE_ENABLE();
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121
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122 #if defined(CYGPKG_CYGMON)
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123 {
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124 // Store the BSP memory info
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125 unsigned long * ram_real_base = (unsigned long *)0x80000000;
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126 unsigned long memsize = *ram_real_base;
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127 // Adjust memsize for the interrupt vectors reserved space
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128 memsize -= (CYGMEM_REGION_ram - (unsigned long)ram_real_base);
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129 cygmon_memsize = memsize;
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130 }
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131
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132 {
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133 //
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134 // Go ahead and enable IM[2] (ie HWInt[0]) so that we get interrupts
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135 // from the external devices. The device interrupts will still be
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136 // disabled in the CBUS FPGA interrupt controller, so this will not
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137 // cause spurious interrupts.
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138 // It is still up to the device drivers to enable the interrupts in
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139 // the interrupt controller
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140 //
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141 register unsigned long status;
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142 asm volatile (" mfc0 %0, $12" : "=r" (status) : );
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143 status |= SR_IBIT3;
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144 asm volatile (" mtc0 %0, $12" : : "r" (status));
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145 }
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146 #endif
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147 }
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148
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149
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150 /*------------------------------------------------------------------------*/
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151 /* Reset support */
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152
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153 void hal_atlas_reset(void)
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154 {
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155 *HAL_ATLAS_SOFTRES = HAL_ATLAS_GORESET;
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156 }
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157
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158 /*------------------------------------------------------------------------*/
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159 /* Syscall support */
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160 #ifdef CYGPKG_CYGMON
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161 // Cygmon provides syscall handling for this board
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162 #include <cyg/hal/hal_stub.h>
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163 int __get_syscall_num (void)
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164 {
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165 return SIGSYS;
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166 }
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167 #endif
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168
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169
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170 /*------------------------------------------------------------------------*/
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171 /* PCI support */
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172 #if defined(CYGPKG_IO_PCI)
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173
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174 #define PCIMEM_START 0x08000000 // PCI memory address
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175 #define PCIMEM_SIZE 0x10000000 // 256 MByte
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176 #define PCIIO_START 0x18000000 // PCI io address
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177 #define PCIIO_SIZE 0x03E00000 // 62 MByte
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178
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179 static int __check_bar(cyg_uint32 addr, cyg_uint32 size)
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180 {
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181 int n;
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182
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183 for (n = 0; n <= 31; n++)
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184 if (size == (1 << n)) {
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185 /* Check that address is naturally aligned */
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186 if (addr != (addr & ~(size-1)))
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187 return 0;
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188 return size - 1;
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189 }
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190 return 0;
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191 }
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192
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193
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194 // One-time PCI initialization.
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195
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196 void cyg_hal_plf_pci_init(void)
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197 {
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198 cyg_uint32 bar_ena, start10, start32, end, size;
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199 cyg_uint8 next_bus;
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200
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201 // Setup for bus mastering
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202 cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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203 CYG_PCI_CFG_COMMAND,
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204 CYG_PCI_CFG_COMMAND_IO |
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205 CYG_PCI_CFG_COMMAND_MEMORY |
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206 CYG_PCI_CFG_COMMAND_MASTER |
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207 CYG_PCI_CFG_COMMAND_PARITY |
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208 CYG_PCI_CFG_COMMAND_SERR);
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209
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210 // Setup latency timer field
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211 cyg_hal_plf_pci_cfg_write_byte(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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212 CYG_PCI_CFG_LATENCY_TIMER, 6);
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213
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214 // Disable all BARs
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215 bar_ena = 0x1ff;
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216
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217 // Check for active SCS10
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218 start10 = HAL_GALILEO_GETREG(HAL_GALILEO_SCS10_LD_OFFSET) << 21;
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219 end = ((HAL_GALILEO_GETREG(HAL_GALILEO_SCS10_HD_OFFSET) & 0x7f) + 1) << 21;
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220 if (end > start10) {
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221 if ((size = __check_bar(start10, end - start10)) != 0) {
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222 // Enable BAR
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223 HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_SCS10_SIZE_OFFSET, size);
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224 bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS10;
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225 }
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226 }
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227
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228 // Check for active SCS32
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229 start32 = HAL_GALILEO_GETREG(HAL_GALILEO_SCS32_LD_OFFSET) << 21;
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230 end = ((HAL_GALILEO_GETREG(HAL_GALILEO_SCS32_HD_OFFSET) & 0x7f) + 1) << 21;
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231 if (end > start32) {
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232 if ((size = __check_bar(start32, end - start32)) != 0) {
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233 // Enable BAR
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234 HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_SCS32_SIZE_OFFSET, size);
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235 bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS32;
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236 }
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237 }
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238
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239 bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS10;
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240 HAL_GALILEO_PUTREG(HAL_GALILEO_BAR_ENA_OFFSET, bar_ena);
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241
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242
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243 cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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244 CYG_PCI_CFG_BAR_0, 0xffffffff);
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245
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246 end = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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247 CYG_PCI_CFG_BAR_0);
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248
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249 cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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250 CYG_PCI_CFG_BAR_0, start10);
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251
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252
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253 cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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254 CYG_PCI_CFG_BAR_1, 0xffffffff);
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255
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256 end = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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257 CYG_PCI_CFG_BAR_1);
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258
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259 cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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260 CYG_PCI_CFG_BAR_1, start32);
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261
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262
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263 #if 0 // FIXME
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264
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265 // SAA9730 was previously initialized just enough to use I2C bus
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266 // during SDRAM configuration. We reset it here so generic PCI
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267 // library can deal with it.
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268 *((volatile unsigned *)(HAL_GALILEO_PCI0_MEM0_BASE + HAL_SAA9730_SYSRESET_OFFSET))
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269 = HAL_SAA9730_SYSRESET_ALL;
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270 #endif
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271
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272 // Configure PCI bus.
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273 next_bus = 1;
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274 cyg_pci_set_memory_base(CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_PCI_MEM0_BASE));
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275 cyg_pci_set_io_base(CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_PCI_IO_BASE));
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276 cyg_pci_configure_bus(0, &next_bus);
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277 }
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278
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279
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280 // Check for configuration error.
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281 static int pci_config_errcheck(void)
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282 {
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283 cyg_uint32 irq;
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284
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285 // Check for master or target abort
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286 irq = HAL_GALILEO_GETREG(HAL_GALILEO_IRQ_CAUSE_OFFSET);
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287
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288 if (irq & (HAL_GALILEO_IRQCAUSE_MASABT | HAL_GALILEO_IRQCAUSE_TARABT)) {
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289 // Error. Clear bits.
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290 HAL_GALILEO_PUTREG(HAL_GALILEO_IRQ_CAUSE_OFFSET,
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291 ~(HAL_GALILEO_IRQCAUSE_MASABT | HAL_GALILEO_IRQCAUSE_TARABT));
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292 return 1;
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293 }
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294 return 0;
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295 }
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296
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297 cyg_uint32 cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus,
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298 cyg_uint32 devfn,
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299 cyg_uint32 offset)
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300 {
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301 cyg_uint32 config_data;
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302
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303 HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
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304 HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
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305 (bus << 16) | (devfn << 8) | offset);
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306
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307 config_data = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
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308
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309 if (pci_config_errcheck())
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310 return 0xffffffff;
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311 return config_data;
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312 }
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313
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314 cyg_uint16 cyg_hal_plf_pci_cfg_read_word (cyg_uint32 bus,
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315 cyg_uint32 devfn,
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316 cyg_uint32 offset)
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317 {
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318 cyg_uint32 config_dword;
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319
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320 HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
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321 HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
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322 (bus << 16) | (devfn << 8) | (offset & ~3));
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323
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324 config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
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325
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326 if (pci_config_errcheck())
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327 return 0xffff;
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328 return (cyg_uint16)((config_dword >> ((offset & 3) * 8)) & 0xffff);
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329 }
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330
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331 cyg_uint8 cyg_hal_plf_pci_cfg_read_byte (cyg_uint32 bus,
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332 cyg_uint32 devfn,
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333 cyg_uint32 offset)
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334 {
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335 cyg_uint32 config_dword;
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336
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337 HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
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338 HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
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339 (bus << 16) | (devfn << 8) | (offset & ~3));
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340
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341 config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
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342
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343 if (pci_config_errcheck())
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344 return 0xff;
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345 return (cyg_uint8)((config_dword >> ((offset & 3) * 8)) & 0xff);
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346 }
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347
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348 void cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus,
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349 cyg_uint32 devfn,
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350 cyg_uint32 offset,
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351 cyg_uint32 data)
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352 {
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353 HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
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354 HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
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355 (bus << 16) | (devfn << 8) | offset);
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356
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357 HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, data);
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358
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359 (void)pci_config_errcheck();
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360 }
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361
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362 void cyg_hal_plf_pci_cfg_write_word (cyg_uint32 bus,
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363 cyg_uint32 devfn,
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364 cyg_uint32 offset,
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365 cyg_uint16 data)
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366 {
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367 cyg_uint32 config_dword, shift;
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368
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369 HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
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370 HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
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371 (bus << 16) | (devfn << 8) | (offset & ~3));
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372
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373 config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
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374 if (pci_config_errcheck())
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375 return;
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376
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377 shift = (offset & 3) * 8;
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378 config_dword &= ~(0xffff << shift);
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379 config_dword |= (data << shift);
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380
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381 HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, config_dword);
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382
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383 (void)pci_config_errcheck();
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384 }
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385
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386 void cyg_hal_plf_pci_cfg_write_byte (cyg_uint32 bus,
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387 cyg_uint32 devfn,
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388 cyg_uint32 offset,
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389 cyg_uint8 data)
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390 {
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391 cyg_uint32 config_dword, shift;
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392
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393 HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
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394 HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
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395 (bus << 16) | (devfn << 8) | (offset & ~3));
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396
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397 config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
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398 if (pci_config_errcheck())
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399 return;
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400
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401 shift = (offset & 3) * 8;
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402 config_dword &= ~(0xff << shift);
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403 config_dword |= (data << shift);
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404
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405 HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, config_dword);
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406
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407 (void)pci_config_errcheck();
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408 }
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409 #endif // defined(CYGPKG_IO_PCI)
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410
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411 /*------------------------------------------------------------------------*/
b939e9cada46 Merge from eCos master repository on 2001-03-29-21:44:39-BST
jlarmour
parents:
diff changeset
412 /* End of plf_misc.c */