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* Added execute permissions to files missed in conversion from CVS
author alexs
date Mon, 12 Oct 2009 02:26:09 +0100
parents d2c90368aeef
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1 #ifndef CYGONCE_PLF_IO_H
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2 #define CYGONCE_PLF_IO_H
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3
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4 //=============================================================================
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5 //
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6 // plf_io.h
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7 //
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8 // HAL platform device IO register support.
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9 //
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10 //=============================================================================
208
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
210
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40 // at http://sources.redhat.com/ecos/ecos-license/
208
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
134
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43 //=============================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): nickg
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47 // Contributors:nickg, jskov
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48 // Date: 2000-05-18
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49 // Purpose: Define IO register support
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50 // Description: The macros defined here provide the HAL APIs for handling
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51 // device IO control registers.
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52 //
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53 // Usage:
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54 // #include <cyg/hal/plf_io.h>
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55 // ...
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56 //
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57 //
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58 //####DESCRIPTIONEND####
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59 //
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60 //=============================================================================
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61
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62 #include <pkgconf/hal.h>
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63
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64 //-----------------------------------------------------------------------------
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65 // BYTE Register access.
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66 // Individual and vectorized access to 8 bit registers.
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67
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68 // Little-endian version
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69 #if (CYG_BYTEORDER == CYG_LSBFIRST)
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70
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71 #define HAL_READ_UINT8( _register_, _value_ ) \
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72 ((_value_) = *((volatile CYG_BYTE *)(_register_)))
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73
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74 #define HAL_WRITE_UINT8( _register_, _value_ ) \
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75 (*((volatile CYG_BYTE *)(_register_)) = (_value_))
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76
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77 #define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
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78 CYG_MACRO_START \
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79 cyg_count32 _i_,_j_; \
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80 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
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81 (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \
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82 CYG_MACRO_END
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83
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84 #define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
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85 CYG_MACRO_START \
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86 cyg_count32 _i_,_j_; \
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87 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
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88 ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \
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89 CYG_MACRO_END
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90
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91 #else // Big-endian version
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92
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93 #define HAL_READ_UINT8( _register_, _value_ ) \
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94 ((_value_) = *((volatile CYG_BYTE *)((CYG_ADDRWORD)(_register_)^3)))
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95
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96 #define HAL_WRITE_UINT8( _register_, _value_ ) \
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97 (*((volatile CYG_BYTE *)((CYG_ADDRWORD)(_register_)^3)) = (_value_))
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98
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99 #define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
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100 CYG_MACRO_START \
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101 cyg_count32 _i_,_j_; \
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102 volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
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103 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
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104 (_buf_)[_i_] = _r_[_j_]; \
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105 CYG_MACRO_END
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106
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107 #define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
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108 CYG_MACRO_START \
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109 cyg_count32 _i_,_j_; \
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110 volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
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111 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
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112 _r_[_j_] = (_buf_)[_i_]; \
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113 CYG_MACRO_END
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114
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115 #endif // Big-endian
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116
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117 //-----------------------------------------------------------------------------
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118 // 16 bit access.
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119 // Individual and vectorized access to 16 bit registers.
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120
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121 // Little-endian version
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122 #if (CYG_BYTEORDER == CYG_LSBFIRST)
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123
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124 #define HAL_READ_UINT16( _register_, _value_ ) \
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125 ((_value_) = *((volatile CYG_WORD16 *)(_register_)))
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126
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127 #define HAL_WRITE_UINT16( _register_, _value_ ) \
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128 (*((volatile CYG_WORD16 *)(_register_)) = (_value_))
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129
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130 #define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
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131 CYG_MACRO_START \
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132 cyg_count32 _i_,_j_; \
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133 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
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134 (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \
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135 CYG_MACRO_END
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136
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137 #define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
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138 CYG_MACRO_START \
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139 cyg_count32 _i_,_j_; \
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140 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
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141 ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \
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142 CYG_MACRO_END
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143
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144 #else // Big-endian version
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145
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146 #define HAL_READ_UINT16( _register_, _value_ ) \
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147 ((_value_) = *((volatile CYG_WORD16 *)((CYG_ADDRWORD)(_register_)^3)))
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148
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149 #define HAL_WRITE_UINT16( _register_, _value_ ) \
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150 (*((volatile CYG_WORD16 *)((CYG_ADDRWORD)(_register_)^3)) = (_value_))
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151
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152 #define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
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153 CYG_MACRO_START \
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154 cyg_count32 _i_,_j_; \
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155 volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
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156 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
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157 (_buf_)[_i_] = _r_[_j_]; \
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158 CYG_MACRO_END
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159
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160 #define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
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161 CYG_MACRO_START \
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162 cyg_count32 _i_,_j_; \
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163 volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
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164 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
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165 _r_[_j_] = (_buf_)[_i_]; \
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166 CYG_MACRO_END
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167
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168 #endif // Big-endian
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169
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170 //-----------------------------------------------------------------------------
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171 // 32 bit access.
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172 // Individual and vectorized access to 32 bit registers.
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173
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174 // Note: same macros for little- and big-endian systems.
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175
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176 #define HAL_READ_UINT32( _register_, _value_ ) \
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177 ((_value_) = *((volatile CYG_WORD32 *)(_register_)))
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178
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179 #define HAL_WRITE_UINT32( _register_, _value_ ) \
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180 (*((volatile CYG_WORD32 *)(_register_)) = (_value_))
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181
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182 #define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
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183 { \
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184 cyg_count32 _i_,_j_; \
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185 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
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186 (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \
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187 }
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188
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189 #define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
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190 { \
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191 cyg_count32 _i_,_j_; \
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192 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
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193 ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \
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194 }
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195
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196 #define HAL_IO_MACROS_DEFINED
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197
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198 //-----------------------------------------------------------------------------
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199 #endif // ifndef CYGONCE_HAL_PLF_IO_H
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200 // End of plf_io.h